Added #code to support define APIC_PIN0_TIMER.
This code ALWAYS runs the 8254 timer thru the 8259 ICU. It depricates the usage of "options SMP_TIMER_NC" in the config file.
This commit is contained in:
Steve Passe
parent
f5edb61526
commit
797cb61b54
@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.90 1997/07/18 03:59:28 fsmp Exp $
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* $Id: clock.c,v 1.91 1997/07/19 02:28:29 fsmp Exp $
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*/
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/*
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@ -66,7 +66,7 @@
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#include <machine/ipl.h>
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#ifdef APIC_IO
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#include <machine/smp.h>
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#include <machine/smptests.h> /** TEST_ALTTIMER */
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#include <machine/smptests.h> /** TEST_ALTTIMER, APIC_PIN0_TIMER */
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#endif /* APIC_IO */
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#include <i386/isa/icu.h>
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@ -874,12 +874,27 @@ cpu_initclocks()
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/* Finish initializing 8253 timer 0. */
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#ifdef APIC_IO
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#if 0
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#ifndef IO_ICU1
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#define IO_ICU1 0x20
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#endif /* IO_ICU1 */
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#endif /** 0 */
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#ifdef APIC_PIN0_TIMER
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/*
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* Allow 8254 timer to INTerrupt 8259:
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* re-initialize master 8259:
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* reset; prog 4 bytes, single ICU, edge triggered
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*/
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outb(IO_ICU1, 0x13);
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outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
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outb(IO_ICU1 + 1, 0x00); /* ignore slave */
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outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
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/* program IO APIC for type 3 INT on INT0 */
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if (ext_int_setup(0, 0) < 0)
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panic("8254 redirect via APIC pin0 impossible!");
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(IRQ0);
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#else /* APIC_PIN0_TIMER */
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/* 8254 is traditionally on ISA IRQ0 */
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if ((x = isa_apic_pin(0)) < 0) {
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/* bummer, attempt to redirect thru the 8259 */
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@ -917,7 +932,8 @@ cpu_initclocks()
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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#else
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#endif /* APIC_PIN0_TIMER */
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#else /* APIC_IO */
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.90 1997/07/18 03:59:28 fsmp Exp $
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* $Id: clock.c,v 1.91 1997/07/19 02:28:29 fsmp Exp $
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*/
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/*
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@ -66,7 +66,7 @@
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#include <machine/ipl.h>
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#ifdef APIC_IO
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#include <machine/smp.h>
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#include <machine/smptests.h> /** TEST_ALTTIMER */
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#include <machine/smptests.h> /** TEST_ALTTIMER, APIC_PIN0_TIMER */
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#endif /* APIC_IO */
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#include <i386/isa/icu.h>
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@ -874,12 +874,27 @@ cpu_initclocks()
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/* Finish initializing 8253 timer 0. */
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#ifdef APIC_IO
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#if 0
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#ifndef IO_ICU1
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#define IO_ICU1 0x20
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#endif /* IO_ICU1 */
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#endif /** 0 */
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#ifdef APIC_PIN0_TIMER
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/*
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* Allow 8254 timer to INTerrupt 8259:
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* re-initialize master 8259:
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* reset; prog 4 bytes, single ICU, edge triggered
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*/
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outb(IO_ICU1, 0x13);
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outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
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outb(IO_ICU1 + 1, 0x00); /* ignore slave */
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outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
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/* program IO APIC for type 3 INT on INT0 */
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if (ext_int_setup(0, 0) < 0)
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panic("8254 redirect via APIC pin0 impossible!");
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(IRQ0);
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#else /* APIC_PIN0_TIMER */
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/* 8254 is traditionally on ISA IRQ0 */
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if ((x = isa_apic_pin(0)) < 0) {
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/* bummer, attempt to redirect thru the 8259 */
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@ -917,7 +932,8 @@ cpu_initclocks()
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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#else
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#endif /* APIC_PIN0_TIMER */
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#else /* APIC_IO */
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.90 1997/07/18 03:59:28 fsmp Exp $
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* $Id: clock.c,v 1.91 1997/07/19 02:28:29 fsmp Exp $
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*/
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/*
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@ -66,7 +66,7 @@
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#include <machine/ipl.h>
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#ifdef APIC_IO
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#include <machine/smp.h>
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#include <machine/smptests.h> /** TEST_ALTTIMER */
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#include <machine/smptests.h> /** TEST_ALTTIMER, APIC_PIN0_TIMER */
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#endif /* APIC_IO */
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#include <i386/isa/icu.h>
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@ -874,12 +874,27 @@ cpu_initclocks()
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/* Finish initializing 8253 timer 0. */
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#ifdef APIC_IO
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#if 0
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#ifndef IO_ICU1
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#define IO_ICU1 0x20
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#endif /* IO_ICU1 */
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#endif /** 0 */
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#ifdef APIC_PIN0_TIMER
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/*
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* Allow 8254 timer to INTerrupt 8259:
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* re-initialize master 8259:
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* reset; prog 4 bytes, single ICU, edge triggered
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*/
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outb(IO_ICU1, 0x13);
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outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
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outb(IO_ICU1 + 1, 0x00); /* ignore slave */
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outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
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/* program IO APIC for type 3 INT on INT0 */
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if (ext_int_setup(0, 0) < 0)
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panic("8254 redirect via APIC pin0 impossible!");
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(IRQ0);
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#else /* APIC_PIN0_TIMER */
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/* 8254 is traditionally on ISA IRQ0 */
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if ((x = isa_apic_pin(0)) < 0) {
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/* bummer, attempt to redirect thru the 8259 */
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@ -917,7 +932,8 @@ cpu_initclocks()
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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#else
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#endif /* APIC_PIN0_TIMER */
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#else /* APIC_IO */
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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@ -22,12 +22,17 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: apic_ipl.s,v 1.1 1997/07/18 22:54:17 smp Exp smp $
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* $Id: apic_ipl.s,v 1.2 1997/07/19 02:28:29 fsmp Exp $
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*/
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#ifdef APIC_IO
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#include <machine/smptests.h> /** APIC_PIN0_TIMER */
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#endif /* APIC_IO */
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.data
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ALIGN_DATA
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#ifndef APIC_PIN0_TIMER
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/* this allows us to change the 8254 APIC pin# assignment */
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.globl _Xintr8254
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_Xintr8254:
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@ -37,6 +42,7 @@ _Xintr8254:
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.globl _mask8254
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_mask8254:
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.long 0
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#endif /* APIC_PIN0_TIMER */
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#ifdef DO_RTC_VEC
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/** XXX FIXME: remove me after several weeks of no problems */
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@ -76,6 +82,17 @@ _vec:
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* generic vector function for 8254 clock
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*/
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ALIGN_TEXT
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#ifdef APIC_PIN0_TIMER
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vec0:
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popl %eax /* return address */
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pushfl
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pushl $KCSEL
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pushl %eax
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cli
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andl $~IRQ_BIT(0), iactive ; /* lazy masking */
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MEXITCOUNT
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jmp _Xintr0 /* XXX might need _Xfastintr0 */
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#else
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.globl _vec8254
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_vec8254:
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popl %eax /* return address */
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@ -83,12 +100,14 @@ _vec8254:
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pushl $KCSEL
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pushl %eax
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cli
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movl _mask8254,%eax /* lazy masking */
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movl _mask8254, %eax /* lazy masking */
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notl %eax
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andl %eax,iactive
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andl %eax, iactive
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MEXITCOUNT
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movl _Xintr8254, %eax
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jmp %eax /* XXX might need _Xfastintr# */
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#endif /* APIC_PIN0_TIMER */
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/*
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* generic vector function for RTC clock
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@ -142,7 +161,9 @@ __CONCAT(vec,irq_num): ; \
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jmp __CONCAT(_Xintr,irq_num)
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BUILD_VEC(0) /* NOT specific in IO APIC hardware */
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#ifndef APIC_PIN0_TIMER
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BUILD_VEC(0)
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#endif /* APIC_PIN0_TIMER */
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BUILD_VEC(1)
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BUILD_VEC(2)
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BUILD_VEC(3)
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.90 1997/07/18 03:59:28 fsmp Exp $
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* $Id: clock.c,v 1.91 1997/07/19 02:28:29 fsmp Exp $
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*/
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/*
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@ -66,7 +66,7 @@
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#include <machine/ipl.h>
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#ifdef APIC_IO
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#include <machine/smp.h>
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#include <machine/smptests.h> /** TEST_ALTTIMER */
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#include <machine/smptests.h> /** TEST_ALTTIMER, APIC_PIN0_TIMER */
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#endif /* APIC_IO */
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#include <i386/isa/icu.h>
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@ -874,12 +874,27 @@ cpu_initclocks()
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/* Finish initializing 8253 timer 0. */
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#ifdef APIC_IO
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#if 0
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#ifndef IO_ICU1
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#define IO_ICU1 0x20
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#endif /* IO_ICU1 */
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#endif /** 0 */
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#ifdef APIC_PIN0_TIMER
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/*
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* Allow 8254 timer to INTerrupt 8259:
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* re-initialize master 8259:
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* reset; prog 4 bytes, single ICU, edge triggered
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*/
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outb(IO_ICU1, 0x13);
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outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
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outb(IO_ICU1 + 1, 0x00); /* ignore slave */
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outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
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/* program IO APIC for type 3 INT on INT0 */
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if (ext_int_setup(0, 0) < 0)
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panic("8254 redirect via APIC pin0 impossible!");
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(IRQ0);
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#else /* APIC_PIN0_TIMER */
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/* 8254 is traditionally on ISA IRQ0 */
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if ((x = isa_apic_pin(0)) < 0) {
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/* bummer, attempt to redirect thru the 8259 */
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@ -917,7 +932,8 @@ cpu_initclocks()
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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#else
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#endif /* APIC_PIN0_TIMER */
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#else /* APIC_IO */
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.90 1997/07/18 03:59:28 fsmp Exp $
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* $Id: clock.c,v 1.91 1997/07/19 02:28:29 fsmp Exp $
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*/
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/*
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@ -66,7 +66,7 @@
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#include <machine/ipl.h>
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#ifdef APIC_IO
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#include <machine/smp.h>
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#include <machine/smptests.h> /** TEST_ALTTIMER */
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#include <machine/smptests.h> /** TEST_ALTTIMER, APIC_PIN0_TIMER */
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#endif /* APIC_IO */
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#include <i386/isa/icu.h>
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@ -874,12 +874,27 @@ cpu_initclocks()
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/* Finish initializing 8253 timer 0. */
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#ifdef APIC_IO
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#if 0
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#ifndef IO_ICU1
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#define IO_ICU1 0x20
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#endif /* IO_ICU1 */
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#endif /** 0 */
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#ifdef APIC_PIN0_TIMER
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/*
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* Allow 8254 timer to INTerrupt 8259:
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* re-initialize master 8259:
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* reset; prog 4 bytes, single ICU, edge triggered
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*/
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outb(IO_ICU1, 0x13);
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outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
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outb(IO_ICU1 + 1, 0x00); /* ignore slave */
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outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
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/* program IO APIC for type 3 INT on INT0 */
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if (ext_int_setup(0, 0) < 0)
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panic("8254 redirect via APIC pin0 impossible!");
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(IRQ0);
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#else /* APIC_PIN0_TIMER */
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/* 8254 is traditionally on ISA IRQ0 */
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if ((x = isa_apic_pin(0)) < 0) {
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/* bummer, attempt to redirect thru the 8259 */
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@ -917,7 +932,8 @@ cpu_initclocks()
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(mask8254);
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#else
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#endif /* APIC_PIN0_TIMER */
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#else /* APIC_IO */
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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