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NTB: MFV 87034511: Correct Number of Scratch Pad Registers

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The NTB Xeon hardware has 16 scratch pad registers and 16 back-to-back
scratch pad registers.  Correct the #define to represent this and update
the variable names to reflect their usage.

Authored by:	Jon Mason
Obtained from:	Linux
Sponsored by:	EMC / Isilon Storage Division
This commit is contained in:
Conrad Meyer 2015-10-13 03:10:04 +00:00
parent 4052b8bc34
commit 7a97964b79
1 changed files with 1 additions and 1 deletions
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2
sys/dev/ntb/ntb_hw/ntb_regs.h
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@ -37,7 +37,7 @@
#define XEON_MSIX_CNT 4
#define XEON_MAX_SPADS 16
#define XEON_MAX_COMPAT_SPADS 8
#define XEON_MAX_COMPAT_SPADS 16
/* Reserve the uppermost bit for link interrupt */
#define XEON_MAX_DB_BITS 15
#define XEON_DB_BITS_PER_VEC 5