PowerPC common SMP startup and time base rework.
- make mftb() shared, rewrite in C, provide complementary mttb() - adjust SMP startup per the above, additional comments, minor naming changes - eliminate redundant TB defines, other minor cosmetics Reviewed by: marcel, nwhitehorn Obtained from: Freescale, Semihalf
This commit is contained in:
Rafal Jaworowski
parent
95b0b37cfc
commit
7ad9c533ef
@ -148,6 +148,14 @@ decr_init(void)
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mtmsr(msr);
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}
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#ifdef SMP
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void
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decr_ap_init(void)
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{
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}
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#endif
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void
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decr_tc_init(void)
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{
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@ -155,17 +163,6 @@ decr_tc_init(void)
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tc_init(&decr_timecounter);
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}
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static __inline u_quad_t
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mftb(void)
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{
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u_long scratch;
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u_quad_t tb;
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__asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw 0,%0,%1; bne 1b"
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: "=r"(tb), "=r"(scratch));
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return tb;
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}
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static unsigned
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decr_get_timecount(struct timecounter *tc)
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{
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@ -151,22 +151,6 @@ decr_init (void)
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mtmsr(msr);
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}
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static __inline u_quad_t
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mftb (void)
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{
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u_long scratch;
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u_quad_t tb;
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__asm__ __volatile__(
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"1: mftbu %0;"
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" mftb %0+1;"
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" mftbu %1;"
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" cmpw 0,%0,%1;"
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" bne 1b"
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: "=r"(tb), "=r"(scratch));
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return tb;
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}
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void
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decr_tc_init(void)
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{
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@ -115,13 +115,37 @@ mfdec(void)
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static __inline register_t
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mfpvr(void)
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{
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register_t value;
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register_t value;
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__asm __volatile ("mfpvr %0" : "=r"(value));
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return (value);
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}
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static __inline u_quad_t
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mftb(void)
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{
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u_quad_t tb;
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uint32_t *tbup = (uint32_t *)&tb;
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uint32_t *tblp = tbup + 1;
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do {
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*tbup = mfspr(TBR_TBU);
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*tblp = mfspr(TBR_TBL);
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} while (*tbup != mfspr(TBR_TBU));
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return (tb);
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}
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static __inline void
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mttb(u_quad_t time)
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{
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mtspr(TBR_TBWL, 0);
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mtspr(TBR_TBWU, (uint32_t)(time >> 32));
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mtspr(TBR_TBWL, (uint32_t)(time & 0xffffffff));
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}
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static __inline void
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eieio(void)
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{
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@ -56,11 +56,12 @@ int is_physical_memory(vm_offset_t addr);
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int mem_valid(vm_offset_t addr, int len);
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void decr_init(void);
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void decr_ap_init(void);
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void decr_tc_init(void);
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void cpu_setup(u_int);
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struct trapframe;
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struct trapframe;
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void powerpc_interrupt(struct trapframe *);
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#endif /* !_MACHINE_MD_VAR_H_ */
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@ -129,8 +129,6 @@
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#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */
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#define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */
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#define SPR_EAR 0x11a /* .68 External Access Register */
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#define SPR_TBL 0x11c /* 468 Time Base Lower */
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#define SPR_TBU 0x11d /* 468 Time Base Upper */
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#define SPR_PVR 0x11f /* 468 Processor Version Register */
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#define MPC601 0x0001
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#define MPC603 0x0003
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@ -30,6 +30,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/bus.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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@ -40,6 +41,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/cpu.h>
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#include <machine/intr_machdep.h>
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#include <machine/platform.h>
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#include <machine/md_var.h>
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#include <machine/smp.h>
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#include "pic_if.h"
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@ -47,30 +49,35 @@ __FBSDID("$FreeBSD$");
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extern struct pcpu __pcpu[MAXCPU];
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volatile static int ap_awake;
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volatile static u_int ap_state;
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volatile static u_int ap_letgo;
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volatile static uint32_t ap_decr;
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volatile static uint32_t ap_tbl;
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volatile static u_quad_t ap_timebase;
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static u_int ipi_msg_cnt[32];
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void
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machdep_ap_bootstrap(void)
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{
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pcpup->pc_awake = 1;
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PCPU_SET(pir, mfspr(SPR_PIR));
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PCPU_SET(awake, 1);
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__asm __volatile("msync; isync");
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while (ap_state == 0)
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while (ap_letgo == 0)
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;
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mtspr(SPR_TBL, 0);
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mtspr(SPR_TBU, 0);
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mtspr(SPR_TBL, ap_tbl);
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/* Initialize DEC and TB, sync with the BSP values */
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decr_ap_init();
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mttb(ap_timebase);
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__asm __volatile("mtdec %0" :: "r"(ap_decr));
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ap_awake++;
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atomic_add_int(&ap_awake, 1);
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CTR1(KTR_SMP, "SMP: AP CPU%d launched", PCPU_GET(cpuid));
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/* Initialize curthread. */
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/* Initialize curthread */
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PCPU_SET(curthread, PCPU_GET(idlethread));
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PCPU_SET(curpcb, curthread->td_pcb);
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/* Let the DEC and external interrupts go */
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mtmsr(mfmsr() | PSL_EE);
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sched_throw(NULL);
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}
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@ -149,8 +156,7 @@ cpu_mp_start(void)
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pc->pc_cpumask = 1 << pc->pc_cpuid;
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pc->pc_hwref = cpu.cr_hwref;
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all_cpus |= pc->pc_cpumask;
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next:
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next:
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error = platform_smp_next_cpu(&cpu);
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}
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}
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@ -176,7 +182,7 @@ static void
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cpu_mp_unleash(void *dummy)
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{
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struct pcpu *pc;
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int cpus;
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int cpus, timeout;
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if (mp_ncpus <= 1)
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return;
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@ -187,35 +193,47 @@ cpu_mp_unleash(void *dummy)
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cpus++;
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pc->pc_other_cpus = all_cpus & ~pc->pc_cpumask;
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if (!pc->pc_bsp) {
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printf("Waking up CPU %d (dev=%x)\n", pc->pc_cpuid,
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pc->pc_hwref);
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if (bootverbose)
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printf("Waking up CPU %d (dev=%x)\n",
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pc->pc_cpuid, pc->pc_hwref);
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platform_smp_start_cpu(pc);
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timeout = 2000; /* wait 2sec for the AP */
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while (!pc->pc_awake && --timeout > 0)
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DELAY(1000);
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} else {
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__asm __volatile("mfspr %0,1023" : "=r"(pc->pc_pir));
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PCPU_SET(pir, mfspr(SPR_PIR));
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pc->pc_awake = 1;
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}
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if (pc->pc_awake)
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if (pc->pc_awake) {
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if (bootverbose)
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printf("Adding CPU %d, pir=%x, awake=%x\n",
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pc->pc_cpuid, pc->pc_pir, pc->pc_awake);
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smp_cpus++;
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} else
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stopped_cpus |= (1 << pc->pc_cpuid);
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}
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ap_awake = 1;
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__asm __volatile("mftb %0" : "=r"(ap_tbl));
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ap_tbl += 10;
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/* Provide our current DEC and TB values for APs */
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__asm __volatile("mfdec %0" : "=r"(ap_decr));
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ap_state++;
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powerpc_sync();
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ap_timebase = mftb() + 10;
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__asm __volatile("msync; isync");
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/* Let APs continue */
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atomic_store_rel_int(&ap_letgo, 1);
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mtspr(SPR_TBL, 0);
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mtspr(SPR_TBU, 0);
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mtspr(SPR_TBL, ap_tbl);
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mttb(ap_timebase);
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while (ap_awake < smp_cpus)
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;
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if (smp_cpus != cpus || cpus != mp_ncpus) {
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printf("SMP: %d CPUs found; %d CPUs usable; %d CPUs woken\n",
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mp_ncpus, cpus, smp_cpus);
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mp_ncpus, cpus, smp_cpus);
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}
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smp_active = 1;
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@ -224,8 +242,6 @@ cpu_mp_unleash(void *dummy)
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SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, cpu_mp_unleash, NULL);
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static u_int ipi_msg_cnt[32];
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int
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powerpc_ipi_handler(void *arg)
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{
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