- Add a workaround for a bug in BlackBird CPUs (said to be part of the
SpitFire erratum #54) which can cause writes to the TICK_CMPR register to fail. This seems to fix the dying clocks problem reported by jhb@ and kris@. [1] - In tick_start() don't reset the tick counter of the boot processor to zero. It's initially reset in _start() and afterwards but _before_ tick_start() is called on the BSP the APs synchronise with the tick counter of the BSP in mp_startup(). Resetting the tick counter of the BSP in tick_start() probably also was the cause of problems seen when using the CPU tick counter as timecounter on SMP machines. Not resetting the tick counter of the BSP in mp_startup() makes the tick counters and tick interrupts between the BSP and APs be pretty much in sync as it's supposed to be. This also means there's no longer a real reason to have separate tick_start() and tick_start_ap() so merge them and zap tick_start_ap(). This is also a first step in simplifying the interface to the tick counters in preparation to use alternate clock hardware where available. - Switch to the algorithm used on FreeBSD/ia64 for updating the tick interrupt register and which compensates the clock drift caused by varying delays between when the tick interrupts actually trigger and when they are serviced. Not compensating the clock drift mainly hurts interactive performance especially when using WITNESS. [2] For further information about the algorithm also see the commit log of sys/ia64/ia64/interrupt.c rev. 1.38. On sparc64 the sysctls for monitoring the behaviour of the tick interrupts are machdep.tick.adjust_edges, machdep.tick.adjust_excess, machdep.tick.adjust_missed and machdep.tick.adjust_ticks. - In tick_init() just use tick_stop() for stopping the tick interrupts until a proper handler is set up later. This also stops the system tick interrupt on USIII systems earlier. - In tick_start() check for a rough upper limit of HZ. - Some minor changes, e.g. use FBSDID, remove unused headers, etc. Info obtained from: Linux [1] Ok'ed by: marcel [2] Additional testing by: kris (earlier version of the workaround), jhb X-MFC after: 3 days [1]
This commit is contained in:
Marius Strobl
parent
c066bca62d
commit
7bed9b320b
@ -171,6 +171,23 @@ int fasword32(u_long asi, void *addr, uint32_t *val);
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: : "r" (val), "rI" (xor)); \
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} while (0)
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/*
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* Macro intended to be used instead of wr(asr23, val, xor) for writing to
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* the TICK_CMPR register in order to avoid a bug in BlackBird CPUs that
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* can cause these writes to fail under certain condidtions which in turn
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* causes the hardclock to stop. The workaround is to perform the write
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* at the beginning of an I-Cache line directly followed by a dummy read.
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*/
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#define wrtickcmpr(val, xor) ({ \
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__asm __volatile( \
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" ba,pt %%xcc, 1f ; " \
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" nop ; " \
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" .align 64 ; " \
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"1: wr %0, %1, %%asr23 ; " \
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" rd %%asr23, %%g0 ; " \
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: : "r" (val), "rI" (xor)); \
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})
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static __inline void
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breakpoint(void)
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{
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@ -51,6 +51,8 @@ struct pmap;
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struct intr_request *pc_irfree; \
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struct pmap *pc_pmap; \
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vm_offset_t pc_addr; \
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u_long pc_tickref; \
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u_long pc_tickadj; \
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u_int pc_mid; \
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u_int pc_node; \
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u_int pc_tlb_ctx; \
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@ -29,15 +29,8 @@
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#ifndef _MACHINE_TICK_H_
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#define _MACHINE_TICK_H_
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typedef void tick_func_t(struct clockframe *);
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void tick_init(u_long clock);
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void tick_start(tick_func_t *func);
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#ifdef SMP
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void tick_start_ap(void);
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#endif
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void tick_start(void);
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void tick_stop(void);
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tick_func_t tick_hardclock;
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#endif
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@ -51,10 +51,11 @@
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/lock.h>
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@ -342,7 +343,7 @@ cpu_mp_bootstrap(struct pcpu *pc)
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csa = &cpu_start_args;
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pmap_map_tsb();
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cpu_setregs(pc);
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tick_start_ap();
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tick_start();
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smp_cpus++;
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KASSERT(curthread != NULL, ("cpu_mp_bootstrap: curthread"));
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@ -22,44 +22,54 @@
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/pcpu.h>
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#include <sys/sysctl.h>
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#include <sys/timetc.h>
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#ifdef SMP
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#include <sys/ktr.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#endif
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#include <dev/ofw/openfirm.h>
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#include <machine/clock.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/tick.h>
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#include <machine/ver.h>
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#ifdef SMP
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#include <machine/cpu.h>
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#endif
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int tick_missed; /* statistics */
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#define TICK_GRACE 10000
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SYSCTL_NODE(_machdep, OID_AUTO, tick, CTLFLAG_RD, 0, "tick statistics");
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static int adjust_edges = 0;
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SYSCTL_INT(_machdep_tick, OID_AUTO, adjust_edges, CTLFLAG_RD, &adjust_edges,
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0, "total number of times tick interrupts got more than 12.5% behind");
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static int adjust_excess = 0;
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SYSCTL_INT(_machdep_tick, OID_AUTO, adjust_excess, CTLFLAG_RD, &adjust_excess,
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0, "total number of ignored tick interrupts");
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static int adjust_missed = 0;
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SYSCTL_INT(_machdep_tick, OID_AUTO, adjust_missed, CTLFLAG_RD, &adjust_missed,
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0, "total number of missed tick interrupts");
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static int adjust_ticks = 0;
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SYSCTL_INT(_machdep_tick, OID_AUTO, adjust_ticks, CTLFLAG_RD, &adjust_ticks,
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0, "total number of tick interrupts with adjustment");
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static void tick_hardclock(struct clockframe *);
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void
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cpu_initclocks(void)
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{
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stathz = hz;
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tick_start(tick_hardclock);
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tick_start();
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}
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static __inline void
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@ -75,72 +85,100 @@ tick_process(struct clockframe *cf)
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statclock(cf);
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}
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void
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static void
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tick_hardclock(struct clockframe *cf)
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{
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int missed;
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u_long next;
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register_t i;
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u_long adj, s, tick, ref;
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long delta;
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int count;
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tick_process(cf);
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/*
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* Avoid stopping of hardclock in case we missed one tick period by
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* ensuring that the the value of the next tick is at least TICK_GRACE
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* ticks in the future.
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* Missed ticks need to be accounted for by repeatedly calling
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* hardclock.
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* The sequence of reading the TICK register, calculating the value
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* of the next tick and writing it to the TICK_CMPR register must not
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* be interrupted, not even by an IPI, otherwise a value that is in
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* the past could be written in the worst case, causing hardclock to
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* stop.
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*/
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missed = 0;
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next = rd(asr23) + tick_increment;
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i = intr_disable();
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while (next < rd(tick) + TICK_GRACE) {
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next += tick_increment;
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missed++;
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}
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wr(asr23, next, 0);
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intr_restore(i);
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atomic_add_int(&tick_missed, missed);
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for (; missed > 0; missed--)
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adj = PCPU_GET(tickadj);
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s = intr_disable();
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tick = rd(tick);
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wrtickcmpr(tick + tick_increment - adj, 0);
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intr_restore(s);
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ref = PCPU_GET(tickref);
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delta = tick - ref;
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count = 0;
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while (delta >= tick_increment) {
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tick_process(cf);
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delta -= tick_increment;
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ref += tick_increment;
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if (adj != 0)
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adjust_ticks++;
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count++;
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}
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if (count > 0) {
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adjust_missed += count - 1;
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if (delta > (tick_increment >> 3)) {
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if (adj == 0)
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adjust_edges++;
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adj = tick_increment >> 4;
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} else
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adj = 0;
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} else {
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adj = 0;
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adjust_excess++;
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}
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PCPU_SET(tickref, ref);
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PCPU_SET(tickadj, adj);
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}
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void
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tick_init(u_long clock)
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{
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tick_freq = clock;
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tick_MHz = clock / 1000000;
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tick_increment = clock / hz;
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/*
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* Avoid stopping of hardclock in terms of a lost tick interrupt
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* by ensuring that the tick period is at least TICK_GRACE ticks.
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*/
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if (tick_increment < TICK_GRACE)
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panic("%s: HZ to high, decrease to at least %ld", __func__,
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clock / TICK_GRACE);
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/*
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* UltraSparc II[e,i] based systems come up with the tick interrupt
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* enabled and a handler that resets the tick counter, causing DELAY()
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* to not work properly when used early in boot.
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* UltraSPARC III based systems come up with the system tick interrupt
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* enabled, causing an interrupt storm on startup since they are not
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* handled.
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*/
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wr(asr23, 1L << 63, 0);
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tick_stop();
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}
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void
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tick_start(tick_func_t *func)
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tick_start(void)
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{
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intr_setup(PIL_TICK, (ih_func_t *)func, -1, NULL, NULL);
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wrpr(tick, 0, 0);
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wr(asr23, tick_increment, 0);
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}
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u_long base, s;
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#ifdef SMP
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void
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tick_start_ap(void)
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{
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u_long base;
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if (PCPU_GET(cpuid) == 0)
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intr_setup(PIL_TICK, (ih_func_t *)tick_hardclock, -1, NULL,
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NULL);
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/*
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* Try to make the ticks interrupt as synchronously as possible to
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* avoid inaccuracies for migrating processes. Leave out one tick to
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* make sure that it is not missed.
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* Try to make the tick interrupts as synchronously as possible on
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* all CPUs to avoid inaccuracies for migrating processes. Leave out
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* one tick to make sure that it is not missed.
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*/
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PCPU_SET(tickadj, 0);
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s = intr_disable();
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base = rd(tick);
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wr(asr23, roundup(base, tick_increment) + tick_increment, 0);
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base = roundup(base, tick_increment);
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PCPU_SET(tickref, base);
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wrtickcmpr(base + tick_increment, 0);
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intr_restore(s);
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}
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#endif
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void
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tick_stop(void)
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@ -148,5 +186,5 @@ tick_stop(void)
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if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
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wr(asr24, 1L << 63, 0);
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wr(asr23, 1L << 63, 0);
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wrtickcmpr(1L << 63, 0);
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}
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