Define the uart clocks so that they can be en/disabled at runtime.
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@ -62,9 +62,14 @@ __FBSDID("$FreeBSD$");
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#define CM_PER_LCDC_CLKCTRL (CM_PER + 0x018)
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#define CM_PER_USB0_CLKCTRL (CM_PER + 0x01C)
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#define CM_PER_TPTC0_CLKCTRL (CM_PER + 0x024)
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#define CM_PER_UART5_CLKCTRL (CM_PER + 0x038)
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#define CM_PER_MMC0_CLKCTRL (CM_PER + 0x03C)
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#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x044)
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#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x048)
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#define CM_PER_UART1_CLKCTRL (CM_PER + 0x06C)
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#define CM_PER_UART2_CLKCTRL (CM_PER + 0x070)
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#define CM_PER_UART3_CLKCTRL (CM_PER + 0x074)
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#define CM_PER_UART4_CLKCTRL (CM_PER + 0x078)
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#define CM_PER_TIMER7_CLKCTRL (CM_PER + 0x07C)
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#define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x080)
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#define CM_PER_TIMER3_CLKCTRL (CM_PER + 0x084)
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@ -146,6 +151,9 @@ static int am335x_clk_musb0_activate(struct ti_clock_dev *clkdev);
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static int am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev);
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static int am335x_clk_pruss_activate(struct ti_clock_dev *clkdev);
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#define AM335X_NOOP_CLOCK_DEV(i) \
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{ .id = (i) }
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#define AM335X_GENERIC_CLOCK_DEV(i) \
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{ .id = (i), \
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.clk_activate = am335x_clk_generic_activate, \
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@ -217,6 +225,14 @@ struct ti_clock_dev ti_clk_devmap[] = {
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.clk_get_source_freq = am335x_clk_get_arm_disp_freq,
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},
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/* UART. Uart0 clock cannot be controlled. */
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AM335X_NOOP_CLOCK_DEV(UART0_CLK),
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AM335X_GENERIC_CLOCK_DEV(UART1_CLK),
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AM335X_GENERIC_CLOCK_DEV(UART2_CLK),
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AM335X_GENERIC_CLOCK_DEV(UART3_CLK),
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AM335X_GENERIC_CLOCK_DEV(UART4_CLK),
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AM335X_GENERIC_CLOCK_DEV(UART5_CLK),
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/* DMTimer */
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AM335X_GENERIC_CLOCK_DEV(DMTIMER2_CLK),
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AM335X_GENERIC_CLOCK_DEV(DMTIMER3_CLK),
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@ -286,6 +302,14 @@ struct am335x_clk_details {
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static struct am335x_clk_details g_am335x_clk_details[] = {
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/* UART. UART0 clock not controllable. */
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_CLK_DETAIL(UART0_CLK, 0, 0),
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_CLK_DETAIL(UART1_CLK, CM_PER_UART1_CLKCTRL, 0),
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_CLK_DETAIL(UART2_CLK, CM_PER_UART2_CLKCTRL, 0),
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_CLK_DETAIL(UART3_CLK, CM_PER_UART3_CLKCTRL, 0),
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_CLK_DETAIL(UART4_CLK, CM_PER_UART4_CLKCTRL, 0),
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_CLK_DETAIL(UART5_CLK, CM_PER_UART5_CLKCTRL, 0),
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/* DMTimer modules */
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_CLK_DETAIL(DMTIMER2_CLK, CM_PER_TIMER2_CLKCTRL, CLKSEL_TIMER2_CLK),
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_CLK_DETAIL(DMTIMER3_CLK, CM_PER_TIMER3_CLKCTRL, CLKSEL_TIMER3_CLK),
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@ -81,10 +81,15 @@ typedef enum {
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USBP2_HSIC_CLK,
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/* UART modules */
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UART1_CLK = 400,
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UART0_CLK = 400,
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UART1_CLK,
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UART2_CLK,
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UART3_CLK,
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UART4_CLK,
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UART5_CLK,
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UART6_CLK,
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UART7_CLK,
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UART8_CLK,
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/* General purpose timer modules */
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GPTIMER1_CLK = 500,
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