Define the uart clocks so that they can be en/disabled at runtime.

This commit is contained in:
ian 2013-08-21 04:20:17 +00:00
parent bd47afb289
commit 7d7f7f1bb2
2 changed files with 30 additions and 1 deletions

View File

@ -62,9 +62,14 @@ __FBSDID("$FreeBSD$");
#define CM_PER_LCDC_CLKCTRL (CM_PER + 0x018)
#define CM_PER_USB0_CLKCTRL (CM_PER + 0x01C)
#define CM_PER_TPTC0_CLKCTRL (CM_PER + 0x024)
#define CM_PER_UART5_CLKCTRL (CM_PER + 0x038)
#define CM_PER_MMC0_CLKCTRL (CM_PER + 0x03C)
#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x044)
#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x048)
#define CM_PER_UART1_CLKCTRL (CM_PER + 0x06C)
#define CM_PER_UART2_CLKCTRL (CM_PER + 0x070)
#define CM_PER_UART3_CLKCTRL (CM_PER + 0x074)
#define CM_PER_UART4_CLKCTRL (CM_PER + 0x078)
#define CM_PER_TIMER7_CLKCTRL (CM_PER + 0x07C)
#define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x080)
#define CM_PER_TIMER3_CLKCTRL (CM_PER + 0x084)
@ -146,6 +151,9 @@ static int am335x_clk_musb0_activate(struct ti_clock_dev *clkdev);
static int am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev);
static int am335x_clk_pruss_activate(struct ti_clock_dev *clkdev);
#define AM335X_NOOP_CLOCK_DEV(i) \
{ .id = (i) }
#define AM335X_GENERIC_CLOCK_DEV(i) \
{ .id = (i), \
.clk_activate = am335x_clk_generic_activate, \
@ -217,6 +225,14 @@ struct ti_clock_dev ti_clk_devmap[] = {
.clk_get_source_freq = am335x_clk_get_arm_disp_freq,
},
/* UART. Uart0 clock cannot be controlled. */
AM335X_NOOP_CLOCK_DEV(UART0_CLK),
AM335X_GENERIC_CLOCK_DEV(UART1_CLK),
AM335X_GENERIC_CLOCK_DEV(UART2_CLK),
AM335X_GENERIC_CLOCK_DEV(UART3_CLK),
AM335X_GENERIC_CLOCK_DEV(UART4_CLK),
AM335X_GENERIC_CLOCK_DEV(UART5_CLK),
/* DMTimer */
AM335X_GENERIC_CLOCK_DEV(DMTIMER2_CLK),
AM335X_GENERIC_CLOCK_DEV(DMTIMER3_CLK),
@ -286,6 +302,14 @@ struct am335x_clk_details {
static struct am335x_clk_details g_am335x_clk_details[] = {
/* UART. UART0 clock not controllable. */
_CLK_DETAIL(UART0_CLK, 0, 0),
_CLK_DETAIL(UART1_CLK, CM_PER_UART1_CLKCTRL, 0),
_CLK_DETAIL(UART2_CLK, CM_PER_UART2_CLKCTRL, 0),
_CLK_DETAIL(UART3_CLK, CM_PER_UART3_CLKCTRL, 0),
_CLK_DETAIL(UART4_CLK, CM_PER_UART4_CLKCTRL, 0),
_CLK_DETAIL(UART5_CLK, CM_PER_UART5_CLKCTRL, 0),
/* DMTimer modules */
_CLK_DETAIL(DMTIMER2_CLK, CM_PER_TIMER2_CLKCTRL, CLKSEL_TIMER2_CLK),
_CLK_DETAIL(DMTIMER3_CLK, CM_PER_TIMER3_CLKCTRL, CLKSEL_TIMER3_CLK),

View File

@ -81,10 +81,15 @@ typedef enum {
USBP2_HSIC_CLK,
/* UART modules */
UART1_CLK = 400,
UART0_CLK = 400,
UART1_CLK,
UART2_CLK,
UART3_CLK,
UART4_CLK,
UART5_CLK,
UART6_CLK,
UART7_CLK,
UART8_CLK,
/* General purpose timer modules */
GPTIMER1_CLK = 500,