From 7e6abd8eb5abd6eed5d9c485f162aadee832c004 Mon Sep 17 00:00:00 2001 From: jmallett Date: Mon, 19 Apr 2010 06:01:58 +0000 Subject: [PATCH] o) Fix XKPHYS physical address extraction. Also define cache coherency attributes for XKPHYS. o) Make coprocessor 0 accessor function macros for register+selector registers take the full name so that e.g. (as done in this commit), prid selector 1 can be written through mips_wr_ebase() rather than mips_wr_prid1(). o) Allow for sign extension of 32-bit segment addresses. o) Remove an unused MIPS-I register number. --- sys/mips/cavium/octeon_machdep.c | 10 -------- sys/mips/cavium/octeon_mp.c | 2 +- sys/mips/include/cpufunc.h | 32 ++++++++++++------------- sys/mips/include/cpuregs.h | 40 ++++++++++++++++++++------------ sys/mips/mips/genassym.c | 6 +++++ 5 files changed, 48 insertions(+), 42 deletions(-) diff --git a/sys/mips/cavium/octeon_machdep.c b/sys/mips/cavium/octeon_machdep.c index c796071a3859..d5df4b426eaa 100644 --- a/sys/mips/cavium/octeon_machdep.c +++ b/sys/mips/cavium/octeon_machdep.c @@ -86,16 +86,6 @@ static void octeon_boot_params_init(register_t ptr); static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx); static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx); -static __inline void -mips_wr_ebase(u_int32_t a0) -{ - __asm __volatile("mtc0 %[a0], $15, 1 ;" - : - : [a0] "r"(a0)); - - mips_barrier(); -} - void platform_cpu_init() { diff --git a/sys/mips/cavium/octeon_mp.c b/sys/mips/cavium/octeon_mp.c index 85cdc45dadd4..8ded87ee282c 100644 --- a/sys/mips/cavium/octeon_mp.c +++ b/sys/mips/cavium/octeon_mp.c @@ -69,7 +69,7 @@ platform_init_ap(int cpuid) /* * Set the exception base. */ - mips_wr_prid1(0x80000000 | cpuid); + mips_wr_ebase(0x80000000 | cpuid); /* * Set up interrupts, clear IPIs and unmask the IPI interrupt. diff --git a/sys/mips/include/cpufunc.h b/sys/mips/include/cpufunc.h index 9c34e3152d86..6520671137a9 100644 --- a/sys/mips/include/cpufunc.h +++ b/sys/mips/include/cpufunc.h @@ -166,7 +166,7 @@ mips_wr_ ## n (uint32_t a0) \ #define MIPS_RDRW32_COP0_SEL(n,r,s) \ static __inline uint32_t \ -mips_rd_ ## n ## s(void) \ +mips_rd_ ## n(void) \ { \ int v0; \ __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ @@ -175,7 +175,7 @@ mips_rd_ ## n ## s(void) \ return (v0); \ } \ static __inline void \ -mips_wr_ ## n ## s(uint32_t a0) \ +mips_wr_ ## n(uint32_t a0) \ { \ __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ __XSTRING(COP0_SYNC)";" \ @@ -201,9 +201,9 @@ static __inline void mips_sync_icache (void) MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); -MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 1); -MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 2); -MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 3); +MIPS_RDRW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1); +MIPS_RDRW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2); +MIPS_RDRW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3); MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); @@ -219,20 +219,20 @@ MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); #endif MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); /* XXX 64-bit? */ -MIPS_RDRW32_COP0_SEL(prid, MIPS_COP_0_PRID, 1); +MIPS_RDRW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); -MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1); -MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2); -MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 3); +MIPS_RDRW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); +MIPS_RDRW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); +MIPS_RDRW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3); MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); -MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 1); -MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 2); -MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 3); +MIPS_RDRW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1); +MIPS_RDRW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2); +MIPS_RDRW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3); -MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 0); -MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 1); -MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 2); -MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 3); +MIPS_RDRW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0); +MIPS_RDRW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1); +MIPS_RDRW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2); +MIPS_RDRW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3); #undef MIPS_RDRW32_COP0 diff --git a/sys/mips/include/cpuregs.h b/sys/mips/include/cpuregs.h index 74e789c1416a..3f4ffd208ba5 100644 --- a/sys/mips/include/cpuregs.h +++ b/sys/mips/include/cpuregs.h @@ -78,21 +78,36 @@ * Caching of mapped addresses is controlled by bits in the TLB entry. */ -#define MIPS_KUSEG_START 0x0 -#define MIPS_KSEG0_START 0x80000000 -#define MIPS_KSEG0_END 0x9fffffff -#define MIPS_KSEG1_START 0xa0000000 -#define MIPS_KSEG1_END 0xbfffffff -#define MIPS_KSSEG_START 0xc0000000 -#define MIPS_KSSEG_END 0xdfffffff +#if !defined(_LOCORE) +#define MIPS_KUSEG_START 0x00000000 +#define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000) +#define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff) +#define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000) +#define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff) +#define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000) +#define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff) +#define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000) +#define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff) + #define MIPS_KSEG2_START MIPS_KSSEG_START #define MIPS_KSEG2_END MIPS_KSSEG_END -#define MIPS_KSEG3_START 0xe0000000 -#define MIPS_KSEG3_END 0xffffffff +#endif + +#define MIPS_XKPHYS_START 0x8000000000000000 +#define MIPS_XKPHYS_END 0xbfffffffffffffff + +#define MIPS_XKPHYS_CCA_UC 0x02 /* Uncached. */ +#define MIPS_XKPHYS_CCA_CNC 0x03 /* Cacheable non-coherent. */ #define MIPS_PHYS_TO_XKPHYS(cca,x) \ ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) -#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL) +#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x07ffffffffffffffULL) + +#define MIPS_XUSEG_START 0x0000000000000000 +#define MIPS_XUSEG_END 0x0000010000000000 + +#define MIPS_XKSEG_START 0xc000000000000000 +#define MIPS_XKSEG_END 0xc00000ff80000000 /* CPU dependent mtc0 hazard hook */ #ifdef TARGET_OCTEON @@ -471,7 +486,6 @@ * (3=32bit, 6=64bit, i=impl dep) * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. - * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low. * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. @@ -531,10 +545,6 @@ #define MIPS_COP_0_EXC_PC _(14) #define MIPS_COP_0_PRID _(15) - -/* MIPS-I */ -#define MIPS_COP_0_TLB_LOW _(2) - /* MIPS-III */ #define MIPS_COP_0_TLB_LO0 _(2) #define MIPS_COP_0_TLB_LO1 _(3) diff --git a/sys/mips/mips/genassym.c b/sys/mips/mips/genassym.c index b10a5e2327b2..53f962b69f31 100644 --- a/sys/mips/mips/genassym.c +++ b/sys/mips/mips/genassym.c @@ -54,6 +54,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -91,9 +92,14 @@ ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc)); ASSYM(SIGFPE, SIGFPE); ASSYM(PAGE_SHIFT, PAGE_SHIFT); ASSYM(PAGE_SIZE, PAGE_SIZE); +ASSYM(PAGE_MASK, PAGE_MASK); ASSYM(SEGSHIFT, SEGSHIFT); ASSYM(NPTEPG, NPTEPG); ASSYM(TDF_NEEDRESCHED, TDF_NEEDRESCHED); ASSYM(TDF_ASTPENDING, TDF_ASTPENDING); ASSYM(PCPU_SIZE, sizeof(struct pcpu)); ASSYM(MAXCOMLEN, MAXCOMLEN); + +ASSYM(MIPS_KSEG0_START, MIPS_KSEG0_START); +ASSYM(MIPS_KSEG1_START, MIPS_KSEG1_START); +ASSYM(MIPS_KSEG2_START, MIPS_KSEG2_START);