o Add gain-level control registers.
o Fix style. Sponsored by: Machdep, Inc.
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2012 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -47,10 +47,10 @@
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#define HDSPE_BUF_POSITION_MASK 0x000FFC0
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/* Frequency */
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#define HDSPE_FREQ_0 (1<<6)
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#define HDSPE_FREQ_1 (1<<7)
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#define HDSPE_FREQ_DOUBLE (1<<8)
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#define HDSPE_FREQ_QUAD (1<<31)
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#define HDSPE_FREQ_0 (1 << 6)
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#define HDSPE_FREQ_1 (1 << 7)
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#define HDSPE_FREQ_DOUBLE (1 << 8)
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#define HDSPE_FREQ_QUAD (1 << 31)
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#define HDSPE_FREQ_32000 HDSPE_FREQ_0
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#define HDSPE_FREQ_44100 HDSPE_FREQ_1
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@ -64,24 +64,50 @@
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#define HDSPE_SPEED_DEFAULT 48000
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/* Latency */
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#define HDSPE_LAT_0 (1<<1)
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#define HDSPE_LAT_1 (1<<2)
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#define HDSPE_LAT_2 (1<<3)
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#define HDSPE_LAT_0 (1 << 1)
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#define HDSPE_LAT_1 (1 << 2)
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#define HDSPE_LAT_2 (1 << 3)
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#define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2)
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#define HDSPE_LAT_BYTES_MAX (4096 * 4)
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#define HDSPE_LAT_BYTES_MIN (32 * 4)
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#define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK)
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/* Gain */
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#define HDSP_ADGain0 (1 << 25)
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#define HDSP_ADGain1 (1 << 26)
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#define HDSP_DAGain0 (1 << 27)
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#define HDSP_DAGain1 (1 << 28)
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#define HDSP_PhoneGain0 (1 << 29)
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#define HDSP_PhoneGain1 (1 << 30)
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#define HDSP_ADGainMask (HDSP_ADGain0 | HDSP_ADGain1)
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#define HDSP_ADGainMinus10dBV (HDSP_ADGainMask)
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#define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
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#define HDSP_ADGainLowGain 0
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#define HDSP_DAGainMask (HDSP_DAGain0 | HDSP_DAGain1)
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#define HDSP_DAGainHighGain (HDSP_DAGainMask)
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#define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
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#define HDSP_DAGainMinus10dBV 0
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#define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
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#define HDSP_PhoneGain0dB HDSP_PhoneGainMask
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#define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
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#define HDSP_PhoneGainMinus12dB 0
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#define HDSPM_statusRegister 0
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#define HDSPM_statusRegister2 192
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/* Settings */
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#define HDSPE_SETTINGS_REG 0
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#define HDSPE_CONTROL_REG 64
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#define HDSPE_STATUS_REG 0
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#define HDSPE_ENABLE (1<<0)
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#define HDSPM_CLOCK_MODE_MASTER (1<<4)
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#define HDSPE_ENABLE (1 << 0)
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#define HDSPM_CLOCK_MODE_MASTER (1 << 4)
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/* Interrupts */
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#define HDSPE_AUDIO_IRQ_PENDING (1<<0)
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#define HDSPE_AUDIO_INT_ENABLE (1<<5)
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#define HDSPE_AUDIO_IRQ_PENDING (1 << 0)
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#define HDSPE_AUDIO_INT_ENABLE (1 << 5)
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#define HDSPE_INTERRUPT_ACK 96
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/* Channels */
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