- Check the slot type capability, set SDHCI_SLOT_{EMBEDDED,NON_REMOVABLE}
for embedded slots. Fail in the sdhci(4) initialization for slot type shared, which is completely unsupported by this driver at the moment. [1] For Intel eMMC controllers, taking the embedded slot type into account obsoltes setting SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE so remove these quirk entries. - Hide the 1.8 V VDD capability when the slot is detected as non-embedded, as the SDHCI specification explicitly states that 1.8 V VDD is applicable to embedded slots only. [2] - Define some easy bits of the SDHCI specification v4.20. [3] - Don't leak bus_dma(9) resources in failure paths of sdhci_init_slot(). Obtained from: DragonFlyBSD 65704a46 [1], 7ba10b88 [2], 0df14648 [3]
This commit is contained in:
Marius Strobl
parent
7a777659ff
commit
7fcf47802a
@ -742,6 +742,7 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
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BUS_DMA_NOWAIT, &slot->dmamap);
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if (err != 0) {
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device_printf(dev, "Can't alloc DMA memory\n");
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bus_dma_tag_destroy(slot->dmatag);
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SDHCI_LOCK_DESTROY(slot);
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return (err);
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}
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@ -751,6 +752,8 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
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sdhci_getaddr, &slot->paddr, 0);
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if (err != 0 || slot->paddr == 0) {
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device_printf(dev, "Can't load DMA memory\n");
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bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
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bus_dma_tag_destroy(slot->dmatag);
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SDHCI_LOCK_DESTROY(slot);
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if (err)
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return (err);
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@ -770,6 +773,22 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
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else
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caps2 = 0;
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}
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if (slot->version >= SDHCI_SPEC_300) {
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if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE &&
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(caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) {
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device_printf(dev,
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"Driver doesn't support shared bus slots\n");
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bus_dmamap_unload(slot->dmatag, slot->dmamap);
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bus_dmamem_free(slot->dmatag, slot->dmamem,
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slot->dmamap);
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bus_dma_tag_destroy(slot->dmatag);
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SDHCI_LOCK_DESTROY(slot);
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return (ENXIO);
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} else if ((caps & SDHCI_SLOTTYPE_MASK) ==
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SDHCI_SLOTTYPE_EMBEDDED) {
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slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
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}
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}
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/* Calculate base clock frequency. */
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if (slot->version >= SDHCI_SPEC_300)
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freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
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@ -819,7 +838,8 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
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slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
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if (caps & SDHCI_CAN_VDD_300)
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slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
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if (caps & SDHCI_CAN_VDD_180)
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/* 1.8V VDD is not supposed to be used for removable cards. */
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if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED))
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slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
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if (slot->host.host_ocr == 0) {
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device_printf(dev, "Hardware doesn't report any "
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@ -966,20 +986,24 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
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if (bootverbose || sdhci_debug) {
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slot_printf(slot,
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"%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s\n",
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"%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n",
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slot->max_clk / 1000000,
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(caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
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(host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" :
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((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"),
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(caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
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(caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
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(caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
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((caps & SDHCI_CAN_VDD_180) &&
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(slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "",
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(host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "",
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(host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "",
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(host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "",
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(host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "",
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(host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "",
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(slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
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(slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO",
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(slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" :
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(slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" :
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"removable");
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if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 |
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MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE))
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slot_printf(slot, "eMMC:%s%s%s%s\n",
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@ -237,6 +237,11 @@
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#define SDHCI_HOST_CONTROL2 0x3E
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#define SDHCI_CTRL2_PRESET_VALUE 0x8000
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#define SDHCI_CTRL2_ASYNC_INTR 0x4000
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#define SDHCI_CTRL2_64BIT_ENABLE 0x2000
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#define SDHCI_CTRL2_HOST_V4_ENABLE 0x1000
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#define SDHCI_CTRL2_CMD23_ENABLE 0x0800
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#define SDHCI_CTRL2_ADMA2_LENGTH_MODE 0x0400
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#define SDHCI_CTRL2_UHS2_IFACE_ENABLE 0x0100
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#define SDHCI_CTRL2_SAMPLING_CLOCK 0x0080
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#define SDHCI_CTRL2_EXEC_TUNING 0x0040
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#define SDHCI_CTRL2_DRIVER_TYPE_MASK 0x0030
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@ -321,6 +326,8 @@
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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#define SDHCI_SPEC_400 3
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#define SDHCI_SPEC_410 4
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#define SDHCI_SPEC_420 5
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SYSCTL_DECL(_hw_sdhci);
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@ -342,6 +349,7 @@ struct sdhci_slot {
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#define SDHCI_TUNING_SUPPORTED 0x08
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#define SDHCI_TUNING_ENABLED 0x10
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#define SDHCI_SDR50_NEEDS_TUNING 0x20
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#define SDHCI_SLOT_EMBEDDED 0x40
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u_char version;
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int timeout; /* Transfer timeout */
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uint32_t max_clk; /* Max possible freq */
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@ -58,7 +58,6 @@ static const struct sdhci_acpi_device {
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u_int quirks;
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} sdhci_acpi_devices[] = {
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{ "80860F14", 1, "Intel Bay Trail/Braswell eMMC 4.5/4.5.1 Controller",
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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@ -76,7 +75,6 @@ static const struct sdhci_acpi_device {
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ "80865ACC", 0, "Intel Apollo Lake eMMC 5.0 Controller",
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SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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@ -106,7 +106,6 @@ static const struct sdhci_device {
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{ 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader",
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SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
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{ 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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@ -116,14 +115,12 @@ static const struct sdhci_device {
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 |
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller",
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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@ -139,7 +136,6 @@ static const struct sdhci_device {
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SDHCI_QUIRK_PRESET_VALUE_BROKEN },
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{ 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller",
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SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */
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SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
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SDHCI_QUIRK_INTEL_POWER_UP_RESET |
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SDHCI_QUIRK_WAIT_WHILE_BUSY |
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SDHCI_QUIRK_MMC_DDR52 |
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