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Minor clean-ups for ARM64 GICv3 and GIC drivers

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GICv3:
- move ICC_SGI1R_EL1 definitions to armreg.h and use proper system
  register's names
GIC:
- remove unused functions

Reviewed by:   andrew
Obtained from: Semihalf
Sponsored by:  Cavium
Differential Revision: https://reviews.freebsd.org/D5119
This commit is contained in:
Zbigniew Bodek 2016-02-11 11:55:37 +00:00
parent d4dae2b1fb
commit 8133eda921
4 changed files with 15 additions and 34 deletions
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23
sys/arm64/arm64/gic.c
View File

@ -303,29 +303,6 @@ gic_ipi_send(device_t dev, cpuset_t cpus, u_int ipi)
gic_d_write_4(sc, GICD_SGIR(0), val | ipi);
}
static int
arm_gic_ipi_read(device_t dev, int i)
{
if (i != -1) {
/*
* The intr code will automagically give the frame pointer
* if the interrupt argument is 0.
*/
if ((unsigned int)i > 16)
return (0);
return (i);
}
return (0x3ff);
}
static void
arm_gic_ipi_clear(device_t dev, int ipi)
{
/* no-op */
}
#endif
static device_method_t arm_gic_methods[] = {

11
sys/arm64/arm64/gic_v3.c
View File

@ -412,14 +412,15 @@ gic_v3_ipi_send(device_t dev, cpuset_t cpuset, u_int ipi)
}
}
if (tlist) {
KASSERT((tlist & ~GICI_SGI_TLIST_MASK) == 0,
KASSERT((tlist & ~ICC_SGI1R_EL1_TL_MASK) == 0,
("Target list too long for GICv3 IPI"));
/* Send SGI to CPUs in target list */
val = tlist;
val |= (uint64_t)CPU_AFF3(aff) << GICI_SGI_AFF3_SHIFT;
val |= (uint64_t)CPU_AFF2(aff) << GICI_SGI_AFF2_SHIFT;
val |= (uint64_t)CPU_AFF1(aff) << GICI_SGI_AFF1_SHIFT;
val |= (uint64_t)(ipi & GICI_SGI_IPI_MASK) << GICI_SGI_IPI_SHIFT;
val |= (uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT;
val |= (uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT;
val |= (uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT;
val |= (uint64_t)(ipi & ICC_SGI1R_EL1_SGIID_MASK) <<
ICC_SGI1R_EL1_SGIID_SHIFT;
gic_icc_write(SGI1R, val);
}
}

6
sys/arm64/arm64/gic_v3_reg.h
View File

@ -356,12 +356,6 @@
/*
* CPU interface
*/
#define GICI_SGI_TLIST_MASK (0xffffUL)
#define GICI_SGI_AFF1_SHIFT (16UL)
#define GICI_SGI_AFF2_SHIFT (32UL)
#define GICI_SGI_AFF3_SHIFT (48UL)
#define GICI_SGI_IPI_MASK (0xfUL)
#define GICI_SGI_IPI_SHIFT (24UL)
/*
* Registers list (ICC_xyz_EL1):

9
sys/arm64/include/armreg.h
View File

@ -118,6 +118,15 @@
/* ICC_PMR_EL1 */
#define ICC_PMR_EL1_PRIO_MASK (0xFFUL)
/* ICC_SGI1R_EL1 */
#define ICC_SGI1R_EL1_TL_MASK 0xffffUL
#define ICC_SGI1R_EL1_AFF1_SHIFT 16
#define ICC_SGI1R_EL1_SGIID_SHIFT 24
#define ICC_SGI1R_EL1_AFF2_SHIFT 32
#define ICC_SGI1R_EL1_AFF3_SHIFT 48
#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL
#define ICC_SGI1R_EL1_IRM (0x1UL << 40)
/* ICC_SRE_EL1 */
#define ICC_SRE_EL1_SRE (1U << 0)