From 819760b35f3196227a1d90089fb98ee115e7ed0d Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Wed, 24 Feb 2021 18:02:40 +0100 Subject: [PATCH] mvebu_gpio: fix interrupt cause register configuration According to Armada 8k documentation, the interrupt cause register (at offset 0x14) is RW0C. Update the configuration in attach and the mvebu_gpio_isrc_eoi() to follow the description. Reviewed by: mmel Obtained from: Semihalf Sponsored by: Marvell Differential Revision: https://reviews.freebsd.org/D29013 --- sys/arm/mv/mvebu_gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/arm/mv/mvebu_gpio.c b/sys/arm/mv/mvebu_gpio.c index afc3f177ade3..f0471b8d019c 100644 --- a/sys/arm/mv/mvebu_gpio.c +++ b/sys/arm/mv/mvebu_gpio.c @@ -333,7 +333,7 @@ mvebu_gpio_isrc_eoi(struct mvebu_gpio_softc *sc, { if (!mgi->is_level) - intr_modify(sc, GPIO_INT_CAUSE, mgi, 1, 1); + intr_modify(sc, GPIO_INT_CAUSE, mgi, 0, 1); } static int @@ -778,7 +778,7 @@ mvebu_gpio_attach(device_t dev) /* Init HW */ gpio_write(sc, GPIO_INT_MASK, pin, 0); gpio_write(sc, GPIO_INT_LEVEL_MASK, pin, 0); - gpio_write(sc, GPIO_INT_CAUSE, pin, 1); + gpio_write(sc, GPIO_INT_CAUSE, pin, 0); gpio_write(sc, GPIO_DATA_IN_POL, pin, 1); gpio_write(sc, GPIO_BLINK_ENA, pin, 0); }