style(9)
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b5a060dd8b
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81e2a01a77
@ -1018,7 +1018,7 @@ msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN)
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error = EINVAL;
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else if (ifp->if_mtu != ifr->ifr_mtu) {
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if (ifr->ifr_mtu > ETHERMTU) {
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if (ifr->ifr_mtu > ETHERMTU) {
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if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
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error = EINVAL;
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MSK_IF_UNLOCK(sc_if);
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@ -1636,7 +1636,7 @@ msk_attach(device_t dev)
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* this workaround does not work so disable checksum offload
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* for VLAN interface.
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*/
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ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO;
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ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO;
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/*
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* Enable Rx checksum offloading for VLAN tagged frames
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* if controller support new descriptor format.
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@ -1921,7 +1921,8 @@ mskc_attach(device_t dev)
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error = ENXIO;
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goto fail;
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}
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mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO);
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mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK |
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M_ZERO);
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if (mmd == NULL) {
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device_printf(dev, "failed to allocate memory for "
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"ivars of PORT_B\n");
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@ -1930,9 +1931,9 @@ mskc_attach(device_t dev)
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}
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mmd->port = MSK_PORT_B;
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mmd->pmd = sc->msk_pmd;
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if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
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if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
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mmd->mii_flags |= MIIF_HAVEFIBER;
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if (sc->msk_pmd == 'P')
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if (sc->msk_pmd == 'P')
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mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
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device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
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}
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@ -3741,10 +3742,10 @@ msk_init_locked(struct msk_if_softc *sc_if)
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ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
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}
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/* GMAC Control reset. */
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
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/* GMAC Control reset. */
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
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if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
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sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
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@ -3854,13 +3855,13 @@ msk_init_locked(struct msk_if_softc *sc_if)
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msk_set_tx_stfwd(sc_if);
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}
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if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
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sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
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/* Disable dynamic watermark - from Linux. */
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reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
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reg &= ~0x03;
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
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}
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if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
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sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
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/* Disable dynamic watermark - from Linux. */
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reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
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reg &= ~0x03;
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CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
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}
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/*
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* Disable Force Sync bit and Alloc bit in Tx RAM interface
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