Remove code for Marvell SoCs that lack a kernel config.
It seems to be old code from the armv6 project branch that never had a kernel config. Reviewed by: mmel Sponsored by: ABT Systems Lrd Differential Revision: https://reviews.freebsd.org/D7166
This commit is contained in:
andrew
parent
8df8065e24
commit
8222ebf941
@ -76,9 +76,7 @@ MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory");
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static int win_eth_can_remap(int i);
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#ifndef SOC_MV_FREY
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static int decode_win_cpu_valid(void);
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#endif
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static int decode_win_usb_valid(void);
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static int decode_win_usb3_valid(void);
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static int decode_win_eth_valid(void);
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@ -88,9 +86,7 @@ static int decode_win_sata_valid(void);
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static int decode_win_idma_valid(void);
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static int decode_win_xor_valid(void);
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#ifndef SOC_MV_FREY
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static void decode_win_cpu_setup(void);
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#endif
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#ifdef SOC_MV_ARMADAXP
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static int decode_win_sdram_fixup(void);
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#endif
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@ -359,7 +355,7 @@ uint32_t
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soc_power_ctrl_get(uint32_t mask)
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{
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#if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) && !defined(SOC_MV_FREY)
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#if !defined(SOC_MV_ORION)
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if (mask != CPU_PM_CTRL_NONE)
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mask &= read_cpu_ctrl(CPU_PM_CTRL);
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@ -377,7 +373,7 @@ void
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soc_power_ctrl_set(uint32_t mask)
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{
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#if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS)
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#if !defined(SOC_MV_ORION)
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if (mask != CPU_PM_CTRL_NONE)
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write_cpu_ctrl(CPU_PM_CTRL, mask);
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#endif
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@ -569,7 +565,6 @@ soc_decode_win(void)
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return(err);
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#endif
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#ifndef SOC_MV_FREY
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if (!decode_win_cpu_valid() || !decode_win_usb_valid() ||
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!decode_win_eth_valid() || !decode_win_idma_valid() ||
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!decode_win_pcie_valid() || !decode_win_sata_valid() ||
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@ -577,13 +572,6 @@ soc_decode_win(void)
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return (EINVAL);
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decode_win_cpu_setup();
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#else
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if (!decode_win_usb_valid() ||
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!decode_win_eth_valid() || !decode_win_idma_valid() ||
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!decode_win_pcie_valid() || !decode_win_sata_valid() ||
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!decode_win_xor_valid() || !decode_win_usb3_valid())
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return (EINVAL);
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#endif
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if (MV_DUMP_WIN)
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soc_dump_decode_win();
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@ -598,7 +586,6 @@ soc_decode_win(void)
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/**************************************************************************
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* Decode windows registers accessors
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**************************************************************************/
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#if !defined(SOC_MV_FREY)
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WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
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@ -607,7 +594,6 @@ WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
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WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
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#endif
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WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
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WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
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@ -712,7 +698,6 @@ static inline uint32_t ddr_sz_read(int i)
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}
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#endif
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#if !defined(SOC_MV_FREY)
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/**************************************************************************
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* Decode windows helper routines
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**************************************************************************/
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@ -935,7 +920,6 @@ decode_win_cpu_setup(void)
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cpu_wins[i].size, cpu_wins[i].remap);
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}
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#endif
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#ifdef SOC_MV_ARMADAXP
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static int
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@ -1294,11 +1278,7 @@ decode_win_eth_dump(u_long base)
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win_eth_epap_read(base));
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}
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#if defined(SOC_MV_LOKIPLUS)
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#define MV_WIN_ETH_DDR_TRGT(n) 0
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#else
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#define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n)
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#endif
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static void
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decode_win_eth_setup(u_long base)
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@ -244,14 +244,9 @@ platform_late_init(void)
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/*
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* Re-initialise decode windows
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*/
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#if !defined(SOC_MV_FREY)
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if (soc_decode_win() != 0)
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printf("WARNING: could not re-initialise decode windows! "
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"Running with existing settings...\n");
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#else
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/* Disable watchdog and timers */
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write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0);
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#endif
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#if defined(SOC_MV_ARMADAXP)
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#if !defined(SMP)
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/* For SMP case it should be initialized after APs are booted */
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@ -52,18 +52,6 @@
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#define ENDPOINT_IRQ_MASK(n) 0x30
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#define ENDPOINT_IRQ_MASK_HI(n) 0x34
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#define ENDPOINT_IRQ_CAUSE_SELECT 0x38
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#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY)
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#define IRQ_CAUSE 0x0
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#define IRQ_MASK 0x4
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#define FIQ_MASK 0x8
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#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4)
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#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */
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#define IRQ_MASK_HI (-1) /* interrupt controller code */
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#define FIQ_MASK_HI (-1)
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#define ENDPOINT_IRQ_MASK_HI(n) (-1)
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#define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
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#define IRQ_CAUSE_ERROR (-1)
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#define IRQ_MASK_ERROR (-1)
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#elif defined (SOC_MV_ARMADAXP)
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#define IRQ_CAUSE 0x18
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#define IRQ_MASK 0x30
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@ -84,17 +72,7 @@
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#define IRQ_MASK_ERROR (-1) /* interrupt controller code */
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#endif
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#if defined(SOC_MV_FREY)
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#define BRIDGE_IRQ_CAUSE 0x118
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#define IRQ_TIMER0 0x00000002
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#define IRQ_TIMER1 0x00000004
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#define IRQ_TIMER_WD 0x00000008
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#define BRIDGE_IRQ_MASK 0x11c
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#define IRQ_TIMER0_MASK 0x00000002
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#define IRQ_TIMER1_MASK 0x00000004
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#define IRQ_TIMER_WD_MASK 0x00000008
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#elif defined(SOC_MV_ARMADAXP)
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#if defined(SOC_MV_ARMADAXP)
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#define BRIDGE_IRQ_CAUSE 0x68
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#define IRQ_TIMER0 0x00000001
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#define IRQ_TIMER1 0x00000002
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@ -113,17 +91,10 @@
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#define IRQ_TIMER_WD_MASK 0x00000008
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#endif
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#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY)
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#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF
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#define IRQ_TIMER0_CLR IRQ_TIMER0
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#define IRQ_TIMER1_CLR IRQ_TIMER1
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#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD
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#else
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#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF)
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#define IRQ_TIMER0_CLR (~IRQ_TIMER0)
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#define IRQ_TIMER1_CLR (~IRQ_TIMER1)
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#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD)
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#endif
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/*
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* System reset
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@ -348,22 +319,14 @@
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#define GPIO2IRQ(gpio) ((gpio) + NIRQ)
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#define IRQ2GPIO(irq) ((irq) - NIRQ)
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#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS)
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#if defined(SOC_MV_ORION)
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#define SAMPLE_AT_RESET 0x10
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#elif defined(SOC_MV_KIRKWOOD)
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#define SAMPLE_AT_RESET 0x30
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#elif defined(SOC_MV_FREY)
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#define SAMPLE_AT_RESET 0x100
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#elif defined(SOC_MV_ARMADA38X)
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#define SAMPLE_AT_RESET 0x400
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#endif
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#if defined(SOC_MV_DISCOVERY)
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#define SAMPLE_AT_RESET_LO 0x30
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#define SAMPLE_AT_RESET_HI 0x34
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#elif defined(SOC_MV_DOVE)
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#define SAMPLE_AT_RESET_LO 0x14
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#define SAMPLE_AT_RESET_HI 0x18
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#elif defined(SOC_MV_ARMADAXP)
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#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_ARMADAXP)
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#define SAMPLE_AT_RESET_LO 0x30
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#define SAMPLE_AT_RESET_HI 0x34
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#endif
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@ -377,9 +340,6 @@
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#elif defined(SOC_MV_DISCOVERY)
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#define TCLK_MASK 0x00000180
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#define TCLK_SHIFT 0x07
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#elif defined(SOC_MV_LOKIPLUS)
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#define TCLK_MASK 0x0000F000
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#define TCLK_SHIFT 0x0C
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#elif defined(SOC_MV_ARMADA38X)
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#define TCLK_MASK 0x00008000
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#define TCLK_SHIFT 15
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@ -452,15 +412,9 @@
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#define MV_DRBL_PCIE_TO_CPU 0
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#define MV_DRBL_CPU_TO_PCIE 1
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#if defined(SOC_MV_FREY)
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#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u))
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#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4)
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#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m))
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#else
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#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d))
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#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4)
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#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30)
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#endif
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/*
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* SCU
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@ -52,25 +52,16 @@
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/* SRAM */
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#define MV_CESA_SRAM_BASE 0xF1100000
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/* AXI Regs */
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#ifdef SOC_MV_DOVE
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#define MV_AXI_PHYS_BASE 0xF1800000
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#define MV_AXI_BASE MV_AXI_PHYS_BASE
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#define MV_AXI_SIZE (16 * 1024 * 1024) /* 16 MB */
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#endif
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/*
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* External devices: 0x80000000, 1 GB (VA == PA)
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* Includes Device Bus, PCI and PCIE.
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*/
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#if defined(SOC_MV_ORION)
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#define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */
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#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_FREY)
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#elif defined(SOC_MV_KIRKWOOD)
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#define MV_PCI_PORTS 1 /* 1x PCIE */
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#elif defined(SOC_MV_DISCOVERY)
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#define MV_PCI_PORTS 8 /* 8x PCIE */
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#elif defined(SOC_MV_DOVE) || defined(SOC_MV_LOKIPLUS)
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#define MV_PCI_PORTS 2 /* 2x PCIE */
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#elif defined(SOC_MV_ARMADAXP)
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#define MV_PCI_PORTS 3 /* 3x PCIE */
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#elif defined(SOC_MV_ARMADA38X)
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@ -93,11 +84,7 @@
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#define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS)
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#define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE))
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#if defined(SOC_MV_FREY)
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#define MV_PCI_VA_MEM_BASE MV_PCI_MEM_BASE
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#else
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#define MV_PCI_VA_MEM_BASE 0
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#endif
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#define MV_PCI_VA_IO_BASE 0
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/*
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@ -120,11 +107,7 @@
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* Integrated SoC peripherals addresses
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*/
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#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */
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#if defined(SOC_MV_DOVE)
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#define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100)
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#elif defined(SOC_MV_LOKIPLUS)
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#define MV_DDR_CADR_BASE (MV_BASE + 0xF1500)
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#elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
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#define MV_DDR_CADR_BASE (MV_BASE + 0x20180)
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#else
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#define MV_DDR_CADR_BASE (MV_BASE + 0x1500)
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@ -137,20 +120,16 @@
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#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
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#define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700)
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#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800)
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#elif !defined(SOC_MV_FREY)
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#else
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#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
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#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
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#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100)
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#else
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#define MV_CPU_CONTROL_BASE (MV_BASE + 0x10000)
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#endif
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#define MV_PCI_BASE (MV_BASE + 0x30000)
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#define MV_PCI_SIZE 0x2000
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#if defined(SOC_MV_FREY)
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#define MV_PCIE_BASE (MV_BASE + 0x8000)
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#elif defined(SOC_MV_ARMADA38X)
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#if defined(SOC_MV_ARMADA38X)
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#define MV_PCIE_BASE (MV_BASE + 0x80000)
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#else
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#define MV_PCIE_BASE (MV_BASE + 0x40000)
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@ -193,26 +172,12 @@
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#endif
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#define MV_WIN_CPU_ATTR_SHIFT 8
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#if defined(SOC_MV_LOKIPLUS)
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#define MV_WIN_CPU_TARGET_SHIFT 0
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#define MV_WIN_CPU_ENABLE_BIT (1 << 5)
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#else
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#define MV_WIN_CPU_TARGET_SHIFT 4
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#define MV_WIN_CPU_ENABLE_BIT 1
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#endif
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#if defined(SOC_MV_DOVE)
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#define MV_WIN_DDR_MAX 2
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#else /* SOC_MV_DOVE */
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#if defined(SOC_MV_LOKIPLUS)
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#define MV_WIN_DDR_BASE(n) (0xc * (n) + 0x4)
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#define MV_WIN_DDR_SIZE(n) (0xc * (n) + 0x0)
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#else /* SOC_MV_LOKIPLUS */
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#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0)
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#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4)
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#endif /* SOC_MV_LOKIPLUS */
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#define MV_WIN_DDR_MAX 4
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#endif /* SOC_MV_DOVE */
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/*
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* These values are valid only for peripherals decoding windows
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@ -280,7 +245,7 @@
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#define MV_XOR_CHAN_MAX 2
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#define MV_XOR_NON_REMAP 4
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#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DOVE)
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#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
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#define MV_WIN_PCIE_TARGET(n) 4
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#define MV_WIN_PCIE_MEM_ATTR(n) 0xE8
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#define MV_WIN_PCIE_IO_ATTR(n) 0xE0
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@ -296,10 +261,6 @@
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#define MV_WIN_PCIE_TARGET(n) 4
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#define MV_WIN_PCIE_MEM_ATTR(n) 0x59
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#define MV_WIN_PCIE_IO_ATTR(n) 0x51
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#elif defined(SOC_MV_LOKIPLUS)
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#define MV_WIN_PCIE_TARGET(n) (3 + (n))
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#define MV_WIN_PCIE_MEM_ATTR(n) 0x59
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#define MV_WIN_PCIE_IO_ATTR(n) 0x51
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#endif
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#define MV_WIN_PCI_TARGET 3
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@ -60,10 +60,7 @@ SOC_IMX6 opt_global.h
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SOC_MV_ARMADAXP opt_global.h
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SOC_MV_ARMADA38X opt_global.h
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SOC_MV_DISCOVERY opt_global.h
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SOC_MV_DOVE opt_global.h
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SOC_MV_FREY opt_global.h
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SOC_MV_KIRKWOOD opt_global.h
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SOC_MV_LOKIPLUS opt_global.h
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SOC_MV_ORION opt_global.h
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SOC_OMAP3 opt_global.h
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SOC_OMAP4 opt_global.h
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