Move i386's intr_machdep.c to the x86 tree and share it with amd64.
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jhb
parent
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@ -1,560 +0,0 @@
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/*-
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Machine dependent interrupt code for amd64. For amd64, we have to
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* deal with different PICs. Thus, we use the passed in vector to lookup
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* an interrupt source associated with that vector. The interrupt source
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* describes which PIC the source belongs to and includes methods to handle
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* that source.
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*/
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#include "opt_atpic.h"
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/ktr.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <sys/syslog.h>
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#include <sys/systm.h>
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#include <machine/clock.h>
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#include <machine/intr_machdep.h>
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#include <machine/smp.h>
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#ifdef DDB
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#include <ddb/ddb.h>
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#endif
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#ifndef DEV_ATPIC
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#include <machine/segments.h>
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#include <machine/frame.h>
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#include <dev/ic/i8259.h>
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#include <x86/isa/icu.h>
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#include <x86/isa/isa.h>
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#endif
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#define MAX_STRAY_LOG 5
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typedef void (*mask_fn)(void *);
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static int intrcnt_index;
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static struct intsrc *interrupt_sources[NUM_IO_INTS];
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static struct mtx intr_table_lock;
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static struct mtx intrcnt_lock;
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static STAILQ_HEAD(, pic) pics;
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#ifdef SMP
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static int assign_cpu;
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#endif
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u_long intrcnt[INTRCNT_COUNT];
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char intrnames[INTRCNT_COUNT * (MAXCOMLEN + 1)];
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size_t sintrcnt = sizeof(intrcnt);
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size_t sintrnames = sizeof(intrnames);
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static int intr_assign_cpu(void *arg, u_char cpu);
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static void intr_disable_src(void *arg);
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static void intr_init(void *__dummy);
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static int intr_pic_registered(struct pic *pic);
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static void intrcnt_setname(const char *name, int index);
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static void intrcnt_updatename(struct intsrc *is);
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static void intrcnt_register(struct intsrc *is);
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static int
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intr_pic_registered(struct pic *pic)
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{
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struct pic *p;
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STAILQ_FOREACH(p, &pics, pics) {
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if (p == pic)
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return (1);
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}
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return (0);
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}
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/*
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* Register a new interrupt controller (PIC). This is to support suspend
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* and resume where we suspend/resume controllers rather than individual
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* sources. This also allows controllers with no active sources (such as
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* 8259As in a system using the APICs) to participate in suspend and resume.
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*/
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int
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intr_register_pic(struct pic *pic)
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{
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int error;
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mtx_lock(&intr_table_lock);
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if (intr_pic_registered(pic))
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error = EBUSY;
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else {
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STAILQ_INSERT_TAIL(&pics, pic, pics);
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error = 0;
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}
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mtx_unlock(&intr_table_lock);
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return (error);
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}
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/*
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* Register a new interrupt source with the global interrupt system.
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* The global interrupts need to be disabled when this function is
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* called.
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*/
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int
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intr_register_source(struct intsrc *isrc)
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{
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int error, vector;
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KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
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vector = isrc->is_pic->pic_vector(isrc);
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if (interrupt_sources[vector] != NULL)
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return (EEXIST);
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error = intr_event_create(&isrc->is_event, isrc, 0, vector,
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intr_disable_src, (mask_fn)isrc->is_pic->pic_enable_source,
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(mask_fn)isrc->is_pic->pic_eoi_source, intr_assign_cpu, "irq%d:",
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vector);
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if (error)
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return (error);
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mtx_lock(&intr_table_lock);
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if (interrupt_sources[vector] != NULL) {
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mtx_unlock(&intr_table_lock);
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intr_event_destroy(isrc->is_event);
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return (EEXIST);
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}
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intrcnt_register(isrc);
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interrupt_sources[vector] = isrc;
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isrc->is_handlers = 0;
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mtx_unlock(&intr_table_lock);
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return (0);
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}
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struct intsrc *
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intr_lookup_source(int vector)
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{
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return (interrupt_sources[vector]);
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}
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int
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intr_add_handler(const char *name, int vector, driver_filter_t filter,
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driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
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{
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struct intsrc *isrc;
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int error;
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isrc = intr_lookup_source(vector);
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if (isrc == NULL)
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return (EINVAL);
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error = intr_event_add_handler(isrc->is_event, name, filter, handler,
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arg, intr_priority(flags), flags, cookiep);
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if (error == 0) {
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mtx_lock(&intr_table_lock);
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intrcnt_updatename(isrc);
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isrc->is_handlers++;
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if (isrc->is_handlers == 1) {
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isrc->is_pic->pic_enable_intr(isrc);
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isrc->is_pic->pic_enable_source(isrc);
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}
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mtx_unlock(&intr_table_lock);
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}
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return (error);
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}
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int
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intr_remove_handler(void *cookie)
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{
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struct intsrc *isrc;
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int error;
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isrc = intr_handler_source(cookie);
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error = intr_event_remove_handler(cookie);
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if (error == 0) {
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mtx_lock(&intr_table_lock);
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isrc->is_handlers--;
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if (isrc->is_handlers == 0) {
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isrc->is_pic->pic_disable_source(isrc, PIC_NO_EOI);
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isrc->is_pic->pic_disable_intr(isrc);
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}
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intrcnt_updatename(isrc);
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mtx_unlock(&intr_table_lock);
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}
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return (error);
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}
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int
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intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
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{
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struct intsrc *isrc;
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isrc = intr_lookup_source(vector);
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if (isrc == NULL)
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return (EINVAL);
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return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
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}
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static void
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intr_disable_src(void *arg)
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{
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struct intsrc *isrc;
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isrc = arg;
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isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
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}
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void
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intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame)
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{
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struct intr_event *ie;
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int vector;
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/*
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* We count software interrupts when we process them. The
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* code here follows previous practice, but there's an
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* argument for counting hardware interrupts when they're
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* processed too.
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*/
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(*isrc->is_count)++;
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PCPU_INC(cnt.v_intr);
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ie = isrc->is_event;
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/*
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* XXX: We assume that IRQ 0 is only used for the ISA timer
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* device (clk).
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*/
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vector = isrc->is_pic->pic_vector(isrc);
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if (vector == 0)
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clkintr_pending = 1;
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/*
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* For stray interrupts, mask and EOI the source, bump the
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* stray count, and log the condition.
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*/
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if (intr_event_handle(ie, frame) != 0) {
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isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
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(*isrc->is_straycount)++;
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if (*isrc->is_straycount < MAX_STRAY_LOG)
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log(LOG_ERR, "stray irq%d\n", vector);
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else if (*isrc->is_straycount == MAX_STRAY_LOG)
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log(LOG_CRIT,
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"too many stray irq %d's: not logging anymore\n",
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vector);
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}
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}
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void
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intr_resume(void)
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{
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struct pic *pic;
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#ifndef DEV_ATPIC
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atpic_reset();
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#endif
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mtx_lock(&intr_table_lock);
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STAILQ_FOREACH(pic, &pics, pics) {
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if (pic->pic_resume != NULL)
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pic->pic_resume(pic);
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}
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mtx_unlock(&intr_table_lock);
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}
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void
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intr_suspend(void)
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{
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struct pic *pic;
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mtx_lock(&intr_table_lock);
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STAILQ_FOREACH(pic, &pics, pics) {
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if (pic->pic_suspend != NULL)
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pic->pic_suspend(pic);
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}
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mtx_unlock(&intr_table_lock);
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}
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static int
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intr_assign_cpu(void *arg, u_char cpu)
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{
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#ifdef SMP
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struct intsrc *isrc;
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int error;
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/*
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* Don't do anything during early boot. We will pick up the
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* assignment once the APs are started.
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*/
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if (assign_cpu && cpu != NOCPU) {
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isrc = arg;
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mtx_lock(&intr_table_lock);
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error = isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[cpu]);
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mtx_unlock(&intr_table_lock);
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} else
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error = 0;
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return (error);
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#else
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return (EOPNOTSUPP);
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#endif
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}
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static void
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intrcnt_setname(const char *name, int index)
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{
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snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
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MAXCOMLEN, name);
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}
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static void
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intrcnt_updatename(struct intsrc *is)
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{
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intrcnt_setname(is->is_event->ie_fullname, is->is_index);
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}
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static void
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intrcnt_register(struct intsrc *is)
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{
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char straystr[MAXCOMLEN + 1];
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KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
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mtx_lock_spin(&intrcnt_lock);
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is->is_index = intrcnt_index;
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intrcnt_index += 2;
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snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
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is->is_pic->pic_vector(is));
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intrcnt_updatename(is);
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is->is_count = &intrcnt[is->is_index];
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intrcnt_setname(straystr, is->is_index + 1);
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is->is_straycount = &intrcnt[is->is_index + 1];
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mtx_unlock_spin(&intrcnt_lock);
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}
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void
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intrcnt_add(const char *name, u_long **countp)
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{
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mtx_lock_spin(&intrcnt_lock);
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*countp = &intrcnt[intrcnt_index];
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intrcnt_setname(name, intrcnt_index);
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intrcnt_index++;
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mtx_unlock_spin(&intrcnt_lock);
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}
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static void
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intr_init(void *dummy __unused)
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{
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intrcnt_setname("???", 0);
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intrcnt_index = 1;
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STAILQ_INIT(&pics);
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mtx_init(&intr_table_lock, "intr sources", NULL, MTX_DEF);
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mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
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}
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SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
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#ifndef DEV_ATPIC
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/* Initialize the two 8259A's to a known-good shutdown state. */
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void
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atpic_reset(void)
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{
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outb(IO_ICU1, ICW1_RESET | ICW1_IC4);
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outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS);
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outb(IO_ICU1 + ICU_IMR_OFFSET, 1 << 2);
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outb(IO_ICU1 + ICU_IMR_OFFSET, ICW4_8086);
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outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
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outb(IO_ICU1, OCW3_SEL | OCW3_RR);
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outb(IO_ICU2, ICW1_RESET | ICW1_IC4);
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outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_IO_INTS + 8);
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outb(IO_ICU2 + ICU_IMR_OFFSET, 2);
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outb(IO_ICU2 + ICU_IMR_OFFSET, ICW4_8086);
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outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
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outb(IO_ICU2, OCW3_SEL | OCW3_RR);
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}
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#endif
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/* Add a description to an active interrupt handler. */
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int
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intr_describe(u_int vector, void *ih, const char *descr)
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{
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struct intsrc *isrc;
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int error;
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isrc = intr_lookup_source(vector);
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if (isrc == NULL)
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return (EINVAL);
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error = intr_event_describe_handler(isrc->is_event, ih, descr);
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if (error)
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return (error);
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intrcnt_updatename(isrc);
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return (0);
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}
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#ifdef DDB
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/*
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* Dump data about interrupt handlers
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*/
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DB_SHOW_COMMAND(irqs, db_show_irqs)
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{
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struct intsrc **isrc;
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int i, verbose;
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if (strcmp(modif, "v") == 0)
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verbose = 1;
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else
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verbose = 0;
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isrc = interrupt_sources;
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for (i = 0; i < NUM_IO_INTS && !db_pager_quit; i++, isrc++)
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if (*isrc != NULL)
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db_dump_intr_event((*isrc)->is_event, verbose);
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}
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#endif
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#ifdef SMP
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/*
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* Support for balancing interrupt sources across CPUs. For now we just
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* allocate CPUs round-robin.
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*/
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static cpuset_t intr_cpus;
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static int current_cpu;
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/*
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* Return the CPU that the next interrupt source should use. For now
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* this just returns the next local APIC according to round-robin.
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*/
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u_int
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intr_next_cpu(void)
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{
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u_int apic_id;
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/* Leave all interrupts on the BSP during boot. */
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if (!assign_cpu)
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return (PCPU_GET(apic_id));
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mtx_lock_spin(&icu_lock);
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apic_id = cpu_apic_ids[current_cpu];
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do {
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current_cpu++;
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if (current_cpu > mp_maxid)
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current_cpu = 0;
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} while (!CPU_ISSET(current_cpu, &intr_cpus));
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mtx_unlock_spin(&icu_lock);
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return (apic_id);
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}
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/* Attempt to bind the specified IRQ to the specified CPU. */
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int
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intr_bind(u_int vector, u_char cpu)
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{
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struct intsrc *isrc;
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isrc = intr_lookup_source(vector);
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if (isrc == NULL)
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return (EINVAL);
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return (intr_event_bind(isrc->is_event, cpu));
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}
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/*
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* Add a CPU to our mask of valid CPUs that can be destinations of
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||||
* interrupts.
|
||||
*/
|
||||
void
|
||||
intr_add_cpu(u_int cpu)
|
||||
{
|
||||
|
||||
if (cpu >= MAXCPU)
|
||||
panic("%s: Invalid CPU ID", __func__);
|
||||
if (bootverbose)
|
||||
printf("INTR: Adding local APIC %d as a target\n",
|
||||
cpu_apic_ids[cpu]);
|
||||
|
||||
CPU_SET(cpu, &intr_cpus);
|
||||
}
|
||||
|
||||
/*
|
||||
* Distribute all the interrupt sources among the available CPUs once the
|
||||
* AP's have been launched.
|
||||
*/
|
||||
static void
|
||||
intr_shuffle_irqs(void *arg __unused)
|
||||
{
|
||||
struct intsrc *isrc;
|
||||
int i;
|
||||
|
||||
/* The BSP is always a valid target. */
|
||||
CPU_SETOF(0, &intr_cpus);
|
||||
|
||||
/* Don't bother on UP. */
|
||||
if (mp_ncpus == 1)
|
||||
return;
|
||||
|
||||
/* Round-robin assign a CPU to each enabled source. */
|
||||
mtx_lock(&intr_table_lock);
|
||||
assign_cpu = 1;
|
||||
for (i = 0; i < NUM_IO_INTS; i++) {
|
||||
isrc = interrupt_sources[i];
|
||||
if (isrc != NULL && isrc->is_handlers > 0) {
|
||||
/*
|
||||
* If this event is already bound to a CPU,
|
||||
* then assign the source to that CPU instead
|
||||
* of picking one via round-robin. Note that
|
||||
* this is careful to only advance the
|
||||
* round-robin if the CPU assignment succeeds.
|
||||
*/
|
||||
if (isrc->is_event->ie_cpu != NOCPU)
|
||||
(void)isrc->is_pic->pic_assign_cpu(isrc,
|
||||
cpu_apic_ids[isrc->is_event->ie_cpu]);
|
||||
else if (isrc->is_pic->pic_assign_cpu(isrc,
|
||||
cpu_apic_ids[current_cpu]) == 0)
|
||||
(void)intr_next_cpu();
|
||||
|
||||
}
|
||||
}
|
||||
mtx_unlock(&intr_table_lock);
|
||||
}
|
||||
SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,
|
||||
NULL);
|
||||
#else
|
||||
/*
|
||||
* Always route interrupts to the current processor in the UP case.
|
||||
*/
|
||||
u_int
|
||||
intr_next_cpu(void)
|
||||
{
|
||||
|
||||
return (PCPU_GET(apic_id));
|
||||
}
|
||||
#endif
|
||||
@ -112,7 +112,6 @@ amd64/amd64/gdb_machdep.c optional gdb
|
||||
amd64/amd64/identcpu.c standard
|
||||
amd64/amd64/in_cksum.c optional inet | inet6
|
||||
amd64/amd64/initcpu.c standard
|
||||
amd64/amd64/intr_machdep.c standard
|
||||
amd64/amd64/io.c optional io
|
||||
amd64/amd64/legacy.c standard
|
||||
amd64/amd64/locore.S standard no-obj
|
||||
@ -475,6 +474,7 @@ x86/pci/pci_bus.c optional pci
|
||||
x86/pci/qpi.c optional pci
|
||||
x86/x86/busdma_machdep.c standard
|
||||
x86/x86/dump_machdep.c standard
|
||||
x86/x86/intr_machdep.c standard
|
||||
x86/x86/io_apic.c standard
|
||||
x86/x86/local_apic.c standard
|
||||
x86/x86/mca.c standard
|
||||
|
||||
@ -405,7 +405,6 @@ i386/i386/i686_mem.c optional mem
|
||||
i386/i386/identcpu.c standard
|
||||
i386/i386/in_cksum.c optional inet | inet6
|
||||
i386/i386/initcpu.c standard
|
||||
i386/i386/intr_machdep.c standard
|
||||
i386/i386/io.c optional io
|
||||
i386/i386/k6_mem.c optional mem
|
||||
i386/i386/legacy.c optional native
|
||||
@ -527,6 +526,7 @@ x86/pci/pci_bus.c optional pci
|
||||
x86/pci/qpi.c optional pci
|
||||
x86/x86/busdma_machdep.c standard
|
||||
x86/x86/dump_machdep.c standard
|
||||
x86/x86/intr_machdep.c standard
|
||||
x86/x86/io_apic.c optional apic
|
||||
x86/x86/local_apic.c optional apic
|
||||
x86/x86/mca.c standard
|
||||
|
||||
@ -144,7 +144,6 @@ i386/i386/i686_mem.c optional mem
|
||||
i386/i386/identcpu.c standard
|
||||
i386/i386/in_cksum.c optional inet | inet6
|
||||
i386/i386/initcpu.c standard
|
||||
i386/i386/intr_machdep.c standard
|
||||
i386/i386/io.c optional io
|
||||
i386/i386/k6_mem.c optional mem
|
||||
i386/i386/legacy.c standard
|
||||
@ -251,6 +250,7 @@ x86/isa/isa.c optional isa
|
||||
x86/pci/pci_bus.c optional pci
|
||||
x86/x86/busdma_machdep.c standard
|
||||
x86/x86/dump_machdep.c standard
|
||||
x86/x86/intr_machdep.c standard
|
||||
x86/x86/io_apic.c optional apic
|
||||
x86/x86/local_apic.c optional apic
|
||||
x86/x86/mca.c standard
|
||||
|
||||
@ -30,7 +30,7 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* Machine dependent interrupt code for i386. For the i386, we have to
|
||||
* Machine dependent interrupt code for x86. For x86, we have to
|
||||
* deal with different PICs. Thus, we use the passed in vector to lookup
|
||||
* an interrupt source associated with that vector. The interrupt source
|
||||
* describes which PIC the source belongs to and includes methods to handle
|
||||
Loading…
Reference in New Issue
Block a user