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sfxge(4): fix Medford timer quantum calculation in common code

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The event/timer block used sysclk in Huntington, but has been
moved to the dpcpu clock domain for Medford. Fix the computed
timer quantum to use the right clock.

Submitted by:   Andy Moreton <amoreton at solarflare.com>
Sponsored by:   Solarflare Communications, Inc.
MFC after:      1 week
Differential Revision:  https://reviews.freebsd.org/D6389
This commit is contained in:
arybchik 2016-05-17 06:26:02 +00:00
parent 1718ddb85c
commit 827fd63ffa
4 changed files with 23 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sys/dev/sfxge/common/ef10_impl.h
View File

@ -1061,7 +1061,9 @@ efx_mcdi_get_mac_address_vf(
extern __checkReturn efx_rc_t
efx_mcdi_get_clock(
__in efx_nic_t *enp,
__out uint32_t *sys_freqp);
__out uint32_t *sys_freqp,
__out uint32_t *dpcpu_freqp);
extern __checkReturn efx_rc_t
efx_mcdi_get_vector_cfg(

10
sys/dev/sfxge/common/ef10_nic.c
View File

@ -389,7 +389,8 @@ efx_mcdi_get_mac_address_vf(
__checkReturn efx_rc_t
efx_mcdi_get_clock(
__in efx_nic_t *enp,
__out uint32_t *sys_freqp)
__out uint32_t *sys_freqp,
__out uint32_t *dpcpu_freqp)
{
efx_mcdi_req_t req;
uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
@ -423,9 +424,16 @@ efx_mcdi_get_clock(
rc = EINVAL;
goto fail3;
}
*dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
if (*dpcpu_freqp == 0) {
rc = EINVAL;
goto fail4;
}
return (0);
fail4:
EFSYS_PROBE(fail4);
fail3:
EFSYS_PROBE(fail3);
fail2:

10
sys/dev/sfxge/common/hunt_nic.c
View File

@ -114,7 +114,7 @@ hunt_board_cfg(
uint32_t vf;
uint32_t mask;
uint32_t flags;
uint32_t sysclk;
uint32_t sysclk, dpcpu_clk;
uint32_t base, nvec;
uint32_t bandwidth;
efx_rc_t rc;
@ -274,13 +274,13 @@ hunt_board_cfg(
goto fail10;
}
/* Get sysclk frequency (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
goto fail11;
/*
* The timer quantum is 1536 sysclk cycles, documented for the
* EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
* The Huntington timer quantum is 1536 sysclk cycles, documented for
* the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
*/
encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
if (encp->enc_bug35388_workaround) {

12
sys/dev/sfxge/common/medford_nic.c
View File

@ -141,7 +141,7 @@ medford_board_cfg(
uint32_t pf;
uint32_t vf;
uint32_t mask;
uint32_t sysclk;
uint32_t sysclk, dpcpu_clk;
uint32_t base, nvec;
uint32_t end_padding;
uint32_t bandwidth;
@ -231,15 +231,15 @@ medford_board_cfg(
/* Chained multicast is always enabled on Medford */
encp->enc_bug26807_workaround = B_TRUE;
/* Get sysclk frequency (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
goto fail8;
/*
* The timer quantum is 1536 sysclk cycles, documented for the
* EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
* The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
* the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
*/
encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;