From 8328f0397d6da836ea8856bdbf9afabbe607292d Mon Sep 17 00:00:00 2001 From: zbb Date: Wed, 20 Jan 2016 14:14:30 +0000 Subject: [PATCH] Change DTS entry of PCIe controller for Armada38x Invalid (in FreeBSD) definition of PCI controller was replaced with another one, working in FreeBSD environment. PCI controller's entry had to move from its parent node so as to be recognized properly by FBSD. PCI was enabled in kernel configuration file. Obtained from: Semihalf Sponsored by: Stormshield Submitted by: Bartosz Szczepanek Differential revision: https://reviews.freebsd.org/D4379 --- sys/arm/conf/ARMADA38X | 6 ++ sys/boot/fdt/dts/arm/armada-385.dtsi | 105 ------------------------- sys/boot/fdt/dts/arm/armada-388-gp.dts | 29 +------ sys/boot/fdt/dts/arm/armada-38x.dtsi | 19 +++++ 4 files changed, 29 insertions(+), 130 deletions(-) diff --git a/sys/arm/conf/ARMADA38X b/sys/arm/conf/ARMADA38X index 0378d5da937a..7cd70da3d214 100644 --- a/sys/arm/conf/ARMADA38X +++ b/sys/arm/conf/ARMADA38X @@ -51,6 +51,12 @@ device uart_ns8250 # Network device ether device vlan +device mii +device bpf +device re + +# PCI +device pci # Interrupt controllers device gic diff --git a/sys/boot/fdt/dts/arm/armada-385.dtsi b/sys/boot/fdt/dts/arm/armada-385.dtsi index c82d67911249..8dc620228033 100644 --- a/sys/boot/fdt/dts/arm/armada-385.dtsi +++ b/sys/boot/fdt/dts/arm/armada-385.dtsi @@ -77,110 +77,5 @@ compatible = "marvell,mv88f6820-pinctrl"; }; }; - - pcie-controller { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ - 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ - 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; - - /* - * This port can be either x4 or x1. When - * configured in x4 by the bootloader, then - * pcie@4,0 is not available. - */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - }; - - /* - * x1 port only available when pcie@1,0 is - * configured as a x1 port - */ - pcie@4,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; - reg = <0x2000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 - 0x81000000 0 0 0x81000000 0x4 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <3>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 7>; - status = "disabled"; - }; - }; }; }; diff --git a/sys/boot/fdt/dts/arm/armada-388-gp.dts b/sys/boot/fdt/dts/arm/armada-388-gp.dts index 06999a006765..8a211f644d43 100644 --- a/sys/boot/fdt/dts/arm/armada-388-gp.dts +++ b/sys/boot/fdt/dts/arm/armada-388-gp.dts @@ -226,31 +226,6 @@ }; }; - pcie-controller { - status = "okay"; - /* - * One PCIe units is accessible through - * standard PCIe slot on the board. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * The two other PCIe units are accessible - * through mini PCIe slot on the board. - */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - pcie@3,0 { - /* Port 2, Lane 0 */ - status = "okay"; - }; - }; - gpio-fan { compatible = "gpio-fan"; gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; @@ -259,6 +234,10 @@ }; }; + pci0: pcie@f1080000 { + status = "okay"; + }; + reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; regulator-name = "usb3-vbus"; diff --git a/sys/boot/fdt/dts/arm/armada-38x.dtsi b/sys/boot/fdt/dts/arm/armada-38x.dtsi index a5d1ff14d446..d93dab28c444 100644 --- a/sys/boot/fdt/dts/arm/armada-38x.dtsi +++ b/sys/boot/fdt/dts/arm/armada-38x.dtsi @@ -593,6 +593,25 @@ }; }; + pci0: pcie@f1080000 { + compatible = "mrvl,pcie"; + status = "disabled"; + device_type = "pci"; + #interrupt-cells = <3>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xf1080000 0x2000>; + bus-range = <0 255>; + ranges = <0x42000000 0x0 0xf1200000 0xf1200000 0x0 0x00100000 + 0x41000000 0x0 0x00000000 0xf1300000 0x0 0x00100000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x0000 0x0 0x0 0x1 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH + >; + }; + clocks { /* 2 GHz fixed main PLL */ mainpll: mainpll {