This commit is contained in:
attilio 2011-11-01 04:01:39 +00:00
parent f8c5162413
commit 834a32dc4f
32 changed files with 427 additions and 291 deletions

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@ -64,9 +64,9 @@ __FBSDID("$FreeBSD$");
#include <unistd.h> #include <unistd.h>
#include <stddef.h> #include <stddef.h>
int bflag, eflag, nflag, sflag, tflag, vflag; static int bflag, eflag, nflag, sflag, tflag, vflag;
int rval; static int rval;
const char *filename; static const char *filename;
static void usage(void); static void usage(void);
static void scanfiles(char *argv[], int cooked); static void scanfiles(char *argv[], int cooked);

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@ -54,16 +54,16 @@ __FBSDID("$FreeBSD$");
#include <string.h> #include <string.h>
#include <unistd.h> #include <unistd.h>
int fflag; /* Unlink existing files. */ static int fflag; /* Unlink existing files. */
int Fflag; /* Remove empty directories also. */ static int Fflag; /* Remove empty directories also. */
int hflag; /* Check new name for symlink first. */ static int hflag; /* Check new name for symlink first. */
int iflag; /* Interactive mode. */ static int iflag; /* Interactive mode. */
int Pflag; /* Create hard links to symlinks. */ static int Pflag; /* Create hard links to symlinks. */
int sflag; /* Symbolic, not hard, link. */ static int sflag; /* Symbolic, not hard, link. */
int vflag; /* Verbose output. */ static int vflag; /* Verbose output. */
int wflag; /* Warn if symlink target does not static int wflag; /* Warn if symlink target does not
* exist, and -f is not enabled. */ * exist, and -f is not enabled. */
char linkch; static char linkch;
int linkit(const char *, const char *, int); int linkit(const char *, const char *, int);
void usage(void); void usage(void);

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@ -56,7 +56,7 @@ __FBSDID("$FreeBSD$");
static int build(char *, mode_t); static int build(char *, mode_t);
static void usage(void); static void usage(void);
int vflag; static int vflag;
int int
main(int argc, char *argv[]) main(int argc, char *argv[])

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@ -68,7 +68,7 @@ __FBSDID("$FreeBSD$");
/* Exit code for a failed exec. */ /* Exit code for a failed exec. */
#define EXEC_FAILED 127 #define EXEC_FAILED 127
int fflg, iflg, nflg, vflg; static int fflg, iflg, nflg, vflg;
static int copy(const char *, const char *); static int copy(const char *, const char *);
static int do_move(const char *, const char *); static int do_move(const char *, const char *);

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@ -362,7 +362,7 @@ tdev(KINFO *k, VARENT *ve)
v = ve->var; v = ve->var;
dev = k->ki_p->ki_tdev; dev = k->ki_p->ki_tdev;
if (dev == NODEV) if (dev == NODEV)
str = strdup("??"); str = strdup("-");
else else
asprintf(&str, "%#jx", (uintmax_t)dev); asprintf(&str, "%#jx", (uintmax_t)dev);
@ -379,7 +379,7 @@ tname(KINFO *k, VARENT *ve)
v = ve->var; v = ve->var;
dev = k->ki_p->ki_tdev; dev = k->ki_p->ki_tdev;
if (dev == NODEV || (ttname = devname(dev, S_IFCHR)) == NULL) if (dev == NODEV || (ttname = devname(dev, S_IFCHR)) == NULL)
str = strdup("?? "); str = strdup("- ");
else { else {
if (strncmp(ttname, "tty", 3) == 0 || if (strncmp(ttname, "tty", 3) == 0 ||
strncmp(ttname, "cua", 3) == 0) strncmp(ttname, "cua", 3) == 0)
@ -403,7 +403,7 @@ longtname(KINFO *k, VARENT *ve)
v = ve->var; v = ve->var;
dev = k->ki_p->ki_tdev; dev = k->ki_p->ki_tdev;
if (dev == NODEV || (ttname = devname(dev, S_IFCHR)) == NULL) if (dev == NODEV || (ttname = devname(dev, S_IFCHR)) == NULL)
ttname = "??"; ttname = "-";
return (strdup(ttname)); return (strdup(ttname));
} }

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@ -29,7 +29,7 @@
.\" @(#)ps.1 8.3 (Berkeley) 4/18/94 .\" @(#)ps.1 8.3 (Berkeley) 4/18/94
.\" $FreeBSD$ .\" $FreeBSD$
.\" .\"
.Dd October 1, 2011 .Dd October 30, 2011
.Dt PS 1 .Dt PS 1
.Os .Os
.Sh NAME .Sh NAME
@ -437,6 +437,10 @@ This is followed by a
.Ql - .Ql -
if the process can no longer reach that if the process can no longer reach that
controlling terminal (i.e., it has been revoked). controlling terminal (i.e., it has been revoked).
A
.Ql -
without a preceding two letter abbreviation or pseudo-terminal device number
indicates a process which never had a controlling terminal.
The full pathname of the controlling terminal is available via the The full pathname of the controlling terminal is available via the
.Cm tty .Cm tty
keyword. keyword.

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@ -57,10 +57,10 @@ __FBSDID("$FreeBSD$");
#include <sysexits.h> #include <sysexits.h>
#include <unistd.h> #include <unistd.h>
int dflag, eval, fflag, iflag, Pflag, vflag, Wflag, stdin_ok; static int dflag, eval, fflag, iflag, Pflag, vflag, Wflag, stdin_ok;
int rflag, Iflag; static int rflag, Iflag;
uid_t uid; static uid_t uid;
volatile sig_atomic_t info; static volatile sig_atomic_t info;
int check(char *, char *, struct stat *); int check(char *, char *, struct stat *);
int check2(char **); int check2(char **);

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@ -118,7 +118,7 @@ enum token_types {
PAREN PAREN
}; };
struct t_op { static struct t_op {
const char *op_text; const char *op_text;
short op_num, op_type; short op_num, op_type;
} const ops [] = { } const ops [] = {
@ -165,10 +165,10 @@ struct t_op {
{0, 0, 0} {0, 0, 0}
}; };
struct t_op const *t_wp_op; static struct t_op const *t_wp_op;
int nargc; static int nargc;
char **t_wp; static char **t_wp;
int parenlevel; static int parenlevel;
static int aexpr(enum token); static int aexpr(enum token);
static int binop(void); static int binop(void);

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@ -6,8 +6,8 @@
.PATH: ${.CURDIR}/../../../cddl/contrib/opensolaris/lib/libzfs/common .PATH: ${.CURDIR}/../../../cddl/contrib/opensolaris/lib/libzfs/common
LIB= zfs LIB= zfs
DPADD= ${LIBMD} ${LIBPTHREAD} ${LIBUMEM} ${LIBUTIL} DPADD= ${LIBMD} ${LIBPTHREAD} ${LIBUMEM} ${LIBUTIL} ${LIBM}
LDADD= -lmd -lpthread -lumem -lutil LDADD= -lmd -lpthread -lumem -lutil -lm
SRCS= deviceid.c \ SRCS= deviceid.c \
fsshare.c \ fsshare.c \

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@ -21,8 +21,8 @@ CFLAGS+= -I${.CURDIR}/../../../sys/cddl/contrib/opensolaris/uts/common/fs/zfs
CFLAGS+= -I${.CURDIR}/../../../sys/cddl/contrib/opensolaris/uts/common/sys CFLAGS+= -I${.CURDIR}/../../../sys/cddl/contrib/opensolaris/uts/common/sys
CFLAGS+= -I${.CURDIR}/../../../sys/cddl/contrib/opensolaris/common/zfs CFLAGS+= -I${.CURDIR}/../../../sys/cddl/contrib/opensolaris/common/zfs
DPADD= ${LIBBSDXML} ${LIBGEOM} ${LIBM} ${LIBNVPAIR} ${LIBSBUF} ${LIBUMEM} \ DPADD= ${LIBGEOM} ${LIBNVPAIR} ${LIBUMEM} \
${LIBUTIL} ${LIBUUTIL} ${LIBZFS} ${LIBUTIL} ${LIBUUTIL} ${LIBZFS}
LDADD= -lbsdxml -lgeom -lm -lnvpair -lsbuf -lumem -lutil -luutil -lzfs LDADD= -lgeom -lnvpair -lumem -lutil -luutil -lzfs
.include <bsd.prog.mk> .include <bsd.prog.mk>

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@ -26,8 +26,8 @@ CFLAGS+= -I${.CURDIR}/../../../sys/cddl/contrib/opensolaris/uts/common/sys
CFLAGS+= -I${.CURDIR}/../../../cddl/contrib/opensolaris/lib/libzpool/common CFLAGS+= -I${.CURDIR}/../../../cddl/contrib/opensolaris/lib/libzpool/common
CFLAGS+= -I${.CURDIR}/../../../cddl/contrib/opensolaris/cmd/stat/common CFLAGS+= -I${.CURDIR}/../../../cddl/contrib/opensolaris/cmd/stat/common
DPADD= ${LIBAVL} ${LIBBSDXML} ${LIBGEOM} ${LIBM} ${LIBNVPAIR} ${LIBSBUF} \ DPADD= ${LIBAVL} ${LIBGEOM} ${LIBNVPAIR} \
${LIBUMEM} ${LIBUTIL} ${LIBUUTIL} ${LIBZFS} ${LIBUMEM} ${LIBUTIL} ${LIBUUTIL} ${LIBZFS}
LDADD= -lavl -lbsdxml -lgeom -lm -lnvpair -lsbuf -lumem -lutil -luutil -lzfs LDADD= -lavl -lgeom -lnvpair -lumem -lutil -luutil -lzfs
.include <bsd.prog.mk> .include <bsd.prog.mk>

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@ -19,8 +19,8 @@ CFLAGS+= -I${.CURDIR}/../../../sys/cddl/contrib/opensolaris/uts/common
CFLAGS+= -I${.CURDIR}/../../contrib/opensolaris/head CFLAGS+= -I${.CURDIR}/../../contrib/opensolaris/head
CFLAGS+= -I${.CURDIR}/../../lib/libumem CFLAGS+= -I${.CURDIR}/../../lib/libumem
DPADD= ${LIBAVL} ${LIBGEOM} ${LIBM} ${LIBNVPAIR} ${LIBUMEM} ${LIBUUTIL} \ DPADD= ${LIBGEOM} ${LIBM} ${LIBNVPAIR} ${LIBUMEM} ${LIBUUTIL} \
${LIBZFS} ${LIBZPOOL} ${LIBZFS} ${LIBZPOOL}
LDADD= -lavl -lgeom -lm -lnvpair -lumem -luutil -lzfs -lzpool LDADD= -lgeom -lm -lnvpair -lumem -luutil -lzfs -lzpool
.include <bsd.prog.mk> .include <bsd.prog.mk>

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@ -18,8 +18,8 @@ CFLAGS+= -I${.CURDIR}/../../contrib/opensolaris/head
CFLAGS+= -I${.CURDIR}/../../lib/libumem CFLAGS+= -I${.CURDIR}/../../lib/libumem
DPADD= ${LIBM} ${LIBNVPAIR} ${LIBUMEM} ${LIBZPOOL} \ DPADD= ${LIBM} ${LIBNVPAIR} ${LIBUMEM} ${LIBZPOOL} \
${LIBPTHREAD} ${LIBZ} ${LIBAVL} ${LIBPTHREAD} ${LIBAVL}
LDADD= -lm -lnvpair -lumem -lzpool -lpthread -lz -lavl LDADD= -lm -lnvpair -lumem -lzpool -lpthread -lavl
CSTD= c99 CSTD= c99

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@ -23,9 +23,9 @@ CFLAGS+= -I${.CURDIR}/../../../sys/cddl/contrib/opensolaris/common/zfs
CFLAGS+= -I${.CURDIR}/../../../cddl/contrib/opensolaris/head CFLAGS+= -I${.CURDIR}/../../../cddl/contrib/opensolaris/head
CFLAGS+= -I${.CURDIR}/../../lib/libumem CFLAGS+= -I${.CURDIR}/../../lib/libumem
DPADD= ${LIBAVL} ${LIBGEOM} ${LIBM} ${LIBNVPAIR} ${LIBPTHREAD} ${LIBUMEM} \ DPADD= ${LIBGEOM} ${LIBM} ${LIBNVPAIR} ${LIBPTHREAD} ${LIBUMEM} \
${LIBUUTIL} ${LIBZ} ${LIBZFS} ${LIBZPOOL} ${LIBUUTIL} ${LIBZFS} ${LIBZPOOL}
LDADD= -lavl -lgeom -lm -lnvpair -lpthread -lumem -luutil -lz -lzfs -lzpool LDADD= -lgeom -lm -lnvpair -lpthread -lumem -luutil -lzfs -lzpool
.include <bsd.prog.mk> .include <bsd.prog.mk>

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@ -1282,6 +1282,7 @@ class X86TargetInfo : public TargetInfo {
CK_K8SSE3, CK_K8SSE3,
CK_Opteron, CK_Opteron,
CK_OpteronSSE3, CK_OpteronSSE3,
CK_AMDFAM10,
/// This specification is deprecated and will be removed in the future. /// This specification is deprecated and will be removed in the future.
/// Users should prefer \see CK_K8. /// Users should prefer \see CK_K8.
@ -1381,6 +1382,7 @@ class X86TargetInfo : public TargetInfo {
.Case("k8-sse3", CK_K8SSE3) .Case("k8-sse3", CK_K8SSE3)
.Case("opteron", CK_Opteron) .Case("opteron", CK_Opteron)
.Case("opteron-sse3", CK_OpteronSSE3) .Case("opteron-sse3", CK_OpteronSSE3)
.Case("amdfam10", CK_AMDFAM10)
.Case("x86-64", CK_x86_64) .Case("x86-64", CK_x86_64)
.Case("geode", CK_Geode) .Case("geode", CK_Geode)
.Default(CK_Generic); .Default(CK_Generic);
@ -1441,6 +1443,7 @@ class X86TargetInfo : public TargetInfo {
case CK_K8SSE3: case CK_K8SSE3:
case CK_Opteron: case CK_Opteron:
case CK_OpteronSSE3: case CK_OpteronSSE3:
case CK_AMDFAM10:
case CK_x86_64: case CK_x86_64:
return true; return true;
} }
@ -1459,12 +1462,10 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
Features["ssse3"] = false; Features["ssse3"] = false;
Features["sse41"] = false; Features["sse41"] = false;
Features["sse42"] = false; Features["sse42"] = false;
Features["sse4a"] = false;
Features["aes"] = false; Features["aes"] = false;
Features["avx"] = false; Features["avx"] = false;
// LLVM does not currently recognize this.
// Features["sse4a"] = false;
// FIXME: This *really* should not be here. // FIXME: This *really* should not be here.
// X86_64 always has SSE2. // X86_64 always has SSE2.
@ -1561,6 +1562,11 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
setFeatureEnabled(Features, "sse3", true); setFeatureEnabled(Features, "sse3", true);
setFeatureEnabled(Features, "3dnowa", true); setFeatureEnabled(Features, "3dnowa", true);
break; break;
case CK_AMDFAM10:
setFeatureEnabled(Features, "sse3", true);
setFeatureEnabled(Features, "sse4a", true);
setFeatureEnabled(Features, "3dnowa", true);
break;
case CK_C3_2: case CK_C3_2:
setFeatureEnabled(Features, "mmx", true); setFeatureEnabled(Features, "mmx", true);
setFeatureEnabled(Features, "sse", true); setFeatureEnabled(Features, "sse", true);
@ -1604,6 +1610,8 @@ bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
else if (Name == "avx") else if (Name == "avx")
Features["avx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = Features["avx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
Features["ssse3"] = Features["sse41"] = Features["sse42"] = true; Features["ssse3"] = Features["sse41"] = Features["sse42"] = true;
else if (Name == "sse4a")
Features["sse4a"] = true;
} else { } else {
if (Name == "mmx") if (Name == "mmx")
Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false; Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
@ -1630,6 +1638,8 @@ bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
Features["aes"] = false; Features["aes"] = false;
else if (Name == "avx") else if (Name == "avx")
Features["avx"] = false; Features["avx"] = false;
else if (Name == "sse4a")
Features["sse4a"] = false;
} }
return true; return true;
@ -1826,6 +1836,11 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__k8__"); Builder.defineMacro("__k8__");
Builder.defineMacro("__tune_k8__"); Builder.defineMacro("__tune_k8__");
break; break;
case CK_AMDFAM10:
Builder.defineMacro("__amdfam10");
Builder.defineMacro("__amdfam10__");
Builder.defineMacro("__tune_amdfam10__");
break;
case CK_Geode: case CK_Geode:
Builder.defineMacro("__geode"); Builder.defineMacro("__geode");
Builder.defineMacro("__geode__"); Builder.defineMacro("__geode__");

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@ -1,5 +1,5 @@
# <pre> # <pre>
# @(#)australasia 8.28 # @(#)australasia 8.29
# This file is in the public domain, so clarified as of # This file is in the public domain, so clarified as of
# 2009-05-17 by Arthur David Olson. # 2009-05-17 by Arthur David Olson.
@ -308,6 +308,20 @@ Zone Indian/Cocos 6:27:40 - LMT 1900
# advance at 2am to 3am on October 23, 2011 and one hour back at 3am to # advance at 2am to 3am on October 23, 2011 and one hour back at 3am to
# 2am on February 26 next year. # 2am on February 26 next year.
# From Ken Rylander (2011-10-24)
# Another change to the Fiji DST end date. In the TZ database the end date for
# Fiji DST 2012, is currently Feb 26. This has been changed to Jan 22.
#
# <a href="http://www.fiji.gov.fj/index.php?option=com_content&view=article&id=5017:amendments-to-daylight-savings&catid=71:press-releases&Itemid=155">
# http://www.fiji.gov.fj/index.php?option=com_content&view=article&id=5017:amendments-to-daylight-savings&catid=71:press-releases&Itemid=155
# </a>
# states:
#
# The end of daylight saving scheduled initially for the 26th of February 2012
# has been brought forward to the 22nd of January 2012.
# The commencement of daylight saving will remain unchanged and start
# on the 23rd of October, 2011.
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S # Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S
Rule Fiji 1998 1999 - Nov Sun>=1 2:00 1:00 S Rule Fiji 1998 1999 - Nov Sun>=1 2:00 1:00 S
Rule Fiji 1999 2000 - Feb lastSun 3:00 0 - Rule Fiji 1999 2000 - Feb lastSun 3:00 0 -
@ -316,7 +330,7 @@ Rule Fiji 2010 only - Mar lastSun 3:00 0 -
Rule Fiji 2010 only - Oct 24 2:00 1:00 S Rule Fiji 2010 only - Oct 24 2:00 1:00 S
Rule Fiji 2011 only - Mar Sun>=1 3:00 0 - Rule Fiji 2011 only - Mar Sun>=1 3:00 0 -
Rule Fiji 2011 only - Oct 23 2:00 1:00 S Rule Fiji 2011 only - Oct 23 2:00 1:00 S
Rule Fiji 2012 only - Feb 26 3:00 0 - Rule Fiji 2012 only - Jan 22 3:00 0 -
# Zone NAME GMTOFF RULES FORMAT [UNTIL] # Zone NAME GMTOFF RULES FORMAT [UNTIL]
Zone Pacific/Fiji 11:53:40 - LMT 1915 Oct 26 # Suva Zone Pacific/Fiji 11:53:40 - LMT 1915 Oct 26 # Suva
12:00 Fiji FJ%sT # Fiji Time 12:00 Fiji FJ%sT # Fiji Time

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@ -1,5 +1,5 @@
# <pre> # <pre>
# @(#)backward 8.10 # @(#)backward 8.11
# This file is in the public domain, so clarified as of # This file is in the public domain, so clarified as of
# 2009-05-17 by Arthur David Olson. # 2009-05-17 by Arthur David Olson.
@ -67,6 +67,7 @@ Link America/Havana Cuba
Link Africa/Cairo Egypt Link Africa/Cairo Egypt
Link Europe/Dublin Eire Link Europe/Dublin Eire
Link Europe/London Europe/Belfast Link Europe/London Europe/Belfast
Link Europe/Chisinau Europe/Tiraspol
Link Europe/London GB Link Europe/London GB
Link Europe/London GB-Eire Link Europe/London GB-Eire
Link Etc/GMT GMT+0 Link Etc/GMT GMT+0

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@ -1,5 +1,5 @@
# <pre> # <pre>
# @(#)europe 8.39 # @(#)europe 8.40
# This file is in the public domain, so clarified as of # This file is in the public domain, so clarified as of
# 2009-05-17 by Arthur David Olson. # 2009-05-17 by Arthur David Olson.
@ -1678,6 +1678,18 @@ Zone Europe/Malta 0:58:04 - LMT 1893 Nov 2 0:00s # Valletta
# a pre-1880 LMT offset of 1:58:32. # a pre-1880 LMT offset of 1:58:32.
# #
# (which agrees with the earlier entry that had been removed) # (which agrees with the earlier entry that had been removed)
#
# From Alexander Krivenyshev (2011-10-26)
# NO need to divide Moldova into two timezones at this point.
# As of today, Transnistria (Pridnestrovie)- Tiraspol reversed its own
# decision to abolish DST this winter.
# Following Moldova and neighboring Ukraine- Transnistria (Pridnestrovie)-
# Tiraspol will go back to winter time on October 30, 2011.
# News from Moldova (in russian):
# <a href="http://ru.publika.md/link_317061.html">
# http://ru.publika.md/link_317061.html
# </a>
# Zone NAME GMTOFF RULES FORMAT [UNTIL] # Zone NAME GMTOFF RULES FORMAT [UNTIL]
Zone Europe/Chisinau 1:55:20 - LMT 1880 Zone Europe/Chisinau 1:55:20 - LMT 1880
@ -1694,21 +1706,6 @@ Zone Europe/Chisinau 1:55:20 - LMT 1880
# See Romania commentary for the guessed 1997 transition to EU rules. # See Romania commentary for the guessed 1997 transition to EU rules.
2:00 EU EE%sT 2:00 EU EE%sT
Zone Europe/Tiraspol 1:58:32 - LMT 1880
1:55 - CMT 1918 Feb 15 # Chisinau MT
1:44:24 - BMT 1931 Jul 24 # Bucharest MT
2:00 Romania EE%sT 1940 Aug 15
2:00 1:00 EEST 1941 Jul 17
1:00 C-Eur CE%sT 1944 Aug 24
3:00 Russia MSK/MSD 1990
3:00 - MSK 1990 May 6
2:00 - EET 1991
2:00 Russia EE%sT 1992
2:00 E-Eur EE%sT 1997
# See Romania commentary for the guessed 1997 transition to EU rules.
2:00 EU EE%sT 2011 Mar lastSun 1:00u
3:00 - FET # Further-eastern European Time
# Monaco # Monaco
# Shanks & Pottenger give 0:09:20 for Paris Mean Time; go with Howse's # Shanks & Pottenger give 0:09:20 for Paris Mean Time; go with Howse's
# more precise 0:09:21. # more precise 0:09:21.

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@ -1,5 +1,5 @@
# <pre> # <pre>
# @(#)northamerica 8.50 # @(#)northamerica 8.51
# This file is in the public domain, so clarified as of # This file is in the public domain, so clarified as of
# 2009-05-17 by Arthur David Olson. # 2009-05-17 by Arthur David Olson.
@ -2690,6 +2690,20 @@ Zone America/Costa_Rica -5:36:20 - LMT 1890 # San Jose
# <a href="http://www.timeanddate.com/news/time/cuba-starts-dst-2011.html"> # <a href="http://www.timeanddate.com/news/time/cuba-starts-dst-2011.html">
# http://www.timeanddate.com/news/time/cuba-starts-dst-2011.html # http://www.timeanddate.com/news/time/cuba-starts-dst-2011.html
# </a> # </a>
#
# From Steffen Thorsen (2011-10-30)
# Cuba will end DST two weeks later this year. Instead of going back
# tonight, it has been delayed to 2011-11-13 at 01:00.
#
# One source (Spanish)
# <a href="http://www.radioangulo.cu/noticias/cuba/17105-cuba-restablecera-el-horario-del-meridiano-de-greenwich.html">
# http://www.radioangulo.cu/noticias/cuba/17105-cuba-restablecera-el-horario-del-meridiano-de-greenwich.html
# </a>
#
# Our page:
# <a href="http://www.timeanddate.com/news/time/cuba-time-changes-2011.html">
# http://www.timeanddate.com/news/time/cuba-time-changes-2011.html
# </a>
# Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S # Rule NAME FROM TO TYPE IN ON AT SAVE LETTER/S
Rule Cuba 1928 only - Jun 10 0:00 1:00 D Rule Cuba 1928 only - Jun 10 0:00 1:00 D
@ -2721,12 +2735,14 @@ Rule Cuba 1997 only - Oct 12 0:00s 0 S
Rule Cuba 1998 1999 - Mar lastSun 0:00s 1:00 D Rule Cuba 1998 1999 - Mar lastSun 0:00s 1:00 D
Rule Cuba 1998 2003 - Oct lastSun 0:00s 0 S Rule Cuba 1998 2003 - Oct lastSun 0:00s 0 S
Rule Cuba 2000 2004 - Apr Sun>=1 0:00s 1:00 D Rule Cuba 2000 2004 - Apr Sun>=1 0:00s 1:00 D
Rule Cuba 2006 max - Oct lastSun 0:00s 0 S Rule Cuba 2006 2010 - Oct lastSun 0:00s 0 S
Rule Cuba 2007 only - Mar Sun>=8 0:00s 1:00 D Rule Cuba 2007 only - Mar Sun>=8 0:00s 1:00 D
Rule Cuba 2008 only - Mar Sun>=15 0:00s 1:00 D Rule Cuba 2008 only - Mar Sun>=15 0:00s 1:00 D
Rule Cuba 2009 2010 - Mar Sun>=8 0:00s 1:00 D Rule Cuba 2009 2010 - Mar Sun>=8 0:00s 1:00 D
Rule Cuba 2011 only - Mar Sun>=15 0:00s 1:00 D Rule Cuba 2011 only - Mar Sun>=15 0:00s 1:00 D
Rule Cuba 2011 only - Nov 13 0:00s 0 S
Rule Cuba 2012 max - Mar Sun>=8 0:00s 1:00 D Rule Cuba 2012 max - Mar Sun>=8 0:00s 1:00 D
Rule Cuba 2012 max - Oct lastSun 0:00s 0 S
# Zone NAME GMTOFF RULES FORMAT [UNTIL] # Zone NAME GMTOFF RULES FORMAT [UNTIL]
Zone America/Havana -5:29:28 - LMT 1890 Zone America/Havana -5:29:28 - LMT 1890

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@ -1,5 +1,5 @@
# <pre> # <pre>
# @(#)zone.tab 8.50 # @(#)zone.tab 8.52
# This file is in the public domain, so clarified as of # This file is in the public domain, so clarified as of
# 2009-05-17 by Arthur David Olson. # 2009-05-17 by Arthur David Olson.
# #
@ -257,8 +257,7 @@ LV +5657+02406 Europe/Riga
LY +3254+01311 Africa/Tripoli LY +3254+01311 Africa/Tripoli
MA +3339-00735 Africa/Casablanca MA +3339-00735 Africa/Casablanca
MC +4342+00723 Europe/Monaco MC +4342+00723 Europe/Monaco
MD +4700+02850 Europe/Chisinau most locations MD +4700+02850 Europe/Chisinau
MD +4651+02938 Europe/Tiraspol Pridnestrovie
ME +4226+01916 Europe/Podgorica ME +4226+01916 Europe/Podgorica
MF +1804-06305 America/Marigot MF +1804-06305 America/Marigot
MG -1855+04731 Indian/Antananarivo MG -1855+04731 Indian/Antananarivo

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@ -317,7 +317,7 @@ doit(struct sockaddr *fromp)
} }
if ((pam_err = pam_set_item(pamh, PAM_RUSER, ruser)) != PAM_SUCCESS || if ((pam_err = pam_set_item(pamh, PAM_RUSER, ruser)) != PAM_SUCCESS ||
(pam_err = pam_set_item(pamh, PAM_RHOST, rhost) != PAM_SUCCESS)) { (pam_err = pam_set_item(pamh, PAM_RHOST, rhost)) != PAM_SUCCESS) {
syslog(LOG_ERR|LOG_AUTH, "pam_set_item(): %s", syslog(LOG_ERR|LOG_AUTH, "pam_set_item(): %s",
pam_strerror(pamh, pam_err)); pam_strerror(pamh, pam_err));
rshd_errx(1, "Login incorrect."); rshd_errx(1, "Login incorrect.");

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@ -7176,11 +7176,15 @@ pf_test6(int dir, struct ifnet *ifp, struct mbuf **m0,
} }
#ifdef __FreeBSD__ #ifdef __FreeBSD__
if (pd.pf_mtag->flags & PF_TAG_GENERATED) if (pd.pf_mtag->flags & PF_TAG_GENERATED) {
PF_UNLOCK();
#else #else
if (m->m_pkthdr.pf.flags & PF_TAG_GENERATED) if (m->m_pkthdr.pf.flags & PF_TAG_GENERATED)
#endif #endif
return (PF_PASS); return (PF_PASS);
#ifdef __FreeBSD__
}
#endif
/* We do IP header normalization and packet reassembly here */ /* We do IP header normalization and packet reassembly here */
if (pf_normalize_ip6(m0, dir, kif, &reason, &pd) != PF_PASS) { if (pf_normalize_ip6(m0, dir, kif, &reason, &pd) != PF_PASS) {

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@ -68,13 +68,13 @@ __FBSDID("$FreeBSD$");
#include <sys/lock.h> #include <sys/lock.h>
#include <sys/module.h> #include <sys/module.h>
#include <sys/mutex.h> #include <sys/mutex.h>
#include <sys/rman.h>
#include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus.h>
#include <dev/ofw/openfirm.h> #include <dev/ofw/openfirm.h>
#include <machine/bus.h> #include <machine/bus.h>
#include <machine/ofw_machdep.h> #include <machine/ofw_machdep.h>
#include <machine/resource.h> #include <machine/resource.h>
#include <sys/rman.h>
#include <cam/cam.h> #include <cam/cam.h>
#include <cam/cam_ccb.h> #include <cam/cam_ccb.h>
@ -92,7 +92,7 @@ __FBSDID("$FreeBSD$");
struct esp_softc { struct esp_softc {
struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
struct device *sc_dev; device_t sc_dev;
struct resource *sc_res; struct resource *sc_res;
@ -102,8 +102,6 @@ struct esp_softc {
struct lsi64854_softc *sc_dma; /* pointer to my DMA */ struct lsi64854_softc *sc_dma; /* pointer to my DMA */
}; };
static devclass_t esp_devclass;
static int esp_probe(device_t); static int esp_probe(device_t);
static int esp_dma_attach(device_t); static int esp_dma_attach(device_t);
static int esp_dma_detach(device_t); static int esp_dma_detach(device_t);
@ -118,7 +116,8 @@ static device_method_t esp_dma_methods[] = {
DEVMETHOD(device_detach, esp_dma_detach), DEVMETHOD(device_detach, esp_dma_detach),
DEVMETHOD(device_suspend, esp_suspend), DEVMETHOD(device_suspend, esp_suspend),
DEVMETHOD(device_resume, esp_resume), DEVMETHOD(device_resume, esp_resume),
{0, 0}
KOBJMETHOD_END
}; };
static driver_t esp_dma_driver = { static driver_t esp_dma_driver = {
@ -136,7 +135,8 @@ static device_method_t esp_sbus_methods[] = {
DEVMETHOD(device_detach, esp_sbus_detach), DEVMETHOD(device_detach, esp_sbus_detach),
DEVMETHOD(device_suspend, esp_suspend), DEVMETHOD(device_suspend, esp_suspend),
DEVMETHOD(device_resume, esp_resume), DEVMETHOD(device_resume, esp_resume),
{0, 0}
KOBJMETHOD_END
}; };
static driver_t esp_sbus_driver = { static driver_t esp_sbus_driver = {
@ -175,7 +175,6 @@ static const struct ncr53c9x_glue const esp_sbus_glue = {
esp_dma_go, esp_dma_go,
esp_dma_stop, esp_dma_stop,
esp_dma_isactive, esp_dma_isactive,
NULL, /* gl_clear_latched_intr */
}; };
static int static int
@ -245,9 +244,9 @@ esp_sbus_attach(device_t dev)
BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */ BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */ NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ BUS_SPACE_MAXSIZE, /* maxsize */
0, /* nsegments */ BUS_SPACE_UNRESTRICTED, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ BUS_SPACE_MAXSIZE, /* maxsegsize */
0, /* flags */ 0, /* flags */
NULL, NULL, /* no locking */ NULL, NULL, /* no locking */
&lsc->sc_parent_dmat); &lsc->sc_parent_dmat);
@ -292,8 +291,10 @@ esp_sbus_attach(device_t dev)
} }
for (i = 0; i < nchildren; i++) { for (i = 0; i < nchildren; i++) {
if (device_is_attached(children[i]) && if (device_is_attached(children[i]) &&
sbus_get_slot(children[i]) == sbus_get_slot(dev) && sbus_get_slot(children[i]) ==
strcmp(ofw_bus_get_name(children[i]), "dma") == 0) { sbus_get_slot(dev) &&
strcmp(ofw_bus_get_name(children[i]),
"dma") == 0) {
/* XXX hackery */ /* XXX hackery */
esc->sc_dma = (struct lsi64854_softc *) esc->sc_dma = (struct lsi64854_softc *)
device_get_softc(children[i]); device_get_softc(children[i]);
@ -453,13 +454,6 @@ espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
NCR_LOCK_INIT(sc); NCR_LOCK_INIT(sc);
/* Attach the DMA engine. */
error = lsi64854_attach(esc->sc_dma);
if (error != 0) {
device_printf(esc->sc_dev, "lsi64854_attach failed\n");
goto fail_lock;
}
sc->sc_id = OF_getscsinitid(esc->sc_dev); sc->sc_id = OF_getscsinitid(esc->sc_dev);
#ifdef ESP_SBUS_DEBUG #ifdef ESP_SBUS_DEBUG
@ -516,9 +510,9 @@ espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
(NCRCFG2_SCSI2 | NCRCFG2_RPE)) { (NCRCFG2_SCSI2 | NCRCFG2_RPE))
sc->sc_rev = NCR_VARIANT_ESP100; sc->sc_rev = NCR_VARIANT_ESP100;
} else { else {
sc->sc_cfg2 = NCRCFG2_SCSI2; sc->sc_cfg2 = NCRCFG2_SCSI2;
NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
sc->sc_cfg3 = 0; sc->sc_cfg3 = 0;
@ -526,9 +520,9 @@ espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
if (NCR_READ_REG(sc, NCR_CFG3) != if (NCR_READ_REG(sc, NCR_CFG3) !=
(NCRCFG3_CDB | NCRCFG3_FCLK)) { (NCRCFG3_CDB | NCRCFG3_FCLK))
sc->sc_rev = NCR_VARIANT_ESP100A; sc->sc_rev = NCR_VARIANT_ESP100A;
} else { else {
/* NCRCFG2_FE enables > 64K transfers. */ /* NCRCFG2_FE enables > 64K transfers. */
sc->sc_cfg2 |= NCRCFG2_FE; sc->sc_cfg2 |= NCRCFG2_FE;
sc->sc_cfg3 = 0; sc->sc_cfg3 = 0;
@ -543,9 +537,11 @@ espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
case 0x02: case 0x02:
if ((uid & 0x07) == 0x02) if ((uid & 0x07) == 0x02)
sc->sc_rev = NCR_VARIANT_FAS216; sc->sc_rev =
NCR_VARIANT_FAS216;
else else
sc->sc_rev = NCR_VARIANT_FAS236; sc->sc_rev =
NCR_VARIANT_FAS236;
break; break;
case 0x0a: case 0x0a:
@ -560,7 +556,8 @@ espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
*/ */
device_printf(esc->sc_dev, device_printf(esc->sc_dev,
"Unknown chip\n"); "Unknown chip\n");
goto fail_lsi; error = ENXIO;
goto fail_lock;
} }
} }
} }
@ -570,12 +567,6 @@ espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
printf("%s: revision %d, uid 0x%x\n", __func__, sc->sc_rev, uid); printf("%s: revision %d, uid 0x%x\n", __func__, sc->sc_rev, uid);
#endif #endif
/*
* XXX minsync and maxxfer _should_ be set up in MI code,
* XXX but it appears to have some dependency on what sort
* XXX of DMA we're hooked up to, etc.
*/
/* /*
* This is the value used to start sync negotiations * This is the value used to start sync negotiations
* Note that the NCR register "SYNCTP" is programmed * Note that the NCR register "SYNCTP" is programmed
@ -587,31 +578,27 @@ espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
*/ */
sc->sc_minsync = 1000 / sc->sc_freq; sc->sc_minsync = 1000 / sc->sc_freq;
/*
* Except for some variants the maximum transfer size is 64k.
*/
sc->sc_maxxfer = 64 * 1024;
sc->sc_maxoffset = 15; sc->sc_maxoffset = 15;
sc->sc_extended_geom = 1; sc->sc_extended_geom = 1;
/* /*
* Alas, we must now modify the value a bit, because it's * Alas, we must now modify the value a bit, because it's
* only valid when can switch on FASTCLK and FASTSCSI bits * only valid when we can switch on FASTCLK and FASTSCSI bits
* in config register 3... * in the config register 3...
*/ */
switch (sc->sc_rev) { switch (sc->sc_rev) {
case NCR_VARIANT_ESP100: case NCR_VARIANT_ESP100:
sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT; sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
sc->sc_maxxfer = 64 * 1024;
sc->sc_minsync = 0; /* No synch on old chip? */ sc->sc_minsync = 0; /* No synch on old chip? */
break; break;
case NCR_VARIANT_ESP100A: case NCR_VARIANT_ESP100A:
sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
sc->sc_maxxfer = 64 * 1024;
/* Min clocks/byte is 5 */
sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
break;
case NCR_VARIANT_ESP200: case NCR_VARIANT_ESP200:
sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT; sc->sc_maxwidth = MSG_EXT_WDTR_BUS_8_BIT;
sc->sc_maxxfer = 16 * 1024 * 1024;
/* Min clocks/byte is 5 */ /* Min clocks/byte is 5 */
sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
break; break;
@ -642,6 +629,19 @@ espattach(struct esp_softc *esc, const struct ncr53c9x_glue *gluep)
break; break;
} }
/*
* Given that we allocate resources based on sc->sc_maxxfer it doesn't
* make sense to supply a value higher than the maximum actually used.
*/
sc->sc_maxxfer = min(sc->sc_maxxfer, MAXPHYS);
/* Attach the DMA engine. */
error = lsi64854_attach(esc->sc_dma);
if (error != 0) {
device_printf(esc->sc_dev, "lsi64854_attach failed\n");
goto fail_lock;
}
/* Establish interrupt channel. */ /* Establish interrupt channel. */
i = 0; i = 0;
if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ, if ((esc->sc_irqres = bus_alloc_resource_any(esc->sc_dev, SYS_RES_IRQ,

View File

@ -123,6 +123,8 @@ __FBSDID("$FreeBSD$");
#include <dev/esp/ncr53c9xreg.h> #include <dev/esp/ncr53c9xreg.h>
#include <dev/esp/ncr53c9xvar.h> #include <dev/esp/ncr53c9xvar.h>
devclass_t esp_devclass;
MODULE_DEPEND(esp, cam, 1, 1, 1); MODULE_DEPEND(esp, cam, 1, 1, 1);
#ifdef NCR53C9X_DEBUG #ifdef NCR53C9X_DEBUG
@ -179,8 +181,7 @@ static inline int ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc,
#define NCR_SET_COUNT(sc, size) do { \ #define NCR_SET_COUNT(sc, size) do { \
NCR_WRITE_REG((sc), NCR_TCL, (size)); \ NCR_WRITE_REG((sc), NCR_TCL, (size)); \
NCR_WRITE_REG((sc), NCR_TCM, (size) >> 8); \ NCR_WRITE_REG((sc), NCR_TCM, (size) >> 8); \
if ((sc->sc_cfg2 & NCRCFG2_FE) || \ if ((sc->sc_features & NCR_F_LARGEXFER) != 0) \
(sc->sc_rev == NCR_VARIANT_FAS366)) \
NCR_WRITE_REG((sc), NCR_TCH, (size) >> 16); \ NCR_WRITE_REG((sc), NCR_TCH, (size) >> 16); \
if (sc->sc_rev == NCR_VARIANT_FAS366) \ if (sc->sc_rev == NCR_VARIANT_FAS366) \
NCR_WRITE_REG(sc, NCR_RCH, 0); \ NCR_WRITE_REG(sc, NCR_RCH, 0); \
@ -391,6 +392,7 @@ ncr53c9x_attach(struct ncr53c9x_softc *sc)
ecb = &sc->ecb_array[i]; ecb = &sc->ecb_array[i];
ecb->sc = sc; ecb->sc = sc;
ecb->tag_id = i; ecb->tag_id = i;
callout_init_mtx(&ecb->ch, &sc->sc_lock, 0);
TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links); TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links);
} }
@ -449,10 +451,10 @@ ncr53c9x_detach(struct ncr53c9x_softc *sc)
xpt_register_async(0, ncr53c9x_async, sc->sc_sim, sc->sc_path); xpt_register_async(0, ncr53c9x_async, sc->sc_sim, sc->sc_path);
xpt_free_path(sc->sc_path); xpt_free_path(sc->sc_path);
xpt_bus_deregister(cam_sim_path(sc->sc_sim)); xpt_bus_deregister(cam_sim_path(sc->sc_sim));
cam_sim_free(sc->sc_sim, TRUE);
NCR_UNLOCK(sc); NCR_UNLOCK(sc);
cam_sim_free(sc->sc_sim, TRUE);
free(sc->ecb_array, M_DEVBUF); free(sc->ecb_array, M_DEVBUF);
free(sc->sc_tinfo, M_DEVBUF); free(sc->sc_tinfo, M_DEVBUF);
if (sc->sc_imess_self) if (sc->sc_imess_self)
@ -504,6 +506,8 @@ ncr53c9x_reset(struct ncr53c9x_softc *sc)
/* FALLTHROUGH */ /* FALLTHROUGH */
case NCR_VARIANT_ESP100A: case NCR_VARIANT_ESP100A:
sc->sc_features |= NCR_F_SELATN3; sc->sc_features |= NCR_F_SELATN3;
if ((sc->sc_cfg2 & NCRCFG2_FE) != 0)
sc->sc_features |= NCR_F_LARGEXFER;
NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
/* FALLTHROUGH */ /* FALLTHROUGH */
case NCR_VARIANT_ESP100: case NCR_VARIANT_ESP100:
@ -514,8 +518,8 @@ ncr53c9x_reset(struct ncr53c9x_softc *sc)
break; break;
case NCR_VARIANT_FAS366: case NCR_VARIANT_FAS366:
sc->sc_features |= sc->sc_features |= NCR_F_HASCFG3 | NCR_F_FASTSCSI |
NCR_F_HASCFG3 | NCR_F_FASTSCSI | NCR_F_SELATN3; NCR_F_SELATN3 | NCR_F_LARGEXFER;
sc->sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO; sc->sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO;
if (sc->sc_id > 7) if (sc->sc_id > 7)
sc->sc_cfg3 |= NCRFASCFG3_IDBIT3; sc->sc_cfg3 |= NCRFASCFG3_IDBIT3;
@ -711,9 +715,6 @@ ncr53c9x_readregs(struct ncr53c9x_softc *sc)
sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR);
if (sc->sc_glue->gl_clear_latched_intr != NULL)
(*sc->sc_glue->gl_clear_latched_intr)(sc);
/* /*
* Determine the SCSI bus phase, return either a real SCSI bus phase * Determine the SCSI bus phase, return either a real SCSI bus phase
* or some pseudo phase we use to detect certain exceptions. * or some pseudo phase we use to detect certain exceptions.
@ -806,7 +807,7 @@ ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
struct ncr53c9x_tinfo *ti; struct ncr53c9x_tinfo *ti;
uint8_t *cmd; uint8_t *cmd;
size_t dmasize; size_t dmasize;
int clen, selatn3, selatns; int clen, error, selatn3, selatns;
int lun = ecb->ccb->ccb_h.target_lun; int lun = ecb->ccb->ccb_h.target_lun;
int target = ecb->ccb->ccb_h.target_id; int target = ecb->ccb->ccb_h.target_id;
@ -887,12 +888,18 @@ ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
dmasize = clen; dmasize = clen;
sc->sc_cmdlen = clen; sc->sc_cmdlen = clen;
sc->sc_cmdp = cmd; sc->sc_cmdp = cmd;
NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); error = NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0,
&dmasize);
if (error != 0) {
sc->sc_cmdlen = 0;
sc->sc_cmdp = NULL;
goto cmd;
}
/* Program the SCSI counter. */ /* Program the SCSI counter. */
NCR_SET_COUNT(sc, dmasize); NCR_SET_COUNT(sc, dmasize);
/* Load the count in. */ /* Load the count in. */
/* if (sc->sc_rev != NCR_VARIANT_FAS366) */
NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
/* And get the target's attention. */ /* And get the target's attention. */
@ -906,6 +913,7 @@ ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb)
return; return;
} }
cmd:
/* /*
* Who am I? This is where we tell the target that we are * Who am I? This is where we tell the target that we are
* happy for it to disconnect etc. * happy for it to disconnect etc.
@ -989,13 +997,11 @@ ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
case XPT_RESET_BUS: case XPT_RESET_BUS:
ncr53c9x_init(sc, 1); ncr53c9x_init(sc, 1);
ccb->ccb_h.status = CAM_REQ_CMP; ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb); break;
return;
case XPT_CALC_GEOMETRY: case XPT_CALC_GEOMETRY:
cam_calc_geometry(&ccb->ccg, sc->sc_extended_geom); cam_calc_geometry(&ccb->ccg, sc->sc_extended_geom);
xpt_done(ccb); break;
return;
case XPT_PATH_INQ: case XPT_PATH_INQ:
cpi = &ccb->cpi; cpi = &ccb->cpi;
@ -1009,19 +1015,19 @@ ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
cpi->max_target = sc->sc_ntarg - 1; cpi->max_target = sc->sc_ntarg - 1;
cpi->max_lun = 7; cpi->max_lun = 7;
cpi->initiator_id = sc->sc_id; cpi->initiator_id = sc->sc_id;
cpi->bus_id = 0;
cpi->base_transfer_speed = 3300;
strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
strncpy(cpi->hba_vid, "Sun", HBA_IDLEN); strncpy(cpi->hba_vid, "NCR", HBA_IDLEN);
strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
cpi->unit_number = cam_sim_unit(sim); cpi->unit_number = cam_sim_unit(sim);
cpi->transport = XPORT_SPI; cpi->bus_id = 0;
cpi->transport_version = 2; cpi->base_transfer_speed = 3300;
cpi->protocol = PROTO_SCSI; cpi->protocol = PROTO_SCSI;
cpi->protocol_version = SCSI_REV_2; cpi->protocol_version = SCSI_REV_2;
cpi->transport = XPORT_SPI;
cpi->transport_version = 2;
cpi->maxio = sc->sc_maxxfer;
ccb->ccb_h.status = CAM_REQ_CMP; ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb); break;
return;
case XPT_GET_TRAN_SETTINGS: case XPT_GET_TRAN_SETTINGS:
cts = &ccb->cts; cts = &ccb->cts;
@ -1064,28 +1070,24 @@ ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
CTS_SPI_VALID_DISC; CTS_SPI_VALID_DISC;
scsi->valid = CTS_SCSI_VALID_TQ; scsi->valid = CTS_SCSI_VALID_TQ;
ccb->ccb_h.status = CAM_REQ_CMP; ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb); break;
return;
case XPT_ABORT: case XPT_ABORT:
device_printf(sc->sc_dev, "XPT_ABORT called\n"); device_printf(sc->sc_dev, "XPT_ABORT called\n");
ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
xpt_done(ccb); break;
return;
case XPT_TERM_IO: case XPT_TERM_IO:
device_printf(sc->sc_dev, "XPT_TERM_IO called\n"); device_printf(sc->sc_dev, "XPT_TERM_IO called\n");
ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
xpt_done(ccb); break;
return;
case XPT_RESET_DEV: case XPT_RESET_DEV:
case XPT_SCSI_IO: case XPT_SCSI_IO:
if (ccb->ccb_h.target_id < 0 || if (ccb->ccb_h.target_id < 0 ||
ccb->ccb_h.target_id >= sc->sc_ntarg) { ccb->ccb_h.target_id >= sc->sc_ntarg) {
ccb->ccb_h.status = CAM_PATH_INVALID; ccb->ccb_h.status = CAM_PATH_INVALID;
xpt_done(ccb); goto done;
return;
} }
/* Get an ECB to use. */ /* Get an ECB to use. */
ecb = ncr53c9x_get_ecb(sc); ecb = ncr53c9x_get_ecb(sc);
@ -1097,8 +1099,7 @@ ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
xpt_freeze_simq(sim, 1); xpt_freeze_simq(sim, 1);
ccb->ccb_h.status = CAM_REQUEUE_REQ; ccb->ccb_h.status = CAM_REQUEUE_REQ;
device_printf(sc->sc_dev, "unable to allocate ecb\n"); device_printf(sc->sc_dev, "unable to allocate ecb\n");
xpt_done(ccb); goto done;
return;
} }
/* Initialize ecb. */ /* Initialize ecb. */
@ -1127,7 +1128,7 @@ ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
ecb->flags |= ECB_READY; ecb->flags |= ECB_READY;
if (sc->sc_state == NCR_IDLE) if (sc->sc_state == NCR_IDLE)
ncr53c9x_sched(sc); ncr53c9x_sched(sc);
break; return;
case XPT_SET_TRAN_SETTINGS: case XPT_SET_TRAN_SETTINGS:
cts = &ccb->cts; cts = &ccb->cts;
@ -1165,16 +1166,16 @@ ncr53c9x_action(struct cam_sim *sim, union ccb *ccb)
} }
ccb->ccb_h.status = CAM_REQ_CMP; ccb->ccb_h.status = CAM_REQ_CMP;
xpt_done(ccb); break;
return;
default: default:
device_printf(sc->sc_dev, "Unhandled function code %d\n", device_printf(sc->sc_dev, "Unhandled function code %d\n",
ccb->ccb_h.func_code); ccb->ccb_h.func_code);
ccb->ccb_h.status = CAM_PROVIDE_FAIL; ccb->ccb_h.status = CAM_PROVIDE_FAIL;
xpt_done(ccb);
return;
} }
done:
xpt_done(ccb);
} }
/* /*
@ -2030,8 +2031,8 @@ ncr53c9x_msgin(struct ncr53c9x_softc *sc)
default: default:
xpt_print_path(ecb->ccb->ccb_h.path); xpt_print_path(ecb->ccb->ccb_h.path);
printf("unrecognized MESSAGE EXTENDED;" printf("unrecognized MESSAGE EXTENDED 0x%x;"
" sending REJECT\n"); " sending REJECT\n", sc->sc_imess[2]);
goto reject; goto reject;
} }
break; break;
@ -2039,7 +2040,8 @@ ncr53c9x_msgin(struct ncr53c9x_softc *sc)
default: default:
NCR_MSGS(("ident ")); NCR_MSGS(("ident "));
xpt_print_path(ecb->ccb->ccb_h.path); xpt_print_path(ecb->ccb->ccb_h.path);
printf("unrecognized MESSAGE; sending REJECT\n"); printf("unrecognized MESSAGE 0x%x; sending REJECT\n",
sc->sc_imess[0]);
/* FALLTHROUGH */ /* FALLTHROUGH */
reject: reject:
ncr53c9x_sched_msgout(SEND_REJECT); ncr53c9x_sched_msgout(SEND_REJECT);
@ -2109,6 +2111,7 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
struct ncr53c9x_tinfo *ti; struct ncr53c9x_tinfo *ti;
struct ncr53c9x_ecb *ecb; struct ncr53c9x_ecb *ecb;
size_t size; size_t size;
int error;
#ifdef NCR53C9X_DEBUG #ifdef NCR53C9X_DEBUG
int i; int i;
#endif #endif
@ -2246,17 +2249,14 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
NCR_MSGS(("> ")); NCR_MSGS(("> "));
} }
#endif #endif
if (sc->sc_rev == NCR_VARIANT_FAS366) {
/* if (sc->sc_rev != NCR_VARIANT_FAS366) {
* XXX FIFO size
*/
ncr53c9x_flushfifo(sc);
ncr53c9x_wrfifo(sc, sc->sc_omp, sc->sc_omlen);
NCRCMD(sc, NCRCMD_TRANS);
} else {
/* (Re)send the message. */ /* (Re)send the message. */
size = ulmin(sc->sc_omlen, sc->sc_maxxfer); size = ulmin(sc->sc_omlen, sc->sc_maxxfer);
NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); error = NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size);
if (error != 0)
goto cmd;
/* Program the SCSI counter. */ /* Program the SCSI counter. */
NCR_SET_COUNT(sc, size); NCR_SET_COUNT(sc, size);
@ -2264,7 +2264,16 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA);
NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA);
NCRDMA_GO(sc); NCRDMA_GO(sc);
return;
} }
cmd:
/*
* XXX FIFO size
*/
ncr53c9x_flushfifo(sc);
ncr53c9x_wrfifo(sc, sc->sc_omp, sc->sc_omlen);
NCRCMD(sc, NCRCMD_TRANS);
} }
void void
@ -2299,7 +2308,7 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
struct ncr53c9x_tinfo *ti; struct ncr53c9x_tinfo *ti;
struct timeval cur, wait; struct timeval cur, wait;
size_t size; size_t size;
int i, nfifo; int error, i, nfifo;
uint8_t msg; uint8_t msg;
NCR_LOCK_ASSERT(sc, MA_OWNED); NCR_LOCK_ASSERT(sc, MA_OWNED);
@ -2974,8 +2983,14 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
size = ecb->clen; size = ecb->clen;
sc->sc_cmdlen = size; sc->sc_cmdlen = size;
sc->sc_cmdp = (void *)&ecb->cmd.cmd; sc->sc_cmdp = (void *)&ecb->cmd.cmd;
NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, error = NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen,
0, &size); 0, &size);
if (error != 0) {
sc->sc_cmdlen = 0;
sc->sc_cmdp = NULL;
goto cmd;
}
/* Program the SCSI counter. */ /* Program the SCSI counter. */
NCR_SET_COUNT(sc, size); NCR_SET_COUNT(sc, size);
@ -2985,30 +3000,51 @@ ncr53c9x_intr1(struct ncr53c9x_softc *sc)
/* Start the command transfer. */ /* Start the command transfer. */
NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA);
NCRDMA_GO(sc); NCRDMA_GO(sc);
} else { sc->sc_prevphase = COMMAND_PHASE;
ncr53c9x_wrfifo(sc, (uint8_t *)&ecb->cmd.cmd, break;
ecb->clen);
NCRCMD(sc, NCRCMD_TRANS);
} }
cmd:
ncr53c9x_wrfifo(sc, (uint8_t *)&ecb->cmd.cmd, ecb->clen);
NCRCMD(sc, NCRCMD_TRANS);
sc->sc_prevphase = COMMAND_PHASE; sc->sc_prevphase = COMMAND_PHASE;
break; break;
case DATA_OUT_PHASE: case DATA_OUT_PHASE:
NCR_PHASE(("DATA_OUT_PHASE [%ld] ", (long)sc->sc_dleft)); NCR_PHASE(("DATA_OUT_PHASE [%ld] ", (long)sc->sc_dleft));
sc->sc_prevphase = DATA_OUT_PHASE;
NCRCMD(sc, NCRCMD_FLUSH); NCRCMD(sc, NCRCMD_FLUSH);
size = ulmin(sc->sc_dleft, sc->sc_maxxfer); size = ulmin(sc->sc_dleft, sc->sc_maxxfer);
NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 0, &size); error = NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 0, &size);
sc->sc_prevphase = DATA_OUT_PHASE;
goto setup_xfer; goto setup_xfer;
case DATA_IN_PHASE: case DATA_IN_PHASE:
NCR_PHASE(("DATA_IN_PHASE ")); NCR_PHASE(("DATA_IN_PHASE "));
sc->sc_prevphase = DATA_IN_PHASE;
if (sc->sc_rev == NCR_VARIANT_ESP100) if (sc->sc_rev == NCR_VARIANT_ESP100)
NCRCMD(sc, NCRCMD_FLUSH); NCRCMD(sc, NCRCMD_FLUSH);
size = ulmin(sc->sc_dleft, sc->sc_maxxfer); size = ulmin(sc->sc_dleft, sc->sc_maxxfer);
NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1, &size); error = NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1, &size);
sc->sc_prevphase = DATA_IN_PHASE; setup_xfer:
setup_xfer: if (error != 0) {
switch (error) {
case EFBIG:
ecb->ccb->ccb_h.status |= CAM_REQ_TOO_BIG;
break;
case EINPROGRESS:
panic("%s: cannot deal with deferred DMA",
__func__);
case EINVAL:
ecb->ccb->ccb_h.status |= CAM_REQ_INVALID;
break;
case ENOMEM:
ecb->ccb->ccb_h.status |= CAM_REQUEUE_REQ;
break;
default:
ecb->ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
}
goto finish;
}
/* Target returned to data phase: wipe "done" memory */ /* Target returned to data phase: wipe "done" memory */
ecb->flags &= ~ECB_TENTATIVE_DONE; ecb->flags &= ~ECB_TENTATIVE_DONE;

View File

@ -31,6 +31,9 @@
/* $FreeBSD$ */ /* $FreeBSD$ */
#ifndef _NCR53C9XREG_H_
#define _NCR53C9XREG_H_
/* /*
* Register addresses, relative to some base address * Register addresses, relative to some base address
*/ */
@ -288,3 +291,4 @@
#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */ #define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */
#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */ #define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */
#endif /* _NCR53C9XREG_H_ */

View File

@ -68,8 +68,8 @@
/* $FreeBSD$ */ /* $FreeBSD$ */
#ifndef _DEV_IC_NCR53C9XVAR_H_ #ifndef _NCR53C9XVAR_H_
#define _DEV_IC_NCR53C9XVAR_H_ #define _NCR53C9XVAR_H_
#include <sys/lock.h> #include <sys/lock.h>
@ -115,7 +115,8 @@
* scsi_status,sense_data}. * scsi_status,sense_data}.
*/ */
struct ncr53c9x_ecb { struct ncr53c9x_ecb {
/* These fields are preserved between alloc and free */ /* These fields are preserved between alloc and free. */
struct callout ch;
struct ncr53c9x_softc *sc; struct ncr53c9x_softc *sc;
int tag_id; int tag_id;
int flags; int flags;
@ -130,7 +131,6 @@ struct ncr53c9x_ecb {
#define ECB_RESET 0x80 #define ECB_RESET 0x80
#define ECB_TENTATIVE_DONE 0x100 #define ECB_TENTATIVE_DONE 0x100
int timeout; int timeout;
struct callout ch;
struct { struct {
uint8_t msg[3]; /* Selection Id msg and tags */ uint8_t msg[3]; /* Selection Id msg and tags */
@ -290,7 +290,7 @@ extern int ncr53c9x_debug;
struct ncr53c9x_softc; struct ncr53c9x_softc;
/* /*
* Function switch used as glue to MD code. * Function switch used as glue to MD code
*/ */
struct ncr53c9x_glue { struct ncr53c9x_glue {
/* Mandatory entry points. */ /* Mandatory entry points. */
@ -304,9 +304,6 @@ struct ncr53c9x_glue {
void (*gl_dma_go)(struct ncr53c9x_softc *); void (*gl_dma_go)(struct ncr53c9x_softc *);
void (*gl_dma_stop)(struct ncr53c9x_softc *); void (*gl_dma_stop)(struct ncr53c9x_softc *);
int (*gl_dma_isactive)(struct ncr53c9x_softc *); int (*gl_dma_isactive)(struct ncr53c9x_softc *);
/* Optional entry points. */
void (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
}; };
struct ncr53c9x_softc { struct ncr53c9x_softc {
@ -330,7 +327,7 @@ struct ncr53c9x_softc {
uint8_t sc_ccf; /* Clock Conversion */ uint8_t sc_ccf; /* Clock Conversion */
uint8_t sc_timeout; uint8_t sc_timeout;
/* register copies, see espreadregs() */ /* register copies, see ncr53c9x_readregs() */
uint8_t sc_espintr; uint8_t sc_espintr;
uint8_t sc_espstat; uint8_t sc_espstat;
uint8_t sc_espstep; uint8_t sc_espstep;
@ -415,6 +412,7 @@ struct ncr53c9x_softc {
#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ #define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
#define NCR_F_DMASELECT 0x04 /* can do dmaselect */ #define NCR_F_DMASELECT 0x04 /* can do dmaselect */
#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */ #define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */
#define NCR_F_LARGEXFER 0x10 /* chip supports transfers > 64k */
/* values for sc_msgout */ /* values for sc_msgout */
#define SEND_DEV_RESET 0x0001 #define SEND_DEV_RESET 0x0001
@ -499,8 +497,10 @@ struct ncr53c9x_softc {
#define ncr53c9x_cpb2stp(sc, cpb) \ #define ncr53c9x_cpb2stp(sc, cpb) \
((250 * (cpb)) / (sc)->sc_freq) ((250 * (cpb)) / (sc)->sc_freq)
extern devclass_t esp_devclass;
int ncr53c9x_attach(struct ncr53c9x_softc *sc); int ncr53c9x_attach(struct ncr53c9x_softc *sc);
int ncr53c9x_detach(struct ncr53c9x_softc *sc); int ncr53c9x_detach(struct ncr53c9x_softc *sc);
void ncr53c9x_intr(void *arg); void ncr53c9x_intr(void *arg);
#endif /* _DEV_IC_NCR53C9XVAR_H_ */ #endif /* _NCR53C9XVAR_H_ */

View File

@ -1370,6 +1370,11 @@ g_md_dumpconf(struct sbuf *sb, const char *indent, struct g_geom *gp,
indent, (uintmax_t) mp->fwsectors); indent, (uintmax_t) mp->fwsectors);
sbuf_printf(sb, "%s<length>%ju</length>\n", sbuf_printf(sb, "%s<length>%ju</length>\n",
indent, (uintmax_t) mp->mediasize); indent, (uintmax_t) mp->mediasize);
sbuf_printf(sb, "%s<compression>%s</compression>\n", indent,
(mp->flags & MD_COMPRESS) == 0 ? "off": "on");
sbuf_printf(sb, "%s<access>%s</access>\n", indent,
(mp->flags & MD_READONLY) == 0 ? "read-write":
"read-only");
sbuf_printf(sb, "%s<type>%s</type>\n", indent, sbuf_printf(sb, "%s<type>%s</type>\n", indent,
type); type);
if (mp->type == MD_VNODE && mp->vnode != NULL) if (mp->type == MD_VNODE && mp->vnode != NULL)

View File

@ -233,9 +233,9 @@ dma_attach(device_t dev)
BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */ BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */ NULL, NULL, /* filter, filterarg */
BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ BUS_SPACE_MAXSIZE, /* maxsize */
0, /* nsegments */ BUS_SPACE_UNRESTRICTED, /* nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ BUS_SPACE_MAXSIZE, /* maxsegsize */
0, /* flags */ 0, /* flags */
NULL, NULL, /* no locking */ NULL, NULL, /* no locking */
&lsc->sc_parent_dmat); &lsc->sc_parent_dmat);

View File

@ -94,7 +94,12 @@ int lsi64854debug = 0;
#define DPRINTF(a,x) #define DPRINTF(a,x)
#endif #endif
#define MAX_DMA_SZ (16*1024*1024) /*
* The rules say we cannot transfer more than the limit of this DMA chip (64k
* for old and 16Mb for new), and we cannot cross a 16Mb boundary.
*/
#define MAX_DMA_SZ (64 * 1024)
#define BOUNDARY (16 * 1024 * 1024)
static void lsi64854_reset(struct lsi64854_softc *); static void lsi64854_reset(struct lsi64854_softc *);
static void lsi64854_map_scsi(void *, bus_dma_segment_t *, int, int); static void lsi64854_map_scsi(void *, bus_dma_segment_t *, int, int);
@ -125,6 +130,7 @@ lsi64854_attach(struct lsi64854_softc *sc)
lockfunc = NULL; lockfunc = NULL;
lockfuncarg = NULL; lockfuncarg = NULL;
sc->sc_maxdmasize = MAX_DMA_SZ;
switch (sc->sc_channel) { switch (sc->sc_channel) {
case L64854_CHANNEL_SCSI: case L64854_CHANNEL_SCSI:
@ -135,6 +141,7 @@ lsi64854_attach(struct lsi64854_softc *sc)
} }
lockfunc = busdma_lock_mutex; lockfunc = busdma_lock_mutex;
lockfuncarg = &nsc->sc_lock; lockfuncarg = &nsc->sc_lock;
sc->sc_maxdmasize = nsc->sc_maxxfer;
sc->intr = lsi64854_scsi_intr; sc->intr = lsi64854_scsi_intr;
sc->setup = lsi64854_setup; sc->setup = lsi64854_setup;
break; break;
@ -153,13 +160,13 @@ lsi64854_attach(struct lsi64854_softc *sc)
if (sc->setup != NULL) { if (sc->setup != NULL) {
error = bus_dma_tag_create( error = bus_dma_tag_create(
sc->sc_parent_dmat, /* parent */ sc->sc_parent_dmat, /* parent */
1, 0, /* alignment, boundary */ 1, BOUNDARY, /* alignment, boundary */
BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */ BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */ NULL, NULL, /* filter, filterarg */
MAX_DMA_SZ, /* maxsize */ sc->sc_maxdmasize, /* maxsize */
1, /* nsegments */ 1, /* nsegments */
MAX_DMA_SZ, /* maxsegsize */ sc->sc_maxdmasize, /* maxsegsize */
BUS_DMA_ALLOCNOW, /* flags */ BUS_DMA_ALLOCNOW, /* flags */
lockfunc, lockfuncarg, /* lockfunc, lockfuncarg */ lockfunc, lockfuncarg, /* lockfunc, lockfuncarg */
&sc->sc_buffer_dmat); &sc->sc_buffer_dmat);
@ -261,13 +268,14 @@ lsi64854_detach(struct lsi64854_softc *sc)
else \ else \
csr |= L64854_INVALIDATE; \ csr |= L64854_INVALIDATE; \
\ \
L64854_SCSR(sc,csr); \ L64854_SCSR(sc, csr); \
} \ } \
/* \ /* \
* Wait for draining to finish \ * Wait for draining to finish \
* rev0 & rev1 call this PACKCNT \ * rev0 & rev1 call this PACKCNT \
*/ \ */ \
DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", \
dontpanic); \
} while (/* CONSTCOND */0) } while (/* CONSTCOND */0)
#define DMA_FLUSH(sc, dontpanic) do { \ #define DMA_FLUSH(sc, dontpanic) do { \
@ -282,12 +290,14 @@ lsi64854_detach(struct lsi64854_softc *sc)
csr = L64854_GCSR(sc); \ csr = L64854_GCSR(sc); \
csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ csr |= L64854_INVALIDATE; /* XXX FAS ? */ \
L64854_SCSR(sc,csr); \ L64854_SCSR(sc, csr); \
} while (/* CONSTCOND */0) } while (/* CONSTCOND */0)
static void static void
lsi64854_reset(struct lsi64854_softc *sc) lsi64854_reset(struct lsi64854_softc *sc)
{ {
bus_dma_tag_t dmat;
bus_dmamap_t dmam;
uint32_t csr; uint32_t csr;
DMA_FLUSH(sc, 1); DMA_FLUSH(sc, 1);
@ -296,10 +306,11 @@ lsi64854_reset(struct lsi64854_softc *sc)
DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr)); DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr));
if (sc->sc_dmasize != 0) { if (sc->sc_dmasize != 0) {
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, dmat = sc->sc_buffer_dmat;
(csr & D_WRITE) != 0 ? BUS_DMASYNC_PREREAD : dmam = sc->sc_dmamap;
BUS_DMASYNC_PREWRITE); bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
bus_dmamap_unload(dmat, dmam);
} }
if (sc->sc_rev == DMAREV_HME) if (sc->sc_rev == DMAREV_HME)
@ -364,15 +375,16 @@ lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error)
sc = (struct lsi64854_softc *)arg; sc = (struct lsi64854_softc *)arg;
if (error != 0)
return;
if (nseg != 1) if (nseg != 1)
panic("%s: cannot map %d segments\n", __func__, nseg); panic("%s: cannot map %d segments\n", __func__, nseg);
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
sc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); sc->sc_datain != 0 ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
bus_write_4(sc->sc_res, L64854_REG_ADDR, segs[0].ds_addr); bus_write_4(sc->sc_res, L64854_REG_ADDR, segs[0].ds_addr);
} }
#define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ - 1)))
/* /*
* setup a DMA transfer * setup a DMA transfer
*/ */
@ -381,6 +393,7 @@ lsi64854_setup(struct lsi64854_softc *sc, void **addr, size_t *len,
int datain, size_t *dmasize) int datain, size_t *dmasize)
{ {
long bcnt; long bcnt;
int error;
uint32_t csr; uint32_t csr;
DMA_FLUSH(sc, 0); DMA_FLUSH(sc, 0);
@ -392,15 +405,12 @@ lsi64854_setup(struct lsi64854_softc *sc, void **addr, size_t *len,
sc->sc_dmalen = len; sc->sc_dmalen = len;
sc->sc_datain = datain; sc->sc_datain = datain;
/* KASSERT(*dmasize <= sc->sc_maxdmasize,
* The rules say we cannot transfer more than the limit ("%s: transfer size %ld too large", __func__, (long)*dmasize));
* of this DMA chip (64k for old and 16Mb for new),
* and we cannot cross a 16Mb boundary.
*/
*dmasize = sc->sc_dmasize =
ulmin(*dmasize, DMAMAX((size_t)*sc->sc_dmaaddr));
DPRINTF(LDB_ANY, ("%s: dmasize=%ld\n", __func__, (long)sc->sc_dmasize)); sc->sc_dmasize = *dmasize;
DPRINTF(LDB_ANY, ("%s: dmasize=%ld\n", __func__, (long)*dmasize));
/* /*
* XXX what length? * XXX what length?
@ -412,24 +422,31 @@ lsi64854_setup(struct lsi64854_softc *sc, void **addr, size_t *len,
bus_write_4(sc->sc_res, L64854_REG_CNT, *dmasize); bus_write_4(sc->sc_res, L64854_REG_CNT, *dmasize);
} }
/* Program the DMA address */ /*
if (sc->sc_dmasize != 0) * Load the transfer buffer and program the DMA address.
if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap, * Note that the NCR53C9x core can't handle EINPROGRESS so we set
*sc->sc_dmaaddr, sc->sc_dmasize, lsi64854_map_scsi, sc, 0)) * BUS_DMA_NOWAIT.
panic("%s: cannot allocate DVMA address", __func__); */
if (*dmasize != 0) {
error = bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
*sc->sc_dmaaddr, *dmasize, lsi64854_map_scsi, sc,
BUS_DMA_NOWAIT);
if (error != 0)
return (error);
}
if (sc->sc_rev == DMAREV_ESC) { if (sc->sc_rev == DMAREV_ESC) {
/* DMA ESC chip bug work-around */ /* DMA ESC chip bug work-around */
bcnt = sc->sc_dmasize; bcnt = *dmasize;
if (((bcnt + (long)*sc->sc_dmaaddr) & PAGE_MASK_8K) != 0) if (((bcnt + (long)*sc->sc_dmaaddr) & PAGE_MASK_8K) != 0)
bcnt = roundup(bcnt, PAGE_SIZE_8K); bcnt = roundup(bcnt, PAGE_SIZE_8K);
bus_write_4(sc->sc_res, L64854_REG_CNT, bcnt); bus_write_4(sc->sc_res, L64854_REG_CNT, bcnt);
} }
/* Setup DMA control register */ /* Setup the DMA control register. */
csr = L64854_GCSR(sc); csr = L64854_GCSR(sc);
if (datain) if (datain != 0)
csr |= L64854_WRITE; csr |= L64854_WRITE;
else else
csr &= ~L64854_WRITE; csr &= ~L64854_WRITE;
@ -455,7 +472,10 @@ lsi64854_scsi_intr(void *arg)
{ {
struct lsi64854_softc *sc = arg; struct lsi64854_softc *sc = arg;
struct ncr53c9x_softc *nsc = sc->sc_client; struct ncr53c9x_softc *nsc = sc->sc_client;
int trans, resid; bus_dma_tag_t dmat;
bus_dmamap_t dmam;
size_t dmasize;
int lxfer, resid, trans;
uint32_t csr; uint32_t csr;
csr = L64854_GCSR(sc); csr = L64854_GCSR(sc);
@ -463,11 +483,12 @@ lsi64854_scsi_intr(void *arg)
DPRINTF(LDB_SCSI, ("%s: addr 0x%x, csr %b\n", __func__, DPRINTF(LDB_SCSI, ("%s: addr 0x%x, csr %b\n", __func__,
bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, DDMACSR_BITS)); bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, DDMACSR_BITS));
if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { if (csr & (D_ERR_PEND | D_SLAVE_ERR)) {
device_printf(sc->sc_dev, "error: csr=%b\n", csr, DDMACSR_BITS); device_printf(sc->sc_dev, "error: csr=%b\n", csr,
csr &= ~D_EN_DMA; /* Stop DMA */ DDMACSR_BITS);
csr &= ~D_EN_DMA; /* Stop DMA. */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= D_INVALIDATE|D_SLAVE_ERR; csr |= D_INVALIDATE | D_SLAVE_ERR;
L64854_SCSR(sc, csr); L64854_SCSR(sc, csr);
return (-1); return (-1);
} }
@ -483,10 +504,11 @@ lsi64854_scsi_intr(void *arg)
L64854_SCSR(sc, csr); L64854_SCSR(sc, csr);
sc->sc_active = 0; sc->sc_active = 0;
if (sc->sc_dmasize == 0) { dmasize = sc->sc_dmasize;
/* A "Transfer Pad" operation completed */ if (dmasize == 0) {
DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, tcm=%d)\n", /* A "Transfer Pad" operation completed. */
__func__, NCR_READ_REG(nsc, NCR_TCL) | DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, "
"tcm=%d)\n", __func__, NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8), (NCR_READ_REG(nsc, NCR_TCM) << 8),
NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM))); NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM)));
return (0); return (0);
@ -499,7 +521,7 @@ lsi64854_scsi_intr(void *arg)
* as residual since the NCR53C9X counter registers get decremented * as residual since the NCR53C9X counter registers get decremented
* as bytes are clocked into the FIFO. * as bytes are clocked into the FIFO.
*/ */
if (!(csr & D_WRITE) && if ((csr & D_WRITE) == 0 &&
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
DPRINTF(LDB_SCSI, ("%s: empty esp FIFO of %d ", __func__, DPRINTF(LDB_SCSI, ("%s: empty esp FIFO of %d ", __func__,
resid)); resid));
@ -509,22 +531,21 @@ lsi64854_scsi_intr(void *arg)
} }
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
lxfer = nsc->sc_features & NCR_F_LARGEXFER;
/* /*
* `Terminal count' is off, so read the residue * "Terminal count" is off, so read the residue
* out of the NCR53C9X counter registers. * out of the NCR53C9X counter registers.
*/ */
resid += (NCR_READ_REG(nsc, NCR_TCL) | resid += (NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8) | (NCR_READ_REG(nsc, NCR_TCM) << 8) |
((nsc->sc_cfg2 & NCRCFG2_FE) ? (lxfer != 0 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0));
(NCR_READ_REG(nsc, NCR_TCH) << 16) : 0));
if (resid == 0 && sc->sc_dmasize == 65536 && if (resid == 0 && dmasize == 65536 && lxfer == 0)
(nsc->sc_cfg2 & NCRCFG2_FE) == 0) /* A transfer of 64k is encoded as TCL=TCM=0. */
/* A transfer of 64K is encoded as `TCL=TCM=0' */
resid = 65536; resid = 65536;
} }
trans = sc->sc_dmasize - resid; trans = dmasize - resid;
if (trans < 0) { /* transferred < 0? */ if (trans < 0) { /* transferred < 0? */
#if 0 #if 0
/* /*
@ -533,21 +554,22 @@ lsi64854_scsi_intr(void *arg)
* another target. As such, don't print the warning. * another target. As such, don't print the warning.
*/ */
device_printf(sc->sc_dev, "xfer (%d) > req (%d)\n", trans, device_printf(sc->sc_dev, "xfer (%d) > req (%d)\n", trans,
sc->sc_dmasize); dmasize);
#endif #endif
trans = sc->sc_dmasize; trans = dmasize;
} }
DPRINTF(LDB_SCSI, ("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", DPRINTF(LDB_SCSI, ("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
__func__, NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM), __func__, NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM),
(nsc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(nsc, NCR_TCH) : 0, (nsc->sc_sc_features & NCR_F_LARGEXFER) != 0 ?
trans, resid)); NCR_READ_REG(nsc, NCR_TCH) : 0, trans, resid));
if (sc->sc_dmasize != 0) { if (dmasize != 0) {
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, dmat = sc->sc_buffer_dmat;
(csr & D_WRITE) != 0 ? BUS_DMASYNC_POSTREAD : dmam = sc->sc_dmamap;
BUS_DMASYNC_POSTWRITE); bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(dmat, dmam);
} }
*sc->sc_dmalen -= trans; *sc->sc_dmalen -= trans;
@ -565,7 +587,7 @@ lsi64854_scsi_intr(void *arg)
} }
/* /*
* Pseudo (chained) interrupt to le driver to handle DMA errors. * Pseudo (chained) interrupt to le(4) driver to handle DMA errors
*/ */
static int static int
lsi64854_enet_intr(void *arg) lsi64854_enet_intr(void *arg)
@ -579,11 +601,12 @@ lsi64854_enet_intr(void *arg)
/* If the DMA logic shows an interrupt, claim it */ /* If the DMA logic shows an interrupt, claim it */
rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { if (csr & (E_ERR_PEND | E_SLAVE_ERR)) {
device_printf(sc->sc_dev, "error: csr=%b\n", csr, EDMACSR_BITS); device_printf(sc->sc_dev, "error: csr=%b\n", csr,
csr &= ~L64854_EN_DMA; /* Stop DMA */ EDMACSR_BITS);
csr &= ~L64854_EN_DMA; /* Stop DMA. */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= E_INVALIDATE|E_SLAVE_ERR; csr |= E_INVALIDATE | E_SLAVE_ERR;
L64854_SCSR(sc, csr); L64854_SCSR(sc, csr);
/* Will be drained with the LE_C0_IDON interrupt. */ /* Will be drained with the LE_C0_IDON interrupt. */
sc->sc_dodrain = 1; sc->sc_dodrain = 1;
@ -610,23 +633,26 @@ lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
sc = (struct lsi64854_softc *)arg; sc = (struct lsi64854_softc *)arg;
if (error != 0)
return;
if (nsegs != 1) if (nsegs != 1)
panic("%s: cannot map %d segments\n", __func__, nsegs); panic("%s: cannot map %d segments\n", __func__, nsegs);
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ? bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap,
BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); sc->sc_datain != 0 ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
bus_write_4(sc->sc_res, L64854_REG_ADDR, segs[0].ds_addr); bus_write_4(sc->sc_res, L64854_REG_ADDR, segs[0].ds_addr);
bus_write_4(sc->sc_res, L64854_REG_CNT, sc->sc_dmasize); bus_write_4(sc->sc_res, L64854_REG_CNT, sc->sc_dmasize);
} }
/* /*
* setup a DMA transfer * Setup a DMA transfer.
*/ */
static int static int
lsi64854_setup_pp(struct lsi64854_softc *sc, void **addr, size_t *len, lsi64854_setup_pp(struct lsi64854_softc *sc, void **addr, size_t *len,
int datain, size_t *dmasize) int datain, size_t *dmasize)
{ {
int error;
uint32_t csr; uint32_t csr;
DMA_FLUSH(sc, 0); DMA_FLUSH(sc, 0);
@ -636,25 +662,25 @@ lsi64854_setup_pp(struct lsi64854_softc *sc, void **addr, size_t *len,
sc->sc_datain = datain; sc->sc_datain = datain;
DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", __func__, DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", __func__,
(long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain != 0 ? 1 : 0));
/* KASSERT(*dmasize <= sc->sc_maxdmasize,
* the rules say we cannot transfer more than the limit ("%s: transfer size %ld too large", __func__, (long)*dmasize));
* of this DMA chip (64k for old and 16Mb for new),
* and we cannot cross a 16Mb boundary.
*/
*dmasize = sc->sc_dmasize =
ulmin(*dmasize, DMAMAX((size_t)*sc->sc_dmaaddr));
DPRINTF(LDB_PP, ("%s: dmasize=%ld\n", __func__, (long)sc->sc_dmasize)); sc->sc_dmasize = *dmasize;
/* Program the DMA address */ DPRINTF(LDB_PP, ("%s: dmasize=%ld\n", __func__, (long)*dmasize));
if (sc->sc_dmasize != 0)
if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize, lsi64854_map_pp, sc, 0))
panic("%s: pp cannot allocate DVMA address", __func__);
/* Setup DMA control register */ /* Load the transfer buffer and program the DMA address. */
if (*dmasize != 0) {
error = bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap,
*sc->sc_dmaaddr, *dmasize, lsi64854_map_pp, sc,
BUS_DMA_NOWAIT);
if (error != 0)
return (error);
}
/* Setup the DMA control register. */
csr = L64854_GCSR(sc); csr = L64854_GCSR(sc);
csr &= ~L64854_BURST_SIZE; csr &= ~L64854_BURST_SIZE;
if (sc->sc_burst == 32) if (sc->sc_burst == 32)
@ -663,10 +689,10 @@ lsi64854_setup_pp(struct lsi64854_softc *sc, void **addr, size_t *len,
csr |= L64854_BURST_16; csr |= L64854_BURST_16;
else else
csr |= L64854_BURST_0; csr |= L64854_BURST_0;
csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; csr |= P_EN_DMA | P_INT_EN | P_EN_CNT;
#if 0 #if 0
/* This bit is read-only in PP csr register */ /* This bit is read-only in PP csr register. */
if (datain) if (datain != 0)
csr |= P_WRITE; csr |= P_WRITE;
else else
csr &= ~P_WRITE; csr &= ~P_WRITE;
@ -677,12 +703,15 @@ lsi64854_setup_pp(struct lsi64854_softc *sc, void **addr, size_t *len,
} }
/* /*
* Parallel port DMA interrupt. * Parallel port DMA interrupt
*/ */
static int static int
lsi64854_pp_intr(void *arg) lsi64854_pp_intr(void *arg)
{ {
struct lsi64854_softc *sc = arg; struct lsi64854_softc *sc = arg;
bus_dma_tag_t dmat;
bus_dmamap_t dmam;
size_t dmasize;
int ret, trans, resid = 0; int ret, trans, resid = 0;
uint32_t csr; uint32_t csr;
@ -691,13 +720,13 @@ lsi64854_pp_intr(void *arg)
DPRINTF(LDB_PP, ("%s: addr 0x%x, csr %b\n", __func__, DPRINTF(LDB_PP, ("%s: addr 0x%x, csr %b\n", __func__,
bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, PDMACSR_BITS)); bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, PDMACSR_BITS));
if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { if ((csr & (P_ERR_PEND | P_SLAVE_ERR)) != 0) {
resid = bus_read_4(sc->sc_res, L64854_REG_CNT); resid = bus_read_4(sc->sc_res, L64854_REG_CNT);
device_printf(sc->sc_dev, "error: resid %d csr=%b\n", resid, device_printf(sc->sc_dev, "error: resid %d csr=%b\n", resid,
csr, PDMACSR_BITS); csr, PDMACSR_BITS);
csr &= ~P_EN_DMA; /* Stop DMA */ csr &= ~P_EN_DMA; /* Stop DMA. */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= P_INVALIDATE|P_SLAVE_ERR; csr |= P_INVALIDATE | P_SLAVE_ERR;
L64854_SCSR(sc, csr); L64854_SCSR(sc, csr);
return (-1); return (-1);
} }
@ -714,17 +743,19 @@ lsi64854_pp_intr(void *arg)
L64854_SCSR(sc, csr); L64854_SCSR(sc, csr);
sc->sc_active = 0; sc->sc_active = 0;
trans = sc->sc_dmasize - resid; dmasize = sc->sc_dmasize;
trans = dmasize - resid;
if (trans < 0) /* transferred < 0? */ if (trans < 0) /* transferred < 0? */
trans = sc->sc_dmasize; trans = dmasize;
*sc->sc_dmalen -= trans; *sc->sc_dmalen -= trans;
*sc->sc_dmaaddr = (char *)*sc->sc_dmaaddr + trans; *sc->sc_dmaaddr = (char *)*sc->sc_dmaaddr + trans;
if (sc->sc_dmasize != 0) { if (dmasize != 0) {
bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, dmat = sc->sc_buffer_dmat;
(csr & D_WRITE) != 0 ? BUS_DMASYNC_POSTREAD : dmam = sc->sc_dmamap;
BUS_DMASYNC_POSTWRITE); bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(dmat, dmam);
} }
return (ret != 0); return (ret != 0);

View File

@ -49,6 +49,7 @@ struct lsi64854_softc {
bus_dma_tag_t sc_parent_dmat; bus_dma_tag_t sc_parent_dmat;
bus_dma_tag_t sc_buffer_dmat; bus_dma_tag_t sc_buffer_dmat;
bus_size_t sc_maxdmasize;
int sc_datain; int sc_datain;
size_t sc_dmasize; size_t sc_dmasize;
void **sc_dmaaddr; void **sc_dmaaddr;

View File

@ -1519,6 +1519,15 @@ ufs_rename(ap)
cache_purge(fdvp); cache_purge(fdvp);
} }
error = ufs_dirremove(fdvp, fip, fcnp->cn_flags, 0); error = ufs_dirremove(fdvp, fip, fcnp->cn_flags, 0);
/*
* The kern_renameat() looks up the fvp using the DELETE flag, which
* causes the removal of the name cache entry for fvp.
* As the relookup of the fvp is done in two steps:
* ufs_lookup_ino() and then VFS_VGET(), another thread might do a
* normal lookup of the from name just before the VFS_VGET() call,
* causing the cache entry to be re-instantiated.
*/
cache_purge(fvp);
unlockout: unlockout:
vput(fdvp); vput(fdvp);

View File

@ -214,7 +214,7 @@
09/08 Richard ``the Lionheart'', king of England born in Oxford, 1157 09/08 Richard ``the Lionheart'', king of England born in Oxford, 1157
09/08 Peter Sellers born in Southsea, England, 1925 09/08 Peter Sellers born in Southsea, England, 1925
09/09 Chinese Communist Party Chairman Mao Tse-Tung dies at age 82, 1976 09/09 Chinese Communist Party Chairman Mao Tse-Tung dies at age 82, 1976
09/09 Dennis MacAlistair Ritchie, creater of C, born, 1941 09/09 Dennis MacAlistair Ritchie, creator of C, born, 1941
09/12 Jesse Owens born, 1913 09/12 Jesse Owens born, 1913
09/13 Walter Reed born, 1851 09/13 Walter Reed born, 1851
09/15 Agatha Christie born in Torquay, England, 1890 09/15 Agatha Christie born in Torquay, England, 1890