Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to
6.0.0 (branches/release_60 r323948). MFC after: 3 months X-MFC-With: r327952 PR: 224669
This commit is contained in:
Dimitry Andric
commit
842d113b5c
@ -79,25 +79,27 @@ struct Mapping {
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#define TSAN_MID_APP_RANGE 1
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#elif defined(__mips64)
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/*
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C/C++ on linux/mips64
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0100 0000 00 - 0200 0000 00: main binary
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0200 0000 00 - 1400 0000 00: -
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1400 0000 00 - 2400 0000 00: shadow
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2400 0000 00 - 3000 0000 00: -
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3000 0000 00 - 4000 0000 00: metainfo (memory blocks and sync objects)
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4000 0000 00 - 6000 0000 00: -
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6000 0000 00 - 6200 0000 00: traces
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6200 0000 00 - fe00 0000 00: -
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fe00 0000 00 - ff00 0000 00: heap
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ff00 0000 00 - ff80 0000 00: -
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ff80 0000 00 - ffff ffff ff: modules and main thread stack
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C/C++ on linux/mips64 (40-bit VMA)
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0000 0000 00 - 0100 0000 00: - (4 GB)
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0100 0000 00 - 0200 0000 00: main binary (4 GB)
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0200 0000 00 - 2000 0000 00: - (120 GB)
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2000 0000 00 - 4000 0000 00: shadow (128 GB)
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4000 0000 00 - 5000 0000 00: metainfo (memory blocks and sync objects) (64 GB)
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5000 0000 00 - aa00 0000 00: - (360 GB)
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aa00 0000 00 - ab00 0000 00: main binary (PIE) (4 GB)
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ab00 0000 00 - b000 0000 00: - (20 GB)
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b000 0000 00 - b200 0000 00: traces (8 GB)
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b200 0000 00 - fe00 0000 00: - (304 GB)
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fe00 0000 00 - ff00 0000 00: heap (4 GB)
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ff00 0000 00 - ff80 0000 00: - (2 GB)
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ff80 0000 00 - ffff ffff ff: modules and main thread stack (<2 GB)
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*/
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struct Mapping {
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static const uptr kMetaShadowBeg = 0x4000000000ull;
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static const uptr kMetaShadowEnd = 0x5000000000ull;
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static const uptr kTraceMemBeg = 0xb000000000ull;
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static const uptr kTraceMemEnd = 0xb200000000ull;
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static const uptr kShadowBeg = 0x2400000000ull;
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static const uptr kShadowBeg = 0x2000000000ull;
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static const uptr kShadowEnd = 0x4000000000ull;
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static const uptr kHeapMemBeg = 0xfe00000000ull;
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static const uptr kHeapMemEnd = 0xff00000000ull;
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@ -508,7 +508,8 @@ class Value;
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/// -> LHS = %a, RHS = i32 4, *CastOp = Instruction::SExt
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///
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SelectPatternResult matchSelectPattern(Value *V, Value *&LHS, Value *&RHS,
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Instruction::CastOps *CastOp = nullptr);
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Instruction::CastOps *CastOp = nullptr,
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unsigned Depth = 0);
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inline SelectPatternResult
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matchSelectPattern(const Value *V, const Value *&LHS, const Value *&RHS,
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Instruction::CastOps *CastOp = nullptr) {
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@ -4165,17 +4165,18 @@ static SelectPatternResult matchClamp(CmpInst::Predicate Pred,
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/// a < c ? min(a,b) : min(b,c) ==> min(min(a,b),min(b,c))
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static SelectPatternResult matchMinMaxOfMinMax(CmpInst::Predicate Pred,
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Value *CmpLHS, Value *CmpRHS,
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Value *TrueVal, Value *FalseVal) {
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Value *TVal, Value *FVal,
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unsigned Depth) {
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// TODO: Allow FP min/max with nnan/nsz.
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assert(CmpInst::isIntPredicate(Pred) && "Expected integer comparison");
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Value *A, *B;
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SelectPatternResult L = matchSelectPattern(TrueVal, A, B);
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SelectPatternResult L = matchSelectPattern(TVal, A, B, nullptr, Depth + 1);
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if (!SelectPatternResult::isMinOrMax(L.Flavor))
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return {SPF_UNKNOWN, SPNB_NA, false};
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Value *C, *D;
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SelectPatternResult R = matchSelectPattern(FalseVal, C, D);
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SelectPatternResult R = matchSelectPattern(FVal, C, D, nullptr, Depth + 1);
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if (L.Flavor != R.Flavor)
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return {SPF_UNKNOWN, SPNB_NA, false};
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@ -4240,7 +4241,8 @@ static SelectPatternResult matchMinMaxOfMinMax(CmpInst::Predicate Pred,
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static SelectPatternResult matchMinMax(CmpInst::Predicate Pred,
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Value *CmpLHS, Value *CmpRHS,
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Value *TrueVal, Value *FalseVal,
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Value *&LHS, Value *&RHS) {
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Value *&LHS, Value *&RHS,
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unsigned Depth) {
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// Assume success. If there's no match, callers should not use these anyway.
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LHS = TrueVal;
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RHS = FalseVal;
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@ -4249,7 +4251,7 @@ static SelectPatternResult matchMinMax(CmpInst::Predicate Pred,
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if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN)
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return SPR;
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SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal);
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SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, Depth);
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if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN)
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return SPR;
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@ -4313,7 +4315,8 @@ static SelectPatternResult matchSelectPattern(CmpInst::Predicate Pred,
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FastMathFlags FMF,
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Value *CmpLHS, Value *CmpRHS,
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Value *TrueVal, Value *FalseVal,
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Value *&LHS, Value *&RHS) {
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Value *&LHS, Value *&RHS,
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unsigned Depth) {
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LHS = CmpLHS;
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RHS = CmpRHS;
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@ -4429,7 +4432,7 @@ static SelectPatternResult matchSelectPattern(CmpInst::Predicate Pred,
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}
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if (CmpInst::isIntPredicate(Pred))
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return matchMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, LHS, RHS);
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return matchMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, LHS, RHS, Depth);
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// According to (IEEE 754-2008 5.3.1), minNum(0.0, -0.0) and similar
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// may return either -0.0 or 0.0, so fcmp/select pair has stricter
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@ -4550,7 +4553,11 @@ static Value *lookThroughCast(CmpInst *CmpI, Value *V1, Value *V2,
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}
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SelectPatternResult llvm::matchSelectPattern(Value *V, Value *&LHS, Value *&RHS,
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Instruction::CastOps *CastOp) {
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Instruction::CastOps *CastOp,
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unsigned Depth) {
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if (Depth >= MaxDepth)
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return {SPF_UNKNOWN, SPNB_NA, false};
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SelectInst *SI = dyn_cast<SelectInst>(V);
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if (!SI) return {SPF_UNKNOWN, SPNB_NA, false};
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@ -4579,7 +4586,7 @@ SelectPatternResult llvm::matchSelectPattern(Value *V, Value *&LHS, Value *&RHS,
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FMF.setNoSignedZeros();
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return ::matchSelectPattern(Pred, FMF, CmpLHS, CmpRHS,
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cast<CastInst>(TrueVal)->getOperand(0), C,
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LHS, RHS);
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LHS, RHS, Depth);
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}
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if (Value *C = lookThroughCast(CmpI, FalseVal, TrueVal, CastOp)) {
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// If this is a potential fmin/fmax with a cast to integer, then ignore
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@ -4588,11 +4595,11 @@ SelectPatternResult llvm::matchSelectPattern(Value *V, Value *&LHS, Value *&RHS,
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FMF.setNoSignedZeros();
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return ::matchSelectPattern(Pred, FMF, CmpLHS, CmpRHS,
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C, cast<CastInst>(FalseVal)->getOperand(0),
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LHS, RHS);
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LHS, RHS, Depth);
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}
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}
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return ::matchSelectPattern(Pred, FMF, CmpLHS, CmpRHS, TrueVal, FalseVal,
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LHS, RHS);
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LHS, RHS, Depth);
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}
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/// Return true if "icmp Pred LHS RHS" is always true.
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@ -812,6 +812,10 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
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auto TII = MF->getTarget().getIntrinsicInfo();
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const Function *F = CI.getCalledFunction();
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// FIXME: support Windows dllimport function calls.
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if (F && F->hasDLLImportStorageClass())
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return false;
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if (CI.isInlineAsm())
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return translateInlineAsm(CI, MIRBuilder);
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@ -661,7 +661,24 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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}
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case TargetOpcode::G_FCONSTANT: {
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
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const ConstantFP *CFP = MI.getOperand(1).getFPImm();
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APFloat Val = CFP->getValueAPF();
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LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
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auto LLT2Sem = [](LLT Ty) {
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switch (Ty.getSizeInBits()) {
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case 32:
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return &APFloat::IEEEsingle();
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break;
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case 64:
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return &APFloat::IEEEdouble();
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break;
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default:
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llvm_unreachable("Unhandled fp widen type");
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}
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};
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bool LosesInfo;
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Val.convert(*LLT2Sem(WideTy), APFloat::rmTowardZero, &LosesInfo);
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MIRBuilder.buildFConstant(DstExt, *ConstantFP::get(Ctx, Val));
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MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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@ -193,9 +193,10 @@ namespace {
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void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
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void usePhysReg(MachineOperand &MO);
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void definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, RegState NewState);
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void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg,
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RegState NewState);
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unsigned calcSpillCost(MCPhysReg PhysReg) const;
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void assignVirtToPhysReg(LiveReg&, MCPhysReg PhysReg);
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void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg);
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LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
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return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
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@ -434,8 +435,8 @@ void RegAllocFast::usePhysReg(MachineOperand &MO) {
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/// Mark PhysReg as reserved or free after spilling any virtregs. This is very
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/// similar to defineVirtReg except the physreg is reserved instead of
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/// allocated.
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void RegAllocFast::definePhysReg(MachineInstr &MI, MCPhysReg PhysReg,
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RegState NewState) {
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void RegAllocFast::definePhysReg(MachineBasicBlock::iterator MI,
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MCPhysReg PhysReg, RegState NewState) {
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markRegUsedInInstr(PhysReg);
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switch (unsigned VirtReg = PhysRegState[PhysReg]) {
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case regDisabled:
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@ -857,7 +858,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
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// Add live-in registers as live.
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for (const MachineBasicBlock::RegisterMaskPair LI : MBB.liveins())
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if (MRI->isAllocatable(LI.PhysReg))
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definePhysReg(*MII, LI.PhysReg, regReserved);
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definePhysReg(MII, LI.PhysReg, regReserved);
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VirtDead.clear();
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Coalesced.clear();
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@ -1380,8 +1380,10 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
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FastISelFailed = false;
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// Initialize the Fast-ISel state, if needed.
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FastISel *FastIS = nullptr;
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if (TM.Options.EnableFastISel)
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if (TM.Options.EnableFastISel) {
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DEBUG(dbgs() << "Enabling fast-isel\n");
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FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
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}
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setupSwiftErrorVals(Fn, TLI, FuncInfo);
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@ -717,6 +717,8 @@ bool TargetPassConfig::addCoreISelPasses() {
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if (EnableGlobalISel == cl::BOU_TRUE ||
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(EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled() &&
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EnableFastISelOption != cl::BOU_TRUE)) {
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TM->setFastISel(false);
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if (addIRTranslator())
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return true;
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@ -476,26 +476,27 @@ unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
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// ADRP + LDRX
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
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ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
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.addGlobalAddress(GV, 0, AArch64II::MO_PAGE | OpFlags);
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ResultReg = createResultReg(&AArch64::GPR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
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ResultReg)
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.addReg(ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
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AArch64II::MO_NC);
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.addReg(ADRPReg)
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.addGlobalAddress(GV, 0,
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AArch64II::MO_PAGEOFF | AArch64II::MO_NC | OpFlags);
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} else {
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// ADRP + ADDX
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
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ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
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.addGlobalAddress(GV, 0, AArch64II::MO_PAGE | OpFlags);
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ResultReg = createResultReg(&AArch64::GPR64spRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
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ResultReg)
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.addReg(ADRPReg)
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.addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
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.addImm(0);
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.addReg(ADRPReg)
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.addGlobalAddress(GV, 0,
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AArch64II::MO_PAGEOFF | AArch64II::MO_NC | OpFlags)
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.addImm(0);
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}
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return ResultReg;
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}
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@ -929,6 +929,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return false;
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}
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// FIXME: PR36018: Volatile loads in some cases are incorrectly selected by
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// folding with an extend. Until we have a G_SEXTLOAD solution bail out if
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// we hit one.
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if (Opcode == TargetOpcode::G_LOAD && MemOp.isVolatile())
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return false;
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const unsigned PtrReg = I.getOperand(1).getReg();
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#ifndef NDEBUG
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const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
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@ -189,15 +189,18 @@ AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
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if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
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return AArch64II::MO_GOT;
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unsigned Flags = GV->hasDLLImportStorageClass() ? AArch64II::MO_DLLIMPORT
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: AArch64II::MO_NO_FLAG;
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if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
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return AArch64II::MO_GOT;
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return AArch64II::MO_GOT | Flags;
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// The small code model's direct accesses use ADRP, which cannot
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// necessarily produce the value 0 (if the code is above 4GB).
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if (useSmallAddressing() && GV->hasExternalWeakLinkage())
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return AArch64II::MO_GOT;
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return AArch64II::MO_GOT | Flags;
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return AArch64II::MO_NO_FLAG;
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return Flags;
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}
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unsigned char AArch64Subtarget::classifyGlobalFunctionReference(
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@ -210,65 +210,73 @@ void SIInsertSkips::kill(MachineInstr &MI) {
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switch (MI.getOperand(2).getImm()) {
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case ISD::SETOEQ:
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case ISD::SETEQ:
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Opcode = AMDGPU::V_CMPX_EQ_F32_e32;
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Opcode = AMDGPU::V_CMPX_EQ_F32_e64;
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break;
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case ISD::SETOGT:
|
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case ISD::SETGT:
|
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Opcode = AMDGPU::V_CMPX_LT_F32_e32;
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Opcode = AMDGPU::V_CMPX_LT_F32_e64;
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break;
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case ISD::SETOGE:
|
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case ISD::SETGE:
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Opcode = AMDGPU::V_CMPX_LE_F32_e32;
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Opcode = AMDGPU::V_CMPX_LE_F32_e64;
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break;
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case ISD::SETOLT:
|
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case ISD::SETLT:
|
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Opcode = AMDGPU::V_CMPX_GT_F32_e32;
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Opcode = AMDGPU::V_CMPX_GT_F32_e64;
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break;
|
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case ISD::SETOLE:
|
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case ISD::SETLE:
|
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Opcode = AMDGPU::V_CMPX_GE_F32_e32;
|
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Opcode = AMDGPU::V_CMPX_GE_F32_e64;
|
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break;
|
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case ISD::SETONE:
|
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case ISD::SETNE:
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Opcode = AMDGPU::V_CMPX_LG_F32_e32;
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Opcode = AMDGPU::V_CMPX_LG_F32_e64;
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break;
|
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case ISD::SETO:
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Opcode = AMDGPU::V_CMPX_O_F32_e32;
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Opcode = AMDGPU::V_CMPX_O_F32_e64;
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break;
|
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case ISD::SETUO:
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Opcode = AMDGPU::V_CMPX_U_F32_e32;
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Opcode = AMDGPU::V_CMPX_U_F32_e64;
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break;
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case ISD::SETUEQ:
|
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Opcode = AMDGPU::V_CMPX_NLG_F32_e32;
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Opcode = AMDGPU::V_CMPX_NLG_F32_e64;
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break;
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case ISD::SETUGT:
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Opcode = AMDGPU::V_CMPX_NGE_F32_e32;
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Opcode = AMDGPU::V_CMPX_NGE_F32_e64;
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break;
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case ISD::SETUGE:
|
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Opcode = AMDGPU::V_CMPX_NGT_F32_e32;
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Opcode = AMDGPU::V_CMPX_NGT_F32_e64;
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break;
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case ISD::SETULT:
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Opcode = AMDGPU::V_CMPX_NLE_F32_e32;
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Opcode = AMDGPU::V_CMPX_NLE_F32_e64;
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break;
|
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case ISD::SETULE:
|
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Opcode = AMDGPU::V_CMPX_NLT_F32_e32;
|
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Opcode = AMDGPU::V_CMPX_NLT_F32_e64;
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break;
|
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case ISD::SETUNE:
|
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Opcode = AMDGPU::V_CMPX_NEQ_F32_e32;
|
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Opcode = AMDGPU::V_CMPX_NEQ_F32_e64;
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break;
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default:
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llvm_unreachable("invalid ISD:SET cond code");
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}
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|
||||
// TODO: Allow this:
|
||||
if (!MI.getOperand(0).isReg() ||
|
||||
!TRI->isVGPR(MBB.getParent()->getRegInfo(),
|
||||
MI.getOperand(0).getReg()))
|
||||
llvm_unreachable("SI_KILL operand should be a VGPR");
|
||||
assert(MI.getOperand(0).isReg());
|
||||
|
||||
BuildMI(MBB, &MI, DL, TII->get(Opcode))
|
||||
.add(MI.getOperand(1))
|
||||
.add(MI.getOperand(0));
|
||||
if (TRI->isVGPR(MBB.getParent()->getRegInfo(),
|
||||
MI.getOperand(0).getReg())) {
|
||||
Opcode = AMDGPU::getVOPe32(Opcode);
|
||||
BuildMI(MBB, &MI, DL, TII->get(Opcode))
|
||||
.add(MI.getOperand(1))
|
||||
.add(MI.getOperand(0));
|
||||
} else {
|
||||
BuildMI(MBB, &MI, DL, TII->get(Opcode))
|
||||
.addReg(AMDGPU::VCC, RegState::Define)
|
||||
.addImm(0) // src0 modifiers
|
||||
.add(MI.getOperand(1))
|
||||
.addImm(0) // src1 modifiers
|
||||
.add(MI.getOperand(0))
|
||||
.addImm(0); // omod
|
||||
}
|
||||
break;
|
||||
}
|
||||
case AMDGPU::SI_KILL_I1_TERMINATOR: {
|
||||
|
||||
@ -39,11 +39,11 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
|
||||
const MCSubtargetInfo &STI) {
|
||||
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
|
||||
uint64_t TSFlags = Desc.TSFlags;
|
||||
unsigned Flags = MI->getFlags();
|
||||
|
||||
if (TSFlags & X86II::LOCK)
|
||||
if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK))
|
||||
OS << "\tlock\t";
|
||||
|
||||
unsigned Flags = MI->getFlags();
|
||||
if (Flags & X86::IP_HAS_REPEAT_NE)
|
||||
OS << "\trepne\t";
|
||||
else if (Flags & X86::IP_HAS_REPEAT)
|
||||
|
||||
@ -31776,9 +31776,10 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
|
||||
// Check all uses of the condition operand to check whether it will be
|
||||
// consumed by non-BLEND instructions. Those may require that all bits
|
||||
// are set properly.
|
||||
for (SDNode *U : Cond->uses()) {
|
||||
for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end();
|
||||
UI != UE; ++UI) {
|
||||
// TODO: Add other opcodes eventually lowered into BLEND.
|
||||
if (U->getOpcode() != ISD::VSELECT)
|
||||
if (UI->getOpcode() != ISD::VSELECT || UI.getOperandNo() != 0)
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
|
||||
@ -142,10 +142,11 @@ recordConditions(const CallSite &CS, BasicBlock *Pred,
|
||||
recordCondition(CS, Pred, CS.getInstruction()->getParent(), Conditions);
|
||||
BasicBlock *From = Pred;
|
||||
BasicBlock *To = Pred;
|
||||
SmallPtrSet<BasicBlock *, 4> Visited = {From};
|
||||
SmallPtrSet<BasicBlock *, 4> Visited;
|
||||
while (!Visited.count(From->getSinglePredecessor()) &&
|
||||
(From = From->getSinglePredecessor())) {
|
||||
recordCondition(CS, From, To, Conditions);
|
||||
Visited.insert(From);
|
||||
To = From;
|
||||
}
|
||||
}
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#include "llvm/ADT/SmallPtrSet.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
#include "llvm/Analysis/DivergenceAnalysis.h"
|
||||
#include "llvm/Analysis/LoopInfo.h"
|
||||
#include "llvm/Analysis/RegionInfo.h"
|
||||
#include "llvm/Analysis/RegionIterator.h"
|
||||
#include "llvm/Analysis/RegionPass.h"
|
||||
@ -176,8 +177,9 @@ class StructurizeCFG : public RegionPass {
|
||||
Region *ParentRegion;
|
||||
|
||||
DominatorTree *DT;
|
||||
LoopInfo *LI;
|
||||
|
||||
std::deque<RegionNode *> Order;
|
||||
SmallVector<RegionNode *, 8> Order;
|
||||
BBSet Visited;
|
||||
|
||||
BBPhiMap DeletedPhis;
|
||||
@ -202,7 +204,7 @@ class StructurizeCFG : public RegionPass {
|
||||
|
||||
void gatherPredicates(RegionNode *N);
|
||||
|
||||
void analyzeNode(RegionNode *N);
|
||||
void collectInfos();
|
||||
|
||||
void insertConditions(bool Loops);
|
||||
|
||||
@ -256,6 +258,7 @@ class StructurizeCFG : public RegionPass {
|
||||
AU.addRequired<DivergenceAnalysis>();
|
||||
AU.addRequiredID(LowerSwitchID);
|
||||
AU.addRequired<DominatorTreeWrapperPass>();
|
||||
AU.addRequired<LoopInfoWrapperPass>();
|
||||
|
||||
AU.addPreserved<DominatorTreeWrapperPass>();
|
||||
RegionPass::getAnalysisUsage(AU);
|
||||
@ -289,17 +292,55 @@ bool StructurizeCFG::doInitialization(Region *R, RGPassManager &RGM) {
|
||||
|
||||
/// \brief Build up the general order of nodes
|
||||
void StructurizeCFG::orderNodes() {
|
||||
assert(Visited.empty());
|
||||
assert(Predicates.empty());
|
||||
assert(Loops.empty());
|
||||
assert(LoopPreds.empty());
|
||||
ReversePostOrderTraversal<Region*> RPOT(ParentRegion);
|
||||
SmallDenseMap<Loop*, unsigned, 8> LoopBlocks;
|
||||
|
||||
// This must be RPO order for the back edge detection to work
|
||||
for (RegionNode *RN : ReversePostOrderTraversal<Region*>(ParentRegion)) {
|
||||
// FIXME: Is there a better order to use for structurization?
|
||||
Order.push_back(RN);
|
||||
analyzeNode(RN);
|
||||
// The reverse post-order traversal of the list gives us an ordering close
|
||||
// to what we want. The only problem with it is that sometimes backedges
|
||||
// for outer loops will be visited before backedges for inner loops.
|
||||
for (RegionNode *RN : RPOT) {
|
||||
BasicBlock *BB = RN->getEntry();
|
||||
Loop *Loop = LI->getLoopFor(BB);
|
||||
++LoopBlocks[Loop];
|
||||
}
|
||||
|
||||
unsigned CurrentLoopDepth = 0;
|
||||
Loop *CurrentLoop = nullptr;
|
||||
for (auto I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
|
||||
BasicBlock *BB = (*I)->getEntry();
|
||||
unsigned LoopDepth = LI->getLoopDepth(BB);
|
||||
|
||||
if (is_contained(Order, *I))
|
||||
continue;
|
||||
|
||||
if (LoopDepth < CurrentLoopDepth) {
|
||||
// Make sure we have visited all blocks in this loop before moving back to
|
||||
// the outer loop.
|
||||
|
||||
auto LoopI = I;
|
||||
while (unsigned &BlockCount = LoopBlocks[CurrentLoop]) {
|
||||
LoopI++;
|
||||
BasicBlock *LoopBB = (*LoopI)->getEntry();
|
||||
if (LI->getLoopFor(LoopBB) == CurrentLoop) {
|
||||
--BlockCount;
|
||||
Order.push_back(*LoopI);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
CurrentLoop = LI->getLoopFor(BB);
|
||||
if (CurrentLoop)
|
||||
LoopBlocks[CurrentLoop]--;
|
||||
|
||||
CurrentLoopDepth = LoopDepth;
|
||||
Order.push_back(*I);
|
||||
}
|
||||
|
||||
// This pass originally used a post-order traversal and then operated on
|
||||
// the list in reverse. Now that we are using a reverse post-order traversal
|
||||
// rather than re-working the whole pass to operate on the list in order,
|
||||
// we just reverse the list and continue to operate on it in reverse.
|
||||
std::reverse(Order.begin(), Order.end());
|
||||
}
|
||||
|
||||
/// \brief Determine the end of the loops
|
||||
@ -425,19 +466,32 @@ void StructurizeCFG::gatherPredicates(RegionNode *N) {
|
||||
}
|
||||
|
||||
/// \brief Collect various loop and predicate infos
|
||||
void StructurizeCFG::analyzeNode(RegionNode *RN) {
|
||||
DEBUG(dbgs() << "Visiting: "
|
||||
<< (RN->isSubRegion() ? "SubRegion with entry: " : "")
|
||||
<< RN->getEntry()->getName() << '\n');
|
||||
void StructurizeCFG::collectInfos() {
|
||||
// Reset predicate
|
||||
Predicates.clear();
|
||||
|
||||
// Analyze all the conditions leading to a node
|
||||
gatherPredicates(RN);
|
||||
// and loop infos
|
||||
Loops.clear();
|
||||
LoopPreds.clear();
|
||||
|
||||
// Remember that we've seen this node
|
||||
Visited.insert(RN->getEntry());
|
||||
// Reset the visited nodes
|
||||
Visited.clear();
|
||||
|
||||
// Find the last back edges
|
||||
analyzeLoops(RN);
|
||||
for (RegionNode *RN : reverse(Order)) {
|
||||
DEBUG(dbgs() << "Visiting: "
|
||||
<< (RN->isSubRegion() ? "SubRegion with entry: " : "")
|
||||
<< RN->getEntry()->getName() << " Loop Depth: "
|
||||
<< LI->getLoopDepth(RN->getEntry()) << "\n");
|
||||
|
||||
// Analyze all the conditions leading to a node
|
||||
gatherPredicates(RN);
|
||||
|
||||
// Remember that we've seen this node
|
||||
Visited.insert(RN->getEntry());
|
||||
|
||||
// Find the last back edges
|
||||
analyzeLoops(RN);
|
||||
}
|
||||
}
|
||||
|
||||
/// \brief Insert the missing branch conditions
|
||||
@ -610,7 +664,7 @@ void StructurizeCFG::changeExit(RegionNode *Node, BasicBlock *NewExit,
|
||||
BasicBlock *StructurizeCFG::getNextFlow(BasicBlock *Dominator) {
|
||||
LLVMContext &Context = Func->getContext();
|
||||
BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() :
|
||||
Order.front()->getEntry();
|
||||
Order.back()->getEntry();
|
||||
BasicBlock *Flow = BasicBlock::Create(Context, FlowBlockName,
|
||||
Func, Insert);
|
||||
DT->addNewBlock(Flow, Dominator);
|
||||
@ -690,8 +744,7 @@ bool StructurizeCFG::isPredictableTrue(RegionNode *Node) {
|
||||
/// Take one node from the order vector and wire it up
|
||||
void StructurizeCFG::wireFlow(bool ExitUseAllowed,
|
||||
BasicBlock *LoopEnd) {
|
||||
RegionNode *Node = Order.front();
|
||||
Order.pop_front();
|
||||
RegionNode *Node = Order.pop_back_val();
|
||||
Visited.insert(Node->getEntry());
|
||||
|
||||
if (isPredictableTrue(Node)) {
|
||||
@ -715,7 +768,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed,
|
||||
|
||||
PrevNode = Node;
|
||||
while (!Order.empty() && !Visited.count(LoopEnd) &&
|
||||
dominatesPredicates(Entry, Order.front())) {
|
||||
dominatesPredicates(Entry, Order.back())) {
|
||||
handleLoops(false, LoopEnd);
|
||||
}
|
||||
|
||||
@ -726,7 +779,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed,
|
||||
|
||||
void StructurizeCFG::handleLoops(bool ExitUseAllowed,
|
||||
BasicBlock *LoopEnd) {
|
||||
RegionNode *Node = Order.front();
|
||||
RegionNode *Node = Order.back();
|
||||
BasicBlock *LoopStart = Node->getEntry();
|
||||
|
||||
if (!Loops.count(LoopStart)) {
|
||||
@ -871,9 +924,10 @@ bool StructurizeCFG::runOnRegion(Region *R, RGPassManager &RGM) {
|
||||
ParentRegion = R;
|
||||
|
||||
DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
|
||||
LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
|
||||
|
||||
orderNodes();
|
||||
|
||||
collectInfos();
|
||||
createFlow();
|
||||
insertConditions(false);
|
||||
insertConditions(true);
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
#include "llvm/IR/CallSite.h"
|
||||
#include "llvm/IR/Constant.h"
|
||||
#include "llvm/IR/Constants.h"
|
||||
#include "llvm/IR/DebugInfoMetadata.h"
|
||||
#include "llvm/IR/DerivedTypes.h"
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/GlobalAlias.h"
|
||||
@ -536,13 +537,23 @@ Optional<Metadata *> MDNodeMapper::tryToMapOperand(const Metadata *Op) {
|
||||
return None;
|
||||
}
|
||||
|
||||
static Metadata *cloneOrBuildODR(const MDNode &N) {
|
||||
auto *CT = dyn_cast<DICompositeType>(&N);
|
||||
// If ODR type uniquing is enabled, we would have uniqued composite types
|
||||
// with identifiers during bitcode reading, so we can just use CT.
|
||||
if (CT && CT->getContext().isODRUniquingDebugTypes() &&
|
||||
CT->getIdentifier() != "")
|
||||
return const_cast<DICompositeType *>(CT);
|
||||
return MDNode::replaceWithDistinct(N.clone());
|
||||
}
|
||||
|
||||
MDNode *MDNodeMapper::mapDistinctNode(const MDNode &N) {
|
||||
assert(N.isDistinct() && "Expected a distinct node");
|
||||
assert(!M.getVM().getMappedMD(&N) && "Expected an unmapped node");
|
||||
DistinctWorklist.push_back(cast<MDNode>(
|
||||
(M.Flags & RF_MoveDistinctMDs)
|
||||
? M.mapToSelf(&N)
|
||||
: M.mapToMetadata(&N, MDNode::replaceWithDistinct(N.clone()))));
|
||||
DistinctWorklist.push_back(
|
||||
cast<MDNode>((M.Flags & RF_MoveDistinctMDs)
|
||||
? M.mapToSelf(&N)
|
||||
: M.mapToMetadata(&N, cloneOrBuildODR(N))));
|
||||
return DistinctWorklist.back();
|
||||
}
|
||||
|
||||
|
||||
@ -354,4 +354,12 @@ def warn_drv_fine_grained_bitfield_accesses_ignored : Warning<
|
||||
def note_drv_verify_prefix_spelling : Note<
|
||||
"-verify prefixes must start with a letter and contain only alphanumeric"
|
||||
" characters, hyphens, and underscores">;
|
||||
|
||||
def warn_drv_experimental_isel_incomplete : Warning<
|
||||
"-fexperimental-isel support for the '%0' architecture is incomplete">,
|
||||
InGroup<ExperimentalISel>;
|
||||
|
||||
def warn_drv_experimental_isel_incomplete_opt : Warning<
|
||||
"-fexperimental-isel support is incomplete for this architecture at the current optimization level">,
|
||||
InGroup<ExperimentalISel>;
|
||||
}
|
||||
|
||||
@ -985,3 +985,6 @@ def UnknownArgument : DiagGroup<"unknown-argument">;
|
||||
// A warning group for warnings about code that clang accepts when
|
||||
// compiling OpenCL C/C++ but which is not compatible with the SPIR spec.
|
||||
def SpirCompat : DiagGroup<"spir-compat">;
|
||||
|
||||
// Warning for the experimental-isel options.
|
||||
def ExperimentalISel : DiagGroup<"experimental-isel">;
|
||||
|
||||
@ -1031,6 +1031,8 @@ def finline_functions : Flag<["-"], "finline-functions">, Group<f_clang_Group>,
|
||||
def finline_hint_functions: Flag<["-"], "finline-hint-functions">, Group<f_clang_Group>, Flags<[CC1Option]>,
|
||||
HelpText<"Inline functions which are (explicitly or implicitly) marked inline">;
|
||||
def finline : Flag<["-"], "finline">, Group<clang_ignored_f_Group>;
|
||||
def fexperimental_isel : Flag<["-"], "fexperimental-isel">, Group<f_clang_Group>,
|
||||
HelpText<"Enables the experimental global instruction selector">;
|
||||
def fexperimental_new_pass_manager : Flag<["-"], "fexperimental-new-pass-manager">,
|
||||
Group<f_clang_Group>, Flags<[CC1Option]>,
|
||||
HelpText<"Enables an experimental new pass manager in LLVM.">;
|
||||
@ -1237,6 +1239,8 @@ def fno_exceptions : Flag<["-"], "fno-exceptions">, Group<f_Group>;
|
||||
def fno_gnu_keywords : Flag<["-"], "fno-gnu-keywords">, Group<f_Group>, Flags<[CC1Option]>;
|
||||
def fno_inline_functions : Flag<["-"], "fno-inline-functions">, Group<f_clang_Group>, Flags<[CC1Option]>;
|
||||
def fno_inline : Flag<["-"], "fno-inline">, Group<f_clang_Group>, Flags<[CC1Option]>;
|
||||
def fno_experimental_isel : Flag<["-"], "fno-experimental-isel">, Group<f_clang_Group>,
|
||||
HelpText<"Disables the experimental global instruction selector">;
|
||||
def fno_experimental_new_pass_manager : Flag<["-"], "fno-experimental-new-pass-manager">,
|
||||
Group<f_clang_Group>, Flags<[CC1Option]>,
|
||||
HelpText<"Disables an experimental new pass manager in LLVM.">;
|
||||
|
||||
@ -4639,6 +4639,37 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
|
||||
CmdArgs.push_back("-fwhole-program-vtables");
|
||||
}
|
||||
|
||||
if (Arg *A = Args.getLastArg(options::OPT_fexperimental_isel,
|
||||
options::OPT_fno_experimental_isel)) {
|
||||
CmdArgs.push_back("-mllvm");
|
||||
if (A->getOption().matches(options::OPT_fexperimental_isel)) {
|
||||
CmdArgs.push_back("-global-isel=1");
|
||||
|
||||
// GISel is on by default on AArch64 -O0, so don't bother adding
|
||||
// the fallback remarks for it. Other combinations will add a warning of
|
||||
// some kind.
|
||||
bool IsArchSupported = Triple.getArch() == llvm::Triple::aarch64;
|
||||
bool IsOptLevelSupported = false;
|
||||
|
||||
Arg *A = Args.getLastArg(options::OPT_O_Group);
|
||||
if (Triple.getArch() == llvm::Triple::aarch64) {
|
||||
if (!A || A->getOption().matches(options::OPT_O0))
|
||||
IsOptLevelSupported = true;
|
||||
}
|
||||
if (!IsArchSupported || !IsOptLevelSupported) {
|
||||
CmdArgs.push_back("-mllvm");
|
||||
CmdArgs.push_back("-global-isel-abort=2");
|
||||
|
||||
if (!IsArchSupported)
|
||||
D.Diag(diag::warn_drv_experimental_isel_incomplete) << Triple.getArchName();
|
||||
else
|
||||
D.Diag(diag::warn_drv_experimental_isel_incomplete_opt);
|
||||
}
|
||||
} else {
|
||||
CmdArgs.push_back("-global-isel=0");
|
||||
}
|
||||
}
|
||||
|
||||
// Finally add the compile command to the compilation.
|
||||
if (Args.hasArg(options::OPT__SLASH_fallback) &&
|
||||
Output.getType() == types::TY_Object &&
|
||||
|
||||
@ -46,7 +46,7 @@ static void handleHVXWarnings(const Driver &D, const ArgList &Args) {
|
||||
// Handle the unsupported values passed to mhvx-length.
|
||||
if (Arg *A = Args.getLastArg(options::OPT_mhexagon_hvx_length_EQ)) {
|
||||
StringRef Val = A->getValue();
|
||||
if (Val != "64B" && Val != "128B")
|
||||
if (!Val.equals_lower("64b") && !Val.equals_lower("128b"))
|
||||
D.Diag(diag::err_drv_unsupported_option_argument)
|
||||
<< A->getOption().getName() << Val;
|
||||
}
|
||||
|
||||
@ -47,6 +47,7 @@
|
||||
using namespace llvm;
|
||||
using namespace llvm::ELF;
|
||||
using namespace llvm::object;
|
||||
using namespace llvm::support;
|
||||
using namespace llvm::support::endian;
|
||||
|
||||
using namespace lld;
|
||||
@ -357,7 +358,7 @@ static uint64_t scanCortexA53Errata843419(InputSection *IS, uint64_t &Off,
|
||||
|
||||
uint64_t PatchOff = 0;
|
||||
const uint8_t *Buf = IS->Data.begin();
|
||||
const uint32_t *InstBuf = reinterpret_cast<const uint32_t *>(Buf + Off);
|
||||
const ulittle32_t *InstBuf = reinterpret_cast<const ulittle32_t *>(Buf + Off);
|
||||
uint32_t Instr1 = *InstBuf++;
|
||||
uint32_t Instr2 = *InstBuf++;
|
||||
uint32_t Instr3 = *InstBuf++;
|
||||
|
||||
@ -45,8 +45,9 @@ struct PhdrEntry {
|
||||
OutputSection *LastSec = nullptr;
|
||||
bool HasLMA = false;
|
||||
|
||||
// True if any of the sections in this program header as a LMA specified via
|
||||
// linker script: AT(addr).
|
||||
// True if one of the sections in this program header has a LMA specified via
|
||||
// linker script: AT(addr). We never allow 2 or more sections with LMA in the
|
||||
// same program header.
|
||||
bool ASectionHasLMA = false;
|
||||
|
||||
uint64_t LMAOffset = 0;
|
||||
|
||||
@ -8,4 +8,4 @@
|
||||
|
||||
#define CLANG_VENDOR "FreeBSD "
|
||||
|
||||
#define SVN_REVISION "323338"
|
||||
#define SVN_REVISION "323948"
|
||||
|
||||
@ -4,5 +4,5 @@
|
||||
#define LLD_VERSION_STRING "6.0.0"
|
||||
#define LLD_VERSION_MAJOR 6
|
||||
#define LLD_VERSION_MINOR 0
|
||||
#define LLD_REVISION_STRING "323338"
|
||||
#define LLD_REVISION_STRING "323948"
|
||||
#define LLD_REPOSITORY_STRING "FreeBSD"
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
/* $FreeBSD$ */
|
||||
#define LLVM_REVISION "svn-r323338"
|
||||
#define LLVM_REVISION "svn-r323948"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user