Replace sb_store64()/sb_load64() with mips3_sd()/mips3_ld() respectively.
Obtained from NetBSD. Suggested by: jmallett@
This commit is contained in:
neel
parent
2652efe7b0
commit
8457716f88
@ -283,6 +283,35 @@ breakpoint(void)
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__asm __volatile ("break");
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}
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#if defined(__GNUC__) && !defined(__mips_o32)
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static inline uint64_t
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mips3_ld(const volatile uint64_t *va)
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{
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uint64_t rv;
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#if defined(_LP64)
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rv = *va;
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#else
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__asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va));
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#endif
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return (rv);
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}
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static inline void
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mips3_sd(volatile uint64_t *va, uint64_t v)
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{
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#if defined(_LP64)
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*va = v;
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#else
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__asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va));
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#endif
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}
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#else
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uint64_t mips3_ld(volatile uint64_t *va);
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void mips3_sd(volatile uint64_t *, uint64_t);
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#endif /* __GNUC__ */
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#endif /* _KERNEL */
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#define readb(va) (*(volatile uint8_t *) (va))
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@ -50,6 +50,38 @@
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* $FreeBSD$
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*/
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/*
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* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jonathan R. Stone for
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* the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Contains code that is the first executed at boot time plus
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* assembly language support routines.
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@ -61,6 +93,7 @@
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/regnum.h>
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#include <machine/cpuregs.h>
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#include "assym.s"
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@ -1586,3 +1619,78 @@ LEAF(octeon_get_control)
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.set mips0
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END(octeon_get_control)
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#endif
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LEAF(mips3_ld)
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.set push
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.set noreorder
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.set mips64
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#if defined(__mips_o32)
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mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
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and t1, t0, ~(MIPS_SR_INT_IE)
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mtc0 t1, MIPS_COP_0_STATUS
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COP0_SYNC
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nop
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nop
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nop
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ld v0, 0(a0)
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#if _BYTE_ORDER == _BIG_ENDIAN
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dsll v1, v0, 32
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dsra v1, v1, 32 # low word in v1
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dsra v0, v0, 32 # high word in v0
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#else
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dsra v1, v0, 32 # high word in v1
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dsll v0, v0, 32
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dsra v0, v0, 32 # low word in v0
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#endif
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mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
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COP0_SYNC
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nop
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#else /* !__mips_o32 */
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ld v0, 0(a0)
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#endif /* !__mips_o32 */
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jr ra
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nop
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.set pop
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END(mips3_ld)
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LEAF(mips3_sd)
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.set push
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.set mips64
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.set noreorder
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#if defined(__mips_o32)
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mfc0 t0, MIPS_COP_0_STATUS # turn off interrupts
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and t1, t0, ~(MIPS_SR_INT_IE)
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mtc0 t1, MIPS_COP_0_STATUS
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COP0_SYNC
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nop
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nop
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nop
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# NOTE: a1 is padding!
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#if _BYTE_ORDER == _BIG_ENDIAN
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dsll a2, a2, 32 # high word in a2
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dsll a3, a3, 32 # low word in a3
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dsrl a3, a3, 32
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#else
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dsll a2, a2, 32 # low word in a2
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dsrl a2, a2, 32
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dsll a3, a3, 32 # high word in a3
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#endif
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or a1, a2, a3
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sd a1, 0(a0)
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mtc0 t0, MIPS_COP_0_STATUS # restore intr status.
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COP0_SYNC
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nop
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#else /* !__mips_o32 */
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sd a1, 0(a0)
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#endif /* !__mips_o32 */
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jr ra
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nop
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.set pop
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END(mips3_sd)
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@ -28,61 +28,11 @@
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#include <machine/asm.h>
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#include <machine/cpuregs.h>
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#include <machine/endian.h>
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/*
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* We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
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* processor. It has some registers that must be accessed using 64-bit load
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* and store instructions.
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*
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* So we have to resort to assembly because the compiler does not emit the
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* 'ld' and 'sd' instructions since it thinks that it is compiling for a
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* 32-bit mips processor.
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*/
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.set mips64
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.set noat
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.set noreorder
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/*
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* Parameters: uint32_t ptr
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* Return value: *(uint64_t *)ptr
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*/
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LEAF(sb_load64)
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ld v1, 0(a0) /* result = *(uint64_t *)ptr */
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move v0, v1
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#if _BYTE_ORDER == _BIG_ENDIAN
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dsll32 v1, v1, 0
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dsra32 v1, v1, 0 /* v1 = lower_uint32(result) */
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jr ra
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dsra32 v0, v0, 0 /* v0 = upper_uint32(result) */
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#else
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dsll32 v0, v0, 0
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dsra32 v0, v0, 0 /* v0 = lower_uint32(result) */
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jr ra
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dsra32 v1, v1, 0 /* v1 = upper_uint32(result) */
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#endif
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END(sb_load64)
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/*
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* Parameters: uint32_t ptr, uint64_t val
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* Return value: void
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*/
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LEAF(sb_store64)
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#if _BYTE_ORDER == _BIG_ENDIAN
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dsll32 a2, a2, 0 /* a2 = upper_uint32(val) */
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dsll32 a3, a3, 0 /* a3 = lower_uint32(val) */
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dsrl32 a3, a3, 0
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#else
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dsll32 a3, a3, 0 /* a3 = upper_uint32(val) */
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dsll32 a2, a2, 0 /* a2 = lower_uint32(val) */
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dsrl32 a2, a2, 0
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#endif
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or t0, a2, a3
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jr ra
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sd t0, 0(a0)
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END(sb_store64)
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#ifdef SMP
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/*
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* This function must be implemented in assembly because it is called early
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@ -38,8 +38,15 @@ __FBSDID("$FreeBSD$");
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#include "sb_scd.h"
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extern void sb_store64(uint32_t addr, uint64_t val);
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extern uint64_t sb_load64(uint32_t addr);
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/*
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* We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
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* processor. It has some registers that must be accessed using 64-bit load
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* and store instructions.
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*
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* We use the mips_ld() and mips_sd() functions to do this for us.
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*/
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#define sb_store64(addr, val) mips3_sd((uint64_t *)(addr), (val))
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#define sb_load64(addr) mips3_ld((uint64_t *)(addr))
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/*
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* System Control and Debug (SCD) unit on the Sibyte ZBbus.
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