d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add Intel Processor Trace registers for:

Browse Source 
- CPUID
- Table of Physical Addresses (ToPA).

Sponsored by:	DARPA, AFRL
This commit is contained in:
br 2017-11-17 17:54:10 +00:00
parent d9e9afeb56
commit 849e978e17
1 changed files with 52 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
sys/x86/include/specialreg.h
View File

@ -188,6 +188,35 @@
#define CPUTPM1_ARAT 0x00000004
#define CPUTPM2_EFFREQ 0x00000001
/* Intel Processor Trace CPUID. */
/* Leaf 0 ebx. */
#define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */
#define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */
#define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */
#define CPUPT_MTC (1 << 3) /* MTC Supported */
#define CPUPT_PRW (1 << 4) /* PTWRITE Supported */
#define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */
/* Leaf 0 ecx. */
#define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */
#define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */
#define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */
#define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */
#define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */
/* Leaf 1 eax. */
#define CPUPT_NADDR_S 0 /* Number of Address Ranges */
#define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S)
#define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */
#define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S)
/* Leaf 1 ebx. */
#define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */
#define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S)
#define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */
#define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S)
/*
* Important bits in the AMD extended cpuid flags
*/
@ -602,6 +631,29 @@
#define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */
#define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */
/* Intel Processor Trace Table of Physical Addresses (ToPA). */
#define TOPA_SIZE_S 6
#define TOPA_SIZE_M (0xf << TOPA_SIZE_S)
#define TOPA_SIZE_4K (0 << TOPA_SIZE_S)
#define TOPA_SIZE_8K (1 << TOPA_SIZE_S)
#define TOPA_SIZE_16K (2 << TOPA_SIZE_S)
#define TOPA_SIZE_32K (3 << TOPA_SIZE_S)
#define TOPA_SIZE_64K (4 << TOPA_SIZE_S)
#define TOPA_SIZE_128K (5 << TOPA_SIZE_S)
#define TOPA_SIZE_256K (6 << TOPA_SIZE_S)
#define TOPA_SIZE_512K (7 << TOPA_SIZE_S)
#define TOPA_SIZE_1M (8 << TOPA_SIZE_S)
#define TOPA_SIZE_2M (9 << TOPA_SIZE_S)
#define TOPA_SIZE_4M (10 << TOPA_SIZE_S)
#define TOPA_SIZE_8M (11 << TOPA_SIZE_S)
#define TOPA_SIZE_16M (12 << TOPA_SIZE_S)
#define TOPA_SIZE_32M (13 << TOPA_SIZE_S)
#define TOPA_SIZE_64M (14 << TOPA_SIZE_S)
#define TOPA_SIZE_128M (15 << TOPA_SIZE_S)
#define TOPA_STOP (1 << 4)
#define TOPA_INT (1 << 2)
#define TOPA_END (1 << 0)
/*
* Constants related to MSR's.
*/