Updates to match changes elsewhere in the PCI subsystem:
- Remove redundant header-type-specific support in the cardbus pcibus clone. The bridges don't need this anymore. - Use pcib_get_bus instead of the deprecated pci_get_secondarybus. - Implement read/write ivar support for the pccbb, and teach it how to report its secondary bus number. Save the subsidiary bus number as well, although we don't use it yet.
This commit is contained in:
Mike Smith
parent
8983cfbf27
commit
84c6b37d74
@ -96,8 +96,6 @@ static int cardbus_attach_card(device_t dev);
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static int cardbus_detach_card(device_t dev, int flags);
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static struct cardbus_devinfo *cardbus_read_device(device_t pcib,
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int b, int s, int f);
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static void *cardbus_readppb(device_t pcib, int b, int s, int f);
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static void *cardbus_readpcb(device_t pcib, int b, int s, int f);
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static void cardbus_hdrtypedata(device_t pcib, int b, int s, int f,
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pcicfgregs *cfg);
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static int cardbus_freecfg(struct cardbus_devinfo *dinfo);
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@ -194,7 +192,7 @@ cardbus_attach_card(device_t dev)
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POWER_ENABLE_SOCKET(bdev, dev);
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bus = pci_get_secondarybus(bdev);
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bus = pcib_get_bus(dev);
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if (bus == 0) {
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/*
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* XXX EVILE BAD XXX
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@ -389,80 +387,6 @@ cardbus_read_device(device_t pcib, int b, int s, int f)
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#undef REG
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}
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/* read config data specific to header type 1 device (PCI to PCI bridge) */
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static void *
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cardbus_readppb(device_t pcib, int b, int s, int f)
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{
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pcih1cfgregs *p;
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p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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if (p == NULL)
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return (NULL);
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p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
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p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
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p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
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p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
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PCIR_IOBASEH_1, 2),
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PCIB_READ_CONFIG(pcib, b, s, f,
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PCIR_IOBASEL_1, 1));
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p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
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PCIR_IOLIMITH_1, 2),
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PCIB_READ_CONFIG(pcib, b, s, f,
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PCIR_IOLIMITL_1, 1));
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p->membase = PCI_PPBMEMBASE (0,
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PCIB_READ_CONFIG(pcib, b, s, f,
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PCIR_MEMBASE_1, 2));
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p->memlimit = PCI_PPBMEMLIMIT (0,
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PCIB_READ_CONFIG(pcib, b, s, f,
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PCIR_MEMLIMIT_1, 2));
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p->pmembase = PCI_PPBMEMBASE (
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(pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
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PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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p->pmemlimit = PCI_PPBMEMLIMIT (
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(pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
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PCIR_PMLIMITH_1, 4),
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PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
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return (p);
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}
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/* read config data specific to header type 2 device (PCI to CardBus bridge) */
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static void *
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cardbus_readpcb(device_t pcib, int b, int s, int f)
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{
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pcih2cfgregs *p;
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p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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if (p == NULL)
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return (NULL);
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p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
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p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
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p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
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p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
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p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
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p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
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p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
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p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
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p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
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p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
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p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
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p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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return p;
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}
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/* extract header type specific config data */
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static void
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@ -478,18 +402,12 @@ cardbus_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
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case 1:
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cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
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cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
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cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
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cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
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cfg->nummaps = PCI_MAXMAPS_1;
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cfg->hdrspec = cardbus_readppb(pcib, b, s, f);
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break;
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case 2:
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cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
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cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
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cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
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cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
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cfg->nummaps = PCI_MAXMAPS_2;
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cfg->hdrspec = cardbus_readpcb(pcib, b, s, f);
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break;
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}
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#undef REG
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@ -518,8 +436,6 @@ cardbus_print_verbose(struct cardbus_devinfo *dinfo)
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printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
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cfg->baseclass, cfg->subclass, cfg->progif,
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cfg->hdrtype, cfg->mfdev);
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printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
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cfg->subordinatebus, cfg->secondarybus);
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#ifdef CARDBUS_DEBUG
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printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
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cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
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@ -922,12 +838,6 @@ cardbus_read_ivar(device_t dev, device_t child, int which, u_long *result)
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case PCI_IVAR_FUNCTION:
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*result = cfg->func;
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break;
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case PCI_IVAR_SECONDARYBUS:
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*result = cfg->secondarybus;
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break;
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case PCI_IVAR_SUBORDINATEBUS:
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*result = cfg->subordinatebus;
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break;
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default:
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return ENOENT;
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}
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@ -959,12 +869,6 @@ cardbus_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
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case PCI_IVAR_SLOT:
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case PCI_IVAR_FUNCTION:
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return EINVAL; /* disallow for now */
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case PCI_IVAR_SECONDARYBUS:
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cfg->secondarybus = value;
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break;
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case PCI_IVAR_SUBORDINATEBUS:
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cfg->subordinatebus = value;
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break;
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default:
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return ENOENT;
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}
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@ -392,6 +392,8 @@ pccbb_attach(device_t dev)
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sc->sc_flags = 0;
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sc->sc_cbdev = NULL;
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sc->sc_pccarddev = NULL;
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sc->sc_secbus = pci_read_config(dev, PCIR_SECBUS_2, 1);
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sc->sc_subbus = pci_read_config(dev, PCIR_SUBBUS_2, 1);
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sc->memalloc = 0;
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sc->ioalloc = 0;
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SLIST_INIT(&sc->rl);
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@ -1779,6 +1781,32 @@ pccbb_release_resource(device_t self, device_t child, int type, int rid,
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rid, r);
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}
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static int
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pccbb_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct pccbb_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = sc->sc_secbus;
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return(0);
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}
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return(ENOENT);
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}
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static int
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pccbb_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
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{
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struct pccbb_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->sc_secbus = value;
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break;
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}
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return(ENOENT);
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}
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/************************************************************************/
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/* PCI compat methods */
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/************************************************************************/
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@ -1820,6 +1848,8 @@ static device_method_t pccbb_methods[] = {
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/* bus methods */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, pccbb_read_ivar),
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DEVMETHOD(bus_write_ivar, pccbb_write_ivar),
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DEVMETHOD(bus_alloc_resource, pccbb_alloc_resource),
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DEVMETHOD(bus_release_resource, pccbb_release_resource),
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DEVMETHOD(bus_activate_resource, pccbb_activate_resource),
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@ -65,8 +65,10 @@ struct pccbb_softc {
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struct resource *sc_irq_res;
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void *sc_intrhand;
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struct pccbb_socketreg *sc_socketreg;
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u_int32_t sc_flags;
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u_int8_t sc_secbus;
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u_int8_t sc_subbus;
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struct mtx sc_mtx;
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u_int32_t sc_flags;
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#define PCCBB_PCIC_IO_RELOC 0x01
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#define PCCBB_PCIC_MEM_32 0x02
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#define PCCBB_CARDATTACHED 0x01000000
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