From 8582cd31010027b6a1b176450dc5becd259617d5 Mon Sep 17 00:00:00 2001
From: Brooks Davis <brooks@FreeBSD.org>
Date: Thu, 27 Feb 2020 20:08:46 +0000
Subject: [PATCH] Merge commit 7214f7a79 from llvm git (by Sam Elliott):

  [RISCV] Lower llvm.trap and llvm.debugtrap

  Summary:
  Until this commit, these have lowered to a call to abort().

  `llvm.trap()` now lowers to `unimp`, which should trap on all systems.

  `llvm.debugtrap()` now lowers to `ebreak`, which is exactly what this
  instruction is for.

  Reviewers: asb, luismarques

  Reviewed By: asb

  Tags: #llvm

  Differential Revision: https://reviews.llvm.org/D69390

This fixes miscompilation resulting in linking failures with
INVARIANTS disabled.

Reviewed by:	dim
Differential Revision:	https://reviews.freebsd.org/D23857
---
 .../llvm/lib/Target/RISCV/RISCVISelLowering.cpp        |  3 +++
 .../llvm/lib/Target/RISCV/RISCVInstrInfo.td            | 10 ++++++++++
 2 files changed, 13 insertions(+)

diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6ce317994d2a..1a370968cb28 100644
--- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -185,6 +185,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
                      Subtarget.is64Bit() ? Legal : Custom);
 
+  setOperationAction(ISD::TRAP, MVT::Other, Legal);
+  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
+
   if (Subtarget.hasStdExtA()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
     setMinCmpXchgSizeInBits(32);
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 69bde15f1218..b5577411cb58 100644
--- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1075,6 +1075,16 @@ let Predicates = [IsRV32], usesCustomInserter = 1, hasSideEffects = 0,
 mayLoad = 0, mayStore = 0, hasNoSchedulingInfo = 1 in
 def ReadCycleWide : Pseudo<(outs GPR:$lo, GPR:$hi), (ins), [], "", "">;
 
+/// traps
+
+// We lower `trap` to `unimp`, as this causes a hard exception on nearly all
+// systems.
+def : Pat<(trap), (UNIMP)>;
+
+// We lower `debugtrap` to `ebreak`, as this will get the attention of the
+// debugger if possible.
+def : Pat<(debugtrap), (EBREAK)>;
+
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//