Retire RL_FLAG_INVMAR bit to match its comment and reality.
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@ -657,7 +657,7 @@ re_set_rxmode(struct rl_softc *sc)
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* write the hash pattern in reverse order for those
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* devices.
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*/
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if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) {
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if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
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h = bswap32(hashes[0]);
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hashes[0] = bswap32(hashes[1]);
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hashes[1] = h;
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@ -1234,22 +1234,21 @@ re_attach(device_t dev)
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break;
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case RL_HWREV_8100E:
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case RL_HWREV_8101E:
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sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR |
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RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
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sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE |
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RL_FLAG_FASTETHER;
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break;
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case RL_HWREV_8102E:
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case RL_HWREV_8102EL:
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sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR |
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RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
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RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP;
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sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE |
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RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
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RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP;
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break;
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case RL_HWREV_8168_SPIN1:
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case RL_HWREV_8168_SPIN2:
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sc->rl_flags |= RL_FLAG_WOLRXENB;
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/* FALLTHROUGH */
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case RL_HWREV_8168_SPIN3:
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sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
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RL_FLAG_MACSTAT;
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sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
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break;
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case RL_HWREV_8168C_SPIN2:
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sc->rl_flags |= RL_FLAG_MACSLEEP;
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@ -1260,9 +1259,8 @@ re_attach(device_t dev)
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/* FALLTHROUGH */
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case RL_HWREV_8168CP:
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case RL_HWREV_8168D:
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sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
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RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
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RL_FLAG_CMDSTOP;
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sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
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RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP;
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/*
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* These controllers support jumbo frame but it seems
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* that enabling it requires touching additional magic
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@ -879,7 +879,6 @@ struct rl_softc {
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int rl_txstart;
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uint32_t rl_flags;
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#define RL_FLAG_MSI 0x0001
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#define RL_FLAG_INVMAR 0x0004
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#define RL_FLAG_PHYWAKE 0x0008
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#define RL_FLAG_NOJUMBO 0x0010
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#define RL_FLAG_PAR 0x0020
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