Set the cache line size for subordinate pci bridges as well as for their
child devices. This fixes dma timeouts for devices behind the bridge. Reported by: simokawa Tested by: simokawa
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@ -216,6 +216,8 @@ ofw_pci_init(device_t dev, phandle_t bushdl, u_int32_t ign,
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panic("ofw_pci_init: OF_getprop failed");
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slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
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func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
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PCIB_WRITE_CONFIG(dev, busno, slot, func, PCIR_CACHELNSZ,
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clnsz / 4, 1);
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if (strcmp(type, OFW_PCI_PCIBUS) == 0) {
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/*
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* This is a pci-pci bridge, initalize the bus number and
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@ -269,8 +271,6 @@ ofw_pci_init(device_t dev, phandle_t bushdl, u_int32_t ign,
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PCIB_WRITE_CONFIG(dev, busno, slot, func,
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PCIR_LATTIMER, imin(lat, 255), 1);
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}
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PCIB_WRITE_CONFIG(dev, busno, slot, func,
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PCIR_CACHELNSZ, clnsz / 4, 1);
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/* Initialize the intline registers. */
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if ((intr = ofw_pci_route_intr(node, ign)) != 255) {
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