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Reduce the diff to the arm_intrng project branch by having the read/write

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macros take the softc they are accessing.
This commit is contained in:
andrew 2014-12-21 16:21:56 +00:00
parent 1bbb36e3f1
commit 86c28c2515
1 changed files with 49 additions and 42 deletions
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91
sys/arm/arm/gic.c
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@ -118,14 +118,14 @@ static struct resource_spec arm_gic_spec[] = {
static struct arm_gic_softc *arm_gic_sc = NULL;
#define gic_c_read_4(reg) \
bus_space_read_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg)
#define gic_c_write_4(reg, val) \
bus_space_write_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg, val)
#define gic_d_read_4(reg) \
bus_space_read_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg)
#define gic_d_write_4(reg, val) \
bus_space_write_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg, val)
#define gic_c_read_4(_sc, _reg) \
bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg))
#define gic_c_write_4(_sc, _reg, _val) \
bus_space_write_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg), (_val))
#define gic_d_read_4(_sc, _reg) \
bus_space_read_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg))
#define gic_d_write_4(_sc, _reg, _val) \
bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
static int gic_config_irq(int irq, enum intr_trigger trig,
enum intr_polarity pol);
@ -158,35 +158,36 @@ arm_gic_probe(device_t dev)
void
gic_init_secondary(void)
{
struct arm_gic_softc *sc = arm_gic_sc;
int i, nirqs;
/* Get the number of interrupts */
nirqs = gic_d_read_4(GICD_TYPER);
nirqs = gic_d_read_4(sc, GICD_TYPER);
nirqs = 32 * ((nirqs & 0x1f) + 1);
for (i = 0; i < nirqs; i += 4)
gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0);
/* Set all the interrupts to be in Group 0 (secure) */
for (i = 0; i < nirqs; i += 32) {
gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
}
/* Enable CPU interface */
gic_c_write_4(GICC_CTLR, 1);
gic_c_write_4(sc, GICC_CTLR, 1);
/* Set priority mask register. */
gic_c_write_4(GICC_PMR, 0xff);
gic_c_write_4(sc, GICC_PMR, 0xff);
/* Enable interrupt distribution */
gic_d_write_4(GICD_CTLR, 0x01);
gic_d_write_4(sc, GICD_CTLR, 0x01);
/*
* Activate the timer interrupts: virtual, secure, and non-secure.
*/
gic_d_write_4(GICD_ISENABLER(27 >> 5), (1UL << (27 & 0x1F)));
gic_d_write_4(GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
gic_d_write_4(GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
gic_d_write_4(sc, GICD_ISENABLER(27 >> 5), (1UL << (27 & 0x1F)));
gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
}
int
@ -266,49 +267,50 @@ arm_gic_attach(device_t dev)
arm_gic_sc = sc;
/* Disable interrupt forwarding to the CPU interface */
gic_d_write_4(GICD_CTLR, 0x00);
gic_d_write_4(sc, GICD_CTLR, 0x00);
/* Get the number of interrupts */
sc->nirqs = gic_d_read_4(GICD_TYPER);
sc->nirqs = gic_d_read_4(sc, GICD_TYPER);
sc->nirqs = 32 * ((sc->nirqs & 0x1f) + 1);
/* Set up function pointers */
arm_post_filter = gic_post_filter;
arm_config_irq = gic_config_irq;
icciidr = gic_c_read_4(GICC_IIDR);
icciidr = gic_c_read_4(sc, GICC_IIDR);
device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n",
icciidr>>20, (icciidr>>16) & 0xF, (icciidr>>12) & 0xf,
(icciidr & 0xfff), sc->nirqs);
/* Set all global interrupts to be level triggered, active low. */
for (i = 32; i < sc->nirqs; i += 16) {
gic_d_write_4(GICD_ICFGR(i >> 4), 0x00000000);
gic_d_write_4(sc, GICD_ICFGR(i >> 4), 0x00000000);
}
/* Disable all interrupts. */
for (i = 32; i < sc->nirqs; i += 32) {
gic_d_write_4(GICD_ICENABLER(i >> 5), 0xFFFFFFFF);
gic_d_write_4(sc, GICD_ICENABLER(i >> 5), 0xFFFFFFFF);
}
for (i = 0; i < sc->nirqs; i += 4) {
gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
gic_d_write_4(GICD_ITARGETSR(i >> 2), 1 << 0 | 1 << 8 | 1 << 16 | 1 << 24);
gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0);
gic_d_write_4(sc, GICD_ITARGETSR(i >> 2),
1 << 0 | 1 << 8 | 1 << 16 | 1 << 24);
}
/* Set all the interrupts to be in Group 0 (secure) */
for (i = 0; i < sc->nirqs; i += 32) {
gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
}
/* Enable CPU interface */
gic_c_write_4(GICC_CTLR, 1);
gic_c_write_4(sc, GICC_CTLR, 1);
/* Set priority mask register. */
gic_c_write_4(GICC_PMR, 0xff);
gic_c_write_4(sc, GICC_PMR, 0xff);
/* Enable interrupt distribution */
gic_d_write_4(GICD_CTLR, 0x01);
gic_d_write_4(sc, GICD_CTLR, 0x01);
return (0);
}
@ -335,28 +337,29 @@ EARLY_DRIVER_MODULE(gic, ofwbus, arm_gic_driver, arm_gic_devclass, 0, 0,
static void
gic_post_filter(void *arg)
{
struct arm_gic_softc *sc = arm_gic_sc;
uintptr_t irq = (uintptr_t) arg;
if (irq > GIC_LAST_IPI)
arm_irq_memory_barrier(irq);
gic_c_write_4(GICC_EOIR, irq);
gic_c_write_4(sc, GICC_EOIR, irq);
}
int
arm_get_next_irq(int last_irq)
{
struct arm_gic_softc *sc = arm_gic_sc;
uint32_t active_irq;
active_irq = gic_c_read_4(GICC_IAR);
active_irq = gic_c_read_4(sc, GICC_IAR);
/*
* Immediatly EOIR the SGIs, because doing so requires the other
* bits (ie CPU number), not just the IRQ number, and we do not
* have this information later.
*/
if ((active_irq & 0x3ff) <= GIC_LAST_IPI)
gic_c_write_4(GICC_EOIR, active_irq);
gic_c_write_4(sc, GICC_EOIR, active_irq);
active_irq &= 0x3FF;
if (active_irq == 0x3FF) {
@ -371,29 +374,32 @@ arm_get_next_irq(int last_irq)
void
arm_mask_irq(uintptr_t nb)
{
struct arm_gic_softc *sc = arm_gic_sc;
gic_d_write_4(GICD_ICENABLER(nb >> 5), (1UL << (nb & 0x1F)));
gic_c_write_4(GICC_EOIR, nb);
gic_d_write_4(sc, GICD_ICENABLER(nb >> 5), (1UL << (nb & 0x1F)));
gic_c_write_4(sc, GICC_EOIR, nb);
}
void
arm_unmask_irq(uintptr_t nb)
{
struct arm_gic_softc *sc = arm_gic_sc;
if (nb > GIC_LAST_IPI)
arm_irq_memory_barrier(nb);
gic_d_write_4(GICD_ISENABLER(nb >> 5), (1UL << (nb & 0x1F)));
gic_d_write_4(sc, GICD_ISENABLER(nb >> 5), (1UL << (nb & 0x1F)));
}
static int
gic_config_irq(int irq, enum intr_trigger trig,
enum intr_polarity pol)
{
struct arm_gic_softc *sc = arm_gic_sc;
uint32_t reg;
uint32_t mask;
/* Function is public-accessible, so validate input arguments */
if ((irq < 0) || (irq >= arm_gic_sc->nirqs))
if ((irq < 0) || (irq >= sc->nirqs))
goto invalid_args;
if ((trig != INTR_TRIGGER_EDGE) && (trig != INTR_TRIGGER_LEVEL) &&
(trig != INTR_TRIGGER_CONFORM))
@ -402,9 +408,9 @@ gic_config_irq(int irq, enum intr_trigger trig,
(pol != INTR_POLARITY_CONFORM))
goto invalid_args;
mtx_lock_spin(&arm_gic_sc->mutex);
mtx_lock_spin(&sc->mutex);
reg = gic_d_read_4(GICD_ICFGR(irq >> 4));
reg = gic_d_read_4(sc, GICD_ICFGR(irq >> 4));
mask = (reg >> 2*(irq % 16)) & 0x3;
if (pol == INTR_POLARITY_LOW) {
@ -426,14 +432,14 @@ gic_config_irq(int irq, enum intr_trigger trig,
/* Set mask */
reg = reg & ~(0x3 << 2*(irq % 16));
reg = reg | (mask << 2*(irq % 16));
gic_d_write_4(GICD_ICFGR(irq >> 4), reg);
gic_d_write_4(sc, GICD_ICFGR(irq >> 4), reg);
mtx_unlock_spin(&arm_gic_sc->mutex);
mtx_unlock_spin(&sc->mutex);
return (0);
invalid_args:
device_printf(arm_gic_sc->dev, "gic_config_irg, invalid parameters\n");
device_printf(sc->dev, "gic_config_irg, invalid parameters\n");
return (EINVAL);
}
@ -441,13 +447,14 @@ invalid_args:
void
pic_ipi_send(cpuset_t cpus, u_int ipi)
{
struct arm_gic_softc *sc = arm_gic_sc;
uint32_t val = 0, i;
for (i = 0; i < MAXCPU; i++)
if (CPU_ISSET(i, &cpus))
val |= 1 << (16 + i);
gic_d_write_4(GICD_SGIR(0), val | ipi);
gic_d_write_4(sc, GICD_SGIR(0), val | ipi);
}
int