diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 79636b5dba57..07090d291411 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -1410,12 +1410,27 @@ cpu_scc_setup_ccnt(void)
  * you want!
  */
 #ifdef _PMC_USER_READ_WRITE_
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+	/* Use the Secure User and Non-secure Access Validation Control Register
+	 * to allow userland access
+	 */
+	__asm volatile ("mcr	p15, 0, %0, c15, c9, 0\n\t"
+			:
+			: "r"(0x00000001));
+#else
 	/* Set PMUSERENR[0] to allow userland access */
 	__asm volatile ("mcr	p15, 0, %0, c9, c14, 0\n\t"
 			:
 			: "r"(0x00000001));
 #endif
-        /* Set up the PMCCNTR register as a cyclecounter:
+#endif
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+	/* Set PMCR[2,0] to enable counters and reset CCNT */
+	__asm volatile ("mcr	p15, 0, %0, c15, c12, 0\n\t"
+			:
+			: "r"(0x00000005));
+#else
+	/* Set up the PMCCNTR register as a cyclecounter:
 	 * Set PMINTENCLR to 0xFFFFFFFF to block interrupts
 	 * Set PMCR[2,0] to enable counters and reset CCNT
 	 * Set PMCNTENSET to 0x80000000 to enable CCNT */
@@ -1426,6 +1441,7 @@ cpu_scc_setup_ccnt(void)
 			: "r"(0xFFFFFFFF),
 			  "r"(0x00000005),
 			  "r"(0x80000000));
+#endif
 }
 #endif
 
diff --git a/sys/arm/include/cpu.h b/sys/arm/include/cpu.h
index d63979ed8913..dd7b6acce3ee 100644
--- a/sys/arm/include/cpu.h
+++ b/sys/arm/include/cpu.h
@@ -25,7 +25,16 @@ get_cyclecount(void)
 	 * Read PMCCNTR. Curses! Its only 32 bits.
 	 * TODO: Fix this by catching overflow with interrupt?
 	 */
+/* The ARMv6 vs ARMv7 divide is going to need a better way of
+ * distinguishing between them.
+ */
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+	/* ARMv6 - Earlier model SCCs */
+	__asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=r" (ccnt));
+#else
+	/* ARMv7 - Later model SCCs */
 	__asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
+#endif
 	ccnt64 = (uint64_t)ccnt;
 	return (ccnt64);
 #else /* No performance counters, so use binuptime(9). This is slooooow */