- Take into account only unmasked bits in interrupt status register
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@ -86,9 +86,10 @@ ar71xx_pci_mask_irq(void *source)
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uint32_t reg;
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unsigned int irq = (unsigned int)source;
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reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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/* flush */
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reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg & ~(1 << irq));
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}
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static void
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@ -99,6 +100,8 @@ ar71xx_pci_unmask_irq(void *source)
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reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq));
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/* flush */
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reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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}
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/*
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@ -294,10 +297,12 @@ ar71xx_pci_attach(device_t dev)
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reset |= (RST_RESET_PCI_CORE | RST_RESET_PCI_BUS);
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ATH_WRITE_REG(AR71XX_RST_RESET, reset);
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DELAY(1000);
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ATH_READ_REG(AR71XX_RST_RESET);
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reset &= ~(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS);
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ATH_WRITE_REG(AR71XX_RST_RESET, reset);
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DELAY(1000);
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ATH_READ_REG(AR71XX_RST_RESET);
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/* Init PCI windows */
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ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR);
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@ -472,9 +477,14 @@ ar71xx_pci_intr(void *arg)
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{
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struct ar71xx_pci_softc *sc = arg;
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struct intr_event *event;
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uint32_t reg, irq;
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uint32_t reg, irq, mask;
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reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS);
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mask = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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/*
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* Handle only unmasked interrupts
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*/
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reg &= mask;
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for (irq = AR71XX_PCI_IRQ_START; irq <= AR71XX_PCI_IRQ_END; irq++) {
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if (reg & (1 << irq)) {
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event = sc->sc_eventstab[irq];
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