Aaron Daily of Adaptec has informed me that some form of paged SCB
algorithm is used on aic7770 Rev E or higher chips to improve perfomance. This required a hardware change but we don't know exactly what (most likely some special register to do fast SCB indexing into host memory), and we are not at all sure that there are more than 4 SCBs on these chips. This probe will still classify the revision of the aic7xxx, but we now default to 4 SCBs (at least until we know more of what was done). This also fixes a bug in the timeout routine where we cleared a flag too soon making it imposible to enter one section of the routine. Submitted by: Timeout bug - Dan Eischen <deischen@iworks.InterWorks.org>
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@ -24,7 +24,7 @@
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*
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* commenced: Sun Sep 27 18:14:01 PDT 1992
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*
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* $Id: aic7xxx.c,v 1.23 1995/04/27 17:47:16 gibbs Exp $
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* $Id: aic7xxx.c,v 1.24 1995/05/01 09:49:45 gibbs Exp $
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*/
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/*
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* TODO:
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@ -1510,9 +1510,9 @@ ahc_init(unit)
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{
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/*
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* See if we have a Rev E or higher
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* aic7770. If so, use 16 SCBs.
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* Anything below a Rev E will have a
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* R/O autoflush disable configuration bit.
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* aic7770. Anything below a Rev E will
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* have a R/O autoflush disable configuration
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* bit.
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*/
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u_char sblkctl_orig;
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sblkctl_orig = inb(SBLKCTL + iobase);
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@ -1522,7 +1522,6 @@ ahc_init(unit)
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if(sblkctl != sblkctl_orig)
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{
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printf("aic7770 >= Rev E, ");
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ahc->maxscbs = 0x10;
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/*
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* Ensure autoflush is enabled
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*/
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@ -2113,7 +2112,6 @@ ahc_abort_scb( unit, ahc, scb )
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goto done;
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}
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scb_control = inb(SCBARRAY + iobase);
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scb_control &= ~SCB_DIS;
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if( scb_control & SCB_DIS ) {
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scb_control &= ~SCB_DIS;
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outb(SCBARRAY + iobase, scb_control);
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