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mips: use the correct va for wbinv flushing.

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arge doesn't trigger this, but ath(4) does.

Tested:

* AR9331 SoC (Carambola2); ath(4) hostap

Submitted by:	ian
This commit is contained in:
Adrian Chadd 2015-10-27 23:11:22 +00:00
parent a57418a761
commit 87af896340
1 changed files with 1 additions and 1 deletions
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2
sys/mips/mips/busdma_machdep.c
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@ -1128,7 +1128,7 @@ bus_dmamap_sync_buf(vm_offset_t buf, int len, bus_dmasync_op_t op, int aligned)
break;
case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE:
mips_dcache_wbinv_range(buf_cl, len);
mips_dcache_wbinv_range(buf, len);
break;
case BUS_DMASYNC_PREREAD: