Bulk changes made during the BSDcon kernel summit and travel afterwards.
Appologies for making this one bulk commit, but I have tested all these changes together and don't want to break anything by trying to disentangle it. o Make debugging a sysctl/tunable o Remove flags word from yenta chip info, it is unused o Make 16-bit card I/O range and 32-bit card I/O range tunables o Start the rename of pccbb to cbb to match NetBSD by misc renames. o Kill the now bogus list of softcs to create kthread. Instead, just create the kthread in the attach routine. o Remove sc_ from some structure names. It isn't needed. o Refine chipset lookup code. o Match generic PCI <-> CardBus bridges. We specifically don't generically match PCI PCMCIA bridges because they are not, with one exception, yenta devices. o Add some comments about the why we need to have a function table ala OLDCARD o The PCI interrupt routing by using the ExCA registers is needed for for all bridges, per the spec, not just TI ones. o Collapse TOPIC95 and TOPIC95B. o Using the ToPIC 97 and 100 datasheets, try to support these bridges better, but more work is needed. o Generally clarify some XXX comments and add them in a few places where things didn't look right to me. o Move interrupt generating register access until after we establish an ISR. o Add support for YV and XV cards. X and Y are numbers to be determined later (but maybe never). o factor powerup code for 16-bit and 32-bit cards. o When a card supports more than one voltage, prefer the lowest supported volage. Windows does this, and MS's design guides imply this is the right thing to do. o Document race between kthread_exit(0) and kldunload's unmapping of pages that John Baldwin and I discovered. o Debounce the CSC interrupt a little better. o When a 16-bit card is inserted when we don't have a pccard child, warn about it better. Ditto for 32-bit card. o Ack ALL the interrupt bits that we get, not just 0x1. o maybe a couple minor style nits corrected.
This commit is contained in:
imp
parent
3985693d09
commit
88a25257e9
File diff suppressed because it is too large
Load Diff
@ -34,133 +34,149 @@
|
||||
|
||||
|
||||
/* PCI header registers */
|
||||
#define PCCBBR_SOCKBASE 0x10 /* len=4 */
|
||||
#define CBBR_SOCKBASE 0x10 /* len=4 */
|
||||
|
||||
#define PCCBBR_MEMBASE0 0x1c /* len=4 */
|
||||
#define PCCBBR_MEMLIMIT0 0x20 /* len=4 */
|
||||
#define PCCBBR_MEMBASE1 0x24 /* len=4 */
|
||||
#define PCCBBR_MEMLIMIT1 0x28 /* len=4 */
|
||||
#define PCCBBR_IOBASE0 0x2c /* len=4 */
|
||||
#define PCCBBR_IOLIMIT0 0x30 /* len=4 */
|
||||
#define PCCBBR_IOBASE1 0x34 /* len=4 */
|
||||
#define PCCBBR_IOLIMIT1 0x38 /* len=4 */
|
||||
#define PCCBB_MEMALIGN 4096
|
||||
#define PCCBB_IOALIGN 4
|
||||
#define CBBR_MEMBASE0 0x1c /* len=4 */
|
||||
#define CBBR_MEMLIMIT0 0x20 /* len=4 */
|
||||
#define CBBR_MEMBASE1 0x24 /* len=4 */
|
||||
#define CBBR_MEMLIMIT1 0x28 /* len=4 */
|
||||
#define CBBR_IOBASE0 0x2c /* len=4 */
|
||||
#define CBBR_IOLIMIT0 0x30 /* len=4 */
|
||||
#define CBBR_IOBASE1 0x34 /* len=4 */
|
||||
#define CBBR_IOLIMIT1 0x38 /* len=4 */
|
||||
#define CBB_MEMALIGN 4096
|
||||
#define CBB_IOALIGN 4
|
||||
|
||||
#define PCCBBR_INTRLINE 0x3c /* len=1 */
|
||||
#define PCCBBR_INTRPIN 0x3d /* len=1 */
|
||||
#define PCCBBR_BRIDGECTRL 0x3e /* len=2 */
|
||||
# define PCCBBM_BRIDGECTRL_MASTER_ABORT 0x0020
|
||||
# define PCCBBM_BRIDGECTRL_RESET 0x0040
|
||||
# define PCCBBM_BRIDGECTRL_INTR_IREQ_EN 0x0080
|
||||
# define PCCBBM_BRIDGECTRL_PREFETCH_0 0x0100
|
||||
# define PCCBBM_BRIDGECTRL_PREFETCH_1 0x0200
|
||||
# define PCCBBM_BRIDGECTRL_WRITE_POST_EN 0x0400
|
||||
#define CBBR_INTRLINE 0x3c /* len=1 */
|
||||
#define CBBR_INTRPIN 0x3d /* len=1 */
|
||||
#define CBBR_BRIDGECTRL 0x3e /* len=2 */
|
||||
# define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020
|
||||
# define CBBM_BRIDGECTRL_RESET 0x0040
|
||||
# define CBBM_BRIDGECTRL_INTR_IREQ_EN 0x0080
|
||||
# define CBBM_BRIDGECTRL_PREFETCH_0 0x0100
|
||||
# define CBBM_BRIDGECTRL_PREFETCH_1 0x0200
|
||||
# define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400
|
||||
/* additional bit for RF5C46[567] */
|
||||
# define PCCBBM_BRIDGECTRL_RL_3E0_EN 0x0800
|
||||
# define PCCBBM_BRIDGECTRL_RL_3E2_EN 0x1000
|
||||
# define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800
|
||||
# define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000
|
||||
|
||||
#define PCCBBR_LEGACY 0x44 /* len=4 */
|
||||
#define CBBR_LEGACY 0x44 /* len=4 */
|
||||
|
||||
#define PCCBBR_CBCTRL 0x91 /* len=1 */
|
||||
#define CBBR_CBCTRL 0x91 /* len=1 */
|
||||
/* bits for TI 113X */
|
||||
# define PCCBBM_CBCTRL_113X_RI_EN 0x80
|
||||
# define PCCBBM_CBCTRL_113X_ZV_EN 0x40
|
||||
# define PCCBBM_CBCTRL_113X_PCI_IRQ_EN 0x20
|
||||
# define PCCBBM_CBCTRL_113X_PCI_INTR 0x10
|
||||
# define PCCBBM_CBCTRL_113X_PCI_CSC 0x08
|
||||
# define PCCBBM_CBCTRL_113X_PCI_CSC_D 0x04
|
||||
# define PCCBBM_CBCTRL_113X_SPEAKER_EN 0x02
|
||||
# define PCCBBM_CBCTRL_113X_INTR_DET 0x01
|
||||
# define CBBM_CBCTRL_113X_RI_EN 0x80
|
||||
# define CBBM_CBCTRL_113X_ZV_EN 0x40
|
||||
# define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20
|
||||
# define CBBM_CBCTRL_113X_PCI_INTR 0x10
|
||||
# define CBBM_CBCTRL_113X_PCI_CSC 0x08
|
||||
# define CBBM_CBCTRL_113X_PCI_CSC_D 0x04
|
||||
# define CBBM_CBCTRL_113X_SPEAKER_EN 0x02
|
||||
# define CBBM_CBCTRL_113X_INTR_DET 0x01
|
||||
/* bits for TI 12XX */
|
||||
# define PCCBBM_CBCTRL_12XX_RI_EN 0x80
|
||||
# define PCCBBM_CBCTRL_12XX_ZV_EN 0x40
|
||||
# define PCCBBM_CBCTRL_12XX_AUD2MUX 0x04
|
||||
# define PCCBBM_CBCTRL_12XX_SPEAKER_EN 0x02
|
||||
# define PCCBBM_CBCTRL_12XX_INTR_DET 0x01
|
||||
#define PCCBBR_DEVCTRL 0x92 /* len=1 */
|
||||
# define PCCBBM_DEVCTRL_INT_SERIAL 0x04
|
||||
# define PCCBBM_DEVCTRL_INT_PCI 0x02
|
||||
# define CBBM_CBCTRL_12XX_RI_EN 0x80
|
||||
# define CBBM_CBCTRL_12XX_ZV_EN 0x40
|
||||
# define CBBM_CBCTRL_12XX_AUD2MUX 0x04
|
||||
# define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02
|
||||
# define CBBM_CBCTRL_12XX_INTR_DET 0x01
|
||||
#define CBBR_DEVCTRL 0x92 /* len=1 */
|
||||
# define CBBM_DEVCTRL_INT_SERIAL 0x04
|
||||
# define CBBM_DEVCTRL_INT_PCI 0x02
|
||||
|
||||
#define PCCBBR_TOPIC_SOCKETCTRL 0x90
|
||||
# define PCCBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
|
||||
/* ToPIC 95 ONLY */
|
||||
#define CBBR_TOPIC_SOCKETCTRL 0x90
|
||||
# define CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
|
||||
/* ToPIC 97, 100 */
|
||||
#define CBBR_TOPIC_ZV_CONTROL 0x9c /* 1 byte */
|
||||
# define CBBM_TOPIC_ZVC_ENABLE 0x1
|
||||
|
||||
#define PCCBBR_TOPIC_SLOTCTRL 0xa0
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_SLOTON 0x00000080
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_SLOTEN 0x00000040
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_ID_LOCK 0x00000020
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_ID_WP 0x00000010
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_PORT_MASK 0x0000000c
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_PORT_SHIFT 2
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_OSF_MASK 0x00000003
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_OSF_SHIFT 0
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_INTB 0x00002000
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_INTA 0x00001000
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_INT_MASK 0x00003000
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_CLOCK_MASK 0x00000c00
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_CLOCK_2 0x00000800 /* PCI Clk/2 */
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_CLOCK_1 0x00000400 /* PCI Clk */
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_CLOCK_0 0x00000000 /* no clock */
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_CARDBUS 0x80000000
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_VS1 0x04000000
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_VS2 0x02000000
|
||||
# define PCCBBM_TOPIC_SLOTCTRL_SWDETECT 0x01000000
|
||||
/* TOPIC 95+ */
|
||||
#define CBBR_TOPIC_SLOTCTRL 0xa0 /* 1 byte */
|
||||
# define CBBM_TOPIC_SLOTCTRL_SLOTON 0x80
|
||||
# define CBBM_TOPIC_SLOTCTRL_SLOTEN 0x40
|
||||
# define CBBM_TOPIC_SLOTCTRL_ID_LOCK 0x20
|
||||
# define CBBM_TOPIC_SLOTCTRL_ID_WP 0x10
|
||||
# define CBBM_TOPIC_SLOTCTRL_PORT_MASK 0x0c
|
||||
# define CBBM_TOPIC_SLOTCTRL_PORT_SHIFT 2
|
||||
# define CBBM_TOPIC_SLOTCTRL_OSF_MASK 0x03
|
||||
# define CBBM_TOPIC_SLOTCTRL_OSF_SHIFT 0
|
||||
|
||||
/* TOPIC 95+ */
|
||||
#define CBBR_TOPIC_INTCTRL 0xa1 /* 1 byte */
|
||||
# define CBBM_TOPIC_INTCTRL_INTB 0x20
|
||||
# define CBBM_TOPIC_INTCTRL_INTA 0x10
|
||||
# define CBBM_TOPIC_INTCTRL_INT_MASK 0x30
|
||||
/* The following bits may be for ToPIC 95 only */
|
||||
# define CBBM_TOPIC_INTCTRL_CLOCK_MASK 0x0c
|
||||
# define CBBM_TOPIC_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */
|
||||
# define CBBM_TOPIC_INTCTRL_CLOCK_1 0x04 /* PCI Clk */
|
||||
# define CBBM_TOPIC_INTCTRL_CLOCK_0 0x00 /* no clock */
|
||||
/* ToPIC97, 100 defines the following bits */
|
||||
# define CBBM_TOPIC_INTCTRL_STSIRQNP 0x04
|
||||
# define CBBM_TOPIC_INTCTRL_IRQNP 0x02
|
||||
# define CBBM_TOPIC_INTCTRL_INTIRQSEL 0x01
|
||||
|
||||
/* TOPIC 95+ */
|
||||
#define CBBR_TOPIC_CDC 0xa3 /* 1 byte */
|
||||
# define CBBM_TOPIC_CDC_CARDBUS 0x80
|
||||
# define CBBM_TOPIC_CDC_VS1 0x04
|
||||
# define CBBM_TOPIC_CDC_VS2 0x02
|
||||
# define CBBM_TOPIC_CDC_SWDETECT 0x01
|
||||
|
||||
/* Socket definitions */
|
||||
#define PCCBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */
|
||||
#define PCCBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */
|
||||
#define PCCBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */
|
||||
#define PCCBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */
|
||||
#define PCCBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */
|
||||
#define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */
|
||||
#define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */
|
||||
#define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */
|
||||
#define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */
|
||||
#define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */
|
||||
|
||||
#define PCCBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */
|
||||
#define PCCBB_SOCKET_MASK_CD 0x06 /* Card Detect */
|
||||
#define PCCBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */
|
||||
#define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */
|
||||
#define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */
|
||||
#define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */
|
||||
|
||||
#define PCCBB_SOCKET_STAT_CARDSTS 0x00000001 /* Card Status Change */
|
||||
#define PCCBB_SOCKET_STAT_CD1 0x00000002 /* Card Detect 1 */
|
||||
#define PCCBB_SOCKET_STAT_CD2 0x00000004 /* Card Detect 2 */
|
||||
#define PCCBB_SOCKET_STAT_CD 0x00000006 /* Card Detect all */
|
||||
#define PCCBB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power Cycle */
|
||||
#define PCCBB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit Card */
|
||||
#define PCCBB_SOCKET_STAT_CB 0x00000020 /* Cardbus Card */
|
||||
#define PCCBB_SOCKET_STAT_IREQ 0x00000040 /* Ready */
|
||||
#define PCCBB_SOCKET_STAT_NOTCARD 0x00000080 /* Unrecognized Card */
|
||||
#define PCCBB_SOCKET_STAT_DATALOST 0x00000100 /* Data Lost */
|
||||
#define PCCBB_SOCKET_STAT_BADVCC 0x00000200 /* Bad VccRequest */
|
||||
#define PCCBB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */
|
||||
#define PCCBB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */
|
||||
#define PCCBB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */
|
||||
#define PCCBB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */
|
||||
#define PCCBB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */
|
||||
#define PCCBB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */
|
||||
#define PCCBB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */
|
||||
#define PCCBB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */
|
||||
#define CBB_SOCKET_STAT_CARDSTS 0x00000001 /* Card Status Change */
|
||||
#define CBB_SOCKET_STAT_CD1 0x00000002 /* Card Detect 1 */
|
||||
#define CBB_SOCKET_STAT_CD2 0x00000004 /* Card Detect 2 */
|
||||
#define CBB_SOCKET_STAT_CD 0x00000006 /* Card Detect all */
|
||||
#define CBB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power Cycle */
|
||||
#define CBB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit Card */
|
||||
#define CBB_SOCKET_STAT_CB 0x00000020 /* Cardbus Card */
|
||||
#define CBB_SOCKET_STAT_IREQ 0x00000040 /* Ready */
|
||||
#define CBB_SOCKET_STAT_NOTCARD 0x00000080 /* Unrecognized Card */
|
||||
#define CBB_SOCKET_STAT_DATALOST 0x00000100 /* Data Lost */
|
||||
#define CBB_SOCKET_STAT_BADVCC 0x00000200 /* Bad VccRequest */
|
||||
#define CBB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */
|
||||
#define CBB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */
|
||||
#define CBB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */
|
||||
#define CBB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */
|
||||
#define CBB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */
|
||||
#define CBB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */
|
||||
#define CBB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */
|
||||
#define CBB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */
|
||||
|
||||
#define PCCBB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */
|
||||
#define CBB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */
|
||||
|
||||
#define PCCBB_SOCKET_CTRL_VPPMASK 0x07
|
||||
#define PCCBB_SOCKET_CTRL_VPP_OFF 0x00
|
||||
#define PCCBB_SOCKET_CTRL_VPP_12V 0x01
|
||||
#define PCCBB_SOCKET_CTRL_VPP_5V 0x02
|
||||
#define PCCBB_SOCKET_CTRL_VPP_3V 0x03
|
||||
#define PCCBB_SOCKET_CTRL_VPP_XV 0x04
|
||||
#define PCCBB_SOCKET_CTRL_VPP_YV 0x05
|
||||
#define CBB_SOCKET_CTRL_VPPMASK 0x07
|
||||
#define CBB_SOCKET_CTRL_VPP_OFF 0x00
|
||||
#define CBB_SOCKET_CTRL_VPP_12V 0x01
|
||||
#define CBB_SOCKET_CTRL_VPP_5V 0x02
|
||||
#define CBB_SOCKET_CTRL_VPP_3V 0x03
|
||||
#define CBB_SOCKET_CTRL_VPP_XV 0x04
|
||||
#define CBB_SOCKET_CTRL_VPP_YV 0x05
|
||||
|
||||
#define PCCBB_SOCKET_CTRL_VCCMASK 0x70
|
||||
#define PCCBB_SOCKET_CTRL_VCC_OFF 0x00
|
||||
#define PCCBB_SOCKET_CTRL_VCC_5V 0x20
|
||||
#define PCCBB_SOCKET_CTRL_VCC_3V 0x30
|
||||
#define PCCBB_SOCKET_CTRL_VCC_XV 0x40
|
||||
#define PCCBB_SOCKET_CTRL_VCC_YV 0x50
|
||||
#define CBB_SOCKET_CTRL_VCCMASK 0x70
|
||||
#define CBB_SOCKET_CTRL_VCC_OFF 0x00
|
||||
#define CBB_SOCKET_CTRL_VCC_5V 0x20
|
||||
#define CBB_SOCKET_CTRL_VCC_3V 0x30
|
||||
#define CBB_SOCKET_CTRL_VCC_XV 0x40
|
||||
#define CBB_SOCKET_CTRL_VCC_YV 0x50
|
||||
|
||||
#define PCCBB_SOCKET_CTRL_STOPCLK 0x80
|
||||
#define CBB_SOCKET_CTRL_STOPCLK 0x80
|
||||
|
||||
#include <dev/pccbb/pccbbdevid.h>
|
||||
|
||||
#define PCCBB_SOCKET_EVENT 0x00
|
||||
#define PCCBB_SOCKET_MASK 0x04
|
||||
#define PCCBB_SOCKET_STATE 0x08
|
||||
#define PCCBB_SOCKET_FORCE 0x0c
|
||||
#define PCCBB_SOCKET_CONTROL 0x10
|
||||
#define PCCBB_SOCKET_POWER 0x14
|
||||
#define CBB_SOCKET_EVENT 0x00
|
||||
#define CBB_SOCKET_MASK 0x04
|
||||
#define CBB_SOCKET_STATE 0x08
|
||||
#define CBB_SOCKET_FORCE 0x0c
|
||||
#define CBB_SOCKET_CONTROL 0x10
|
||||
#define CBB_SOCKET_POWER 0x14
|
||||
|
||||
@ -53,37 +53,35 @@ struct pccbb_reslist {
|
||||
#define PCCBB_AUTO_OPEN_SMALLHOLE 0x100
|
||||
|
||||
struct pccbb_softc {
|
||||
device_t sc_dev;
|
||||
device_t dev;
|
||||
struct exca_softc exca;
|
||||
struct resource *sc_base_res;
|
||||
struct resource *sc_irq_res;
|
||||
void *sc_intrhand;
|
||||
bus_space_tag_t sc_bst;
|
||||
bus_space_handle_t sc_bsh;
|
||||
u_int8_t sc_secbus;
|
||||
u_int8_t sc_subbus;
|
||||
struct mtx sc_mtx;
|
||||
u_int32_t sc_flags;
|
||||
struct resource *base_res;
|
||||
struct resource *irq_res;
|
||||
void *intrhand;
|
||||
bus_space_tag_t bst;
|
||||
bus_space_handle_t bsh;
|
||||
u_int8_t secbus;
|
||||
u_int8_t subbus;
|
||||
struct mtx mtx;
|
||||
u_int32_t flags;
|
||||
#define PCCBB_16BIT_CARD 0x02000000
|
||||
#define PCCBB_KTHREAD_RUNNING 0x04000000
|
||||
#define PCCBB_KTHREAD_DONE 0x08000000
|
||||
int sc_chipset; /* chipset id */
|
||||
int chipset; /* chipset id */
|
||||
#define CB_UNKNOWN 0 /* NOT Cardbus-PCI bridge */
|
||||
#define CB_TI113X 1 /* TI PCI1130/1131 */
|
||||
#define CB_TI12XX 2 /* TI PCI1250/1220 */
|
||||
#define CB_RF5C47X 3 /* RICOH RF5C475/476/477 */
|
||||
#define CB_RF5C46X 4 /* RICOH RF5C465/466/467 */
|
||||
#define CB_TOPIC95 5 /* Toshiba ToPIC95 */
|
||||
#define CB_TOPIC95B 6 /* Toshiba ToPIC95B */
|
||||
#define CB_CIRRUS 5 /* Cirrus Logic CLPD683x */
|
||||
#define CB_TOPIC95 6 /* Toshiba ToPIC95 */
|
||||
#define CB_TOPIC97 7 /* Toshiba ToPIC97/100 */
|
||||
#define CB_CIRRUS 8 /* Cirrus Logic CLPD683x */
|
||||
SLIST_HEAD(, pccbb_reslist) rl;
|
||||
|
||||
device_t sc_cbdev;
|
||||
device_t sc_pccarddev;
|
||||
device_t cbdev;
|
||||
device_t pccarddev;
|
||||
|
||||
/* kthread staff */
|
||||
struct proc *event_thread;
|
||||
struct proc *event_thread;
|
||||
};
|
||||
|
||||
/* result of detect_card */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user