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MFC r281592, r281918, r282119, r282266:

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- Fix the length of efuse content
- Disable usb aggregation mode by default since it boots performance
This commit is contained in:
kevlo 2015-05-03 15:09:34 +00:00
parent 6095111181
commit 89820200ab
2 changed files with 44 additions and 19 deletions
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1
sys/dev/usb/usbdevs
View File

@ -3729,6 +3729,7 @@ product REALTEK RTL8188CU_1 0x817a RTL8188CU
product REALTEK RTL8188CU_2 0x817b RTL8188CU
product REALTEK RTL8187 0x8187 RTL8187 Wireless Adapter
product REALTEK RTL8187B_0 0x8189 RTL8187B Wireless Adapter
product REALTEK RTL8188CU_3 0x8191 RTL8188CU
product REALTEK RTL8196EU 0x8196 RTL8196EU
product REALTEK RTL8187B_1 0x8197 RTL8187B Wireless Adapter
product REALTEK RTL8187B_2 0x8198 RTL8187B Wireless Adapter

62
sys/dev/usb/wlan/if_urtwn.c
View File

@ -136,6 +136,7 @@ static const STRUCT_USB_HOST_ID urtwn_devs[] = {
URTWN_DEV(REALTEK, RTL8188CU_0),
URTWN_DEV(REALTEK, RTL8188CU_1),
URTWN_DEV(REALTEK, RTL8188CU_2),
URTWN_DEV(REALTEK, RTL8188CU_3),
URTWN_DEV(REALTEK, RTL8188CU_COMBO),
URTWN_DEV(REALTEK, RTL8188CUS),
URTWN_DEV(REALTEK, RTL8188RU_1),
@ -144,7 +145,6 @@ static const STRUCT_USB_HOST_ID urtwn_devs[] = {
URTWN_DEV(REALTEK, RTL8191CU),
URTWN_DEV(REALTEK, RTL8192CE),
URTWN_DEV(REALTEK, RTL8192CU),
URTWN_DEV(REALTEK, RTL8188CU_0),
URTWN_DEV(SITECOMEU, RTL8188CU_1),
URTWN_DEV(SITECOMEU, RTL8188CU_2),
URTWN_DEV(SITECOMEU, RTL8192CU),
@ -1188,7 +1188,7 @@ urtwn_efuse_read(struct urtwn_softc *sc)
uint8_t *rom = (uint8_t *)&sc->rom;
uint16_t addr = 0;
uint32_t reg;
uint8_t off, msk;
uint8_t off, msk, vol;
int i;
urtwn_efuse_switch_power(sc);
@ -1221,12 +1221,19 @@ urtwn_efuse_read(struct urtwn_softc *sc)
printf("\n");
}
#endif
/* Disable LDO 2.5V. */
vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3);
urtwn_write_1(sc, R92C_EFUSE_TEST + 3, vol & ~(0x80));
}
static void
urtwn_efuse_switch_power(struct urtwn_softc *sc)
{
uint32_t reg;
if (sc->chip & URTWN_CHIP_88E)
urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON);
reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
@ -1243,6 +1250,16 @@ urtwn_efuse_switch_power(struct urtwn_softc *sc)
urtwn_write_2(sc, R92C_SYS_CLKR,
reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
}
if (!(sc->chip & URTWN_CHIP_88E)) {
uint8_t vol;
/* Enable LDO 2.5V. */
vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3);
vol &= 0x0f;
vol |= 0x30;
urtwn_write_1(sc, R92C_EFUSE_TEST + 3, (vol | 0x80));
}
}
static int
@ -1310,7 +1327,7 @@ urtwn_r88e_read_rom(struct urtwn_softc *sc)
/* Read full ROM image. */
memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom));
while (addr < 1024) {
while (addr < 512) {
reg = urtwn_efuse_read_1(sc, addr);
if (reg == 0xff)
break;
@ -1336,6 +1353,8 @@ urtwn_r88e_read_rom(struct urtwn_softc *sc)
}
}
urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF);
addr = 0x10;
for (i = 0; i < 6; i++)
sc->cck_tx_pwr[i] = sc->r88e_rom[addr++];
@ -2175,14 +2194,12 @@ urtwn_r92c_power_on(struct urtwn_softc *sc)
static int
urtwn_r88e_power_on(struct urtwn_softc *sc)
{
uint8_t val;
uint32_t reg;
int ntries;
/* Wait for power ready bit. */
for (ntries = 0; ntries < 5000; ntries++) {
val = urtwn_read_1(sc, 0x6) & 0x2;
if (val == 0x2)
if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
break;
urtwn_ms_delay(sc);
}
@ -2197,17 +2214,23 @@ urtwn_r88e_power_on(struct urtwn_softc *sc)
urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
R92C_SYS_FUNC_EN_BB_GLB_RST));
urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80);
urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2,
urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80);
/* Disable HWPDN. */
urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80);
urtwn_write_2(sc, R92C_APS_FSMCO,
urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN);
/* Disable WL suspend. */
urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18);
urtwn_write_2(sc, R92C_APS_FSMCO,
urtwn_read_2(sc, R92C_APS_FSMCO) &
~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE));
urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1);
urtwn_write_2(sc, R92C_APS_FSMCO,
urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
for (ntries = 0; ntries < 5000; ntries++) {
if (!(urtwn_read_1(sc, 0x5) & 0x1))
if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_ONMAC))
break;
urtwn_ms_delay(sc);
}
@ -2215,7 +2238,8 @@ urtwn_r88e_power_on(struct urtwn_softc *sc)
return (ETIMEDOUT);
/* Enable LDO normal mode. */
urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10);
urtwn_write_1(sc, R92C_LPLDO_CTRL,
urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10);
/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
urtwn_write_2(sc, R92C_CR, 0);
@ -2547,7 +2571,6 @@ urtwn_r88e_dma_init(struct urtwn_softc *sc)
return (EIO);
/* Set number of pages for normal priority queue. */
urtwn_write_2(sc, R92C_RQPN_NPQ, 0);
urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d);
urtwn_write_4(sc, R92C_RQPN, 0x808e000d);
@ -3366,16 +3389,17 @@ urtwn_init_locked(void *arg)
urtwn_write_1(sc, R92C_TRXDMA_CTRL,
urtwn_read_1(sc, R92C_TRXDMA_CTRL) |
R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
R92C_USB_SPECIAL_OPTION_AGG_EN);
urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
if (sc->chip & URTWN_CHIP_88E)
urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
else
else {
urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
urtwn_write_1(sc, R92C_USB_AGG_TH, 8);
urtwn_write_1(sc, R92C_USB_AGG_TO, 6);
urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
R92C_USB_SPECIAL_OPTION_AGG_EN);
urtwn_write_1(sc, R92C_USB_AGG_TH, 8);
urtwn_write_1(sc, R92C_USB_AGG_TO, 6);
}
/* Initialize beacon parameters. */
urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010);