This patch adds the feature to provide PCI information via IOCTL query.
Reviewed by: ambrisko MFC after: 2 weeks Sponsored by: AVAGO Technologies
This commit is contained in:
kadesai
parent
6b7074e362
commit
89cb6b04b0
@ -87,6 +87,8 @@ mrsas_get_ctrl_info(struct mrsas_softc *sc,
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static int
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mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc,
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struct mrsas_mfi_cmd *cmd_to_abort);
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static struct mrsas_softc *mrsas_get_softc_instance(struct cdev *dev,
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u_long cmd, caddr_t arg);
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u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset);
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u_int8_t
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mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
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@ -1231,6 +1233,39 @@ mrsas_resume(device_t dev)
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return (0);
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}
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/**
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* mrsas_get_softc_instance: Find softc instance based on cmd type
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*
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* This function will return softc instance based on cmd type.
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* In some case, application fire ioctl on required management instance and
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* do not provide host_no. Use cdev->si_drv1 to get softc instance for those
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* case, else get the softc instance from host_no provided by application in
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* user data.
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*/
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static struct mrsas_softc *
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mrsas_get_softc_instance(struct cdev *dev, u_long cmd, caddr_t arg)
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{
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struct mrsas_softc *sc = NULL;
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struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg;
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if (cmd == MRSAS_IOC_GET_PCI_INFO){
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sc = dev->si_drv1;
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} else {
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/* get the Host number & the softc from data sent by the Application */
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sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no];
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if ((user_ioc->host_no >= mrsas_mgmt_info.max_index) || (sc == NULL)) {
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if (sc == NULL)
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mrsas_dprint(sc, MRSAS_FAULT,
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"There is no Controller number %d .\n", user_ioc->host_no);
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else
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mrsas_dprint(sc, MRSAS_FAULT,
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"Invalid Controller number %d .\n", user_ioc->host_no);
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}
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}
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return sc;
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}
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/*
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* mrsas_ioctl: IOCtl commands entry point.
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*
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@ -1243,19 +1278,12 @@ mrsas_ioctl(struct cdev *dev, u_long cmd, caddr_t arg, int flag,
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{
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struct mrsas_softc *sc;
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int ret = 0, i = 0;
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MRSAS_DRV_PCI_INFORMATION *pciDrvInfo;
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struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg;
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/* get the Host number & the softc from data sent by the Application */
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sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no];
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if ((mrsas_mgmt_info.max_index == user_ioc->host_no) || (sc == NULL)) {
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printf("Please check the controller number\n");
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if (sc == NULL)
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printf("There is NO such Host no. %d\n", user_ioc->host_no);
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sc = mrsas_get_softc_instance(dev, cmd, arg);
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if (!sc)
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return ENOENT;
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}
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if (sc->remove_in_progress) {
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mrsas_dprint(sc, MRSAS_INFO,
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"Driver remove or shutdown called.\n");
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@ -1299,6 +1327,22 @@ mrsas_ioctl(struct cdev *dev, u_long cmd, caddr_t arg, int flag,
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case MRSAS_IOC_SCAN_BUS:
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ret = mrsas_bus_scan(sc);
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break;
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case MRSAS_IOC_GET_PCI_INFO:
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pciDrvInfo = (MRSAS_DRV_PCI_INFORMATION *)arg;
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memset (pciDrvInfo, 0, sizeof(MRSAS_DRV_PCI_INFORMATION));
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pciDrvInfo->busNumber = pci_get_bus(sc->mrsas_dev);
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pciDrvInfo->deviceNumber = pci_get_slot(sc->mrsas_dev);
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pciDrvInfo->functionNumber = pci_get_function(sc->mrsas_dev);
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pciDrvInfo->domainID = pci_get_domain(sc->mrsas_dev);
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mrsas_dprint (sc, MRSAS_INFO, "pci bus no: %d,"
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"pci device no: %d, pci function no: %d,"
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"pci domain ID: %d\n",
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pciDrvInfo->busNumber, pciDrvInfo->deviceNumber,
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pciDrvInfo->functionNumber, pciDrvInfo->domainID);
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ret = 0;
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break;
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default:
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mrsas_dprint(sc, MRSAS_TRACE, "IOCTL command 0x%lx is not handled\n", cmd);
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ret = ENOENT;
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@ -2413,6 +2413,167 @@ struct mrsas_mgmt_info {
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int max_index;
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};
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#define PCI_TYPE0_ADDRESSES 6
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#define PCI_TYPE1_ADDRESSES 2
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#define PCI_TYPE2_ADDRESSES 5
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typedef struct _MRSAS_DRV_PCI_COMMON_HEADER
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{
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u_int16_t vendorID; // (ro)
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u_int16_t deviceID; // (ro)
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u_int16_t command; // Device control
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u_int16_t status;
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u_int8_t revisionID; // (ro)
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u_int8_t progIf; // (ro)
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u_int8_t subClass; // (ro)
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u_int8_t baseClass; // (ro)
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u_int8_t cacheLineSize; // (ro+)
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u_int8_t latencyTimer; // (ro+)
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u_int8_t headerType; // (ro)
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u_int8_t bist; // Built in self test
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union
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{
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struct _MRSAS_DRV_PCI_HEADER_TYPE_0
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{
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u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
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u_int32_t cis;
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u_int16_t subVendorID;
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u_int16_t subSystemID;
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u_int32_t romBaseAddress;
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u_int8_t capabilitiesPtr;
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u_int8_t reserved1[3];
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u_int32_t reserved2;
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u_int8_t interruptLine;
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u_int8_t interruptPin; // (ro)
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u_int8_t minimumGrant; // (ro)
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u_int8_t maximumLatency; // (ro)
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} type0;
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/*
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* PCI to PCI Bridge
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*/
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struct _MRSAS_DRV_PCI_HEADER_TYPE_1
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{
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u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
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u_int8_t primaryBus;
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u_int8_t secondaryBus;
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u_int8_t subordinateBus;
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u_int8_t secondaryLatency;
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u_int8_t ioBase;
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u_int8_t ioLimit;
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u_int16_t secondaryStatus;
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u_int16_t memoryBase;
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u_int16_t memoryLimit;
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u_int16_t prefetchBase;
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u_int16_t prefetchLimit;
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u_int32_t prefetchBaseUpper32;
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u_int32_t prefetchLimitUpper32;
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u_int16_t ioBaseUpper16;
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u_int16_t ioLimitUpper16;
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u_int8_t capabilitiesPtr;
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u_int8_t reserved1[3];
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u_int32_t romBaseAddress;
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u_int8_t interruptLine;
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u_int8_t interruptPin;
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u_int16_t bridgeControl;
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} type1;
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/*
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* PCI to CARDBUS Bridge
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*/
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struct _MRSAS_DRV_PCI_HEADER_TYPE_2
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{
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u_int32_t socketRegistersBaseAddress;
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u_int8_t capabilitiesPtr;
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u_int8_t reserved;
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u_int16_t secondaryStatus;
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u_int8_t primaryBus;
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u_int8_t secondaryBus;
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u_int8_t subordinateBus;
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u_int8_t secondaryLatency;
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struct
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{
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u_int32_t base;
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u_int32_t limit;
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} range[PCI_TYPE2_ADDRESSES-1];
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u_int8_t interruptLine;
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u_int8_t interruptPin;
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u_int16_t bridgeControl;
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} type2;
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} u;
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} MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
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#define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes
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typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY
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{
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union
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{
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struct
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{
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u_int32_t linkSpeed :4;
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u_int32_t linkWidth :6;
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u_int32_t aspmSupport :2;
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u_int32_t losExitLatency :3;
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u_int32_t l1ExitLatency :3;
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u_int32_t rsvdp :6;
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u_int32_t portNumber :8;
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}bits;
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u_int32_t asUlong;
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}u;
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}MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
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#define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
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typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY
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{
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union
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{
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struct
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{
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u_int16_t linkSpeed :4;
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u_int16_t negotiatedLinkWidth :6;
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u_int16_t linkTrainingError :1;
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u_int16_t linkTraning :1;
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u_int16_t slotClockConfig :1;
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u_int16_t rsvdZ :3;
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}bits;
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u_int16_t asUshort;
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}u;
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u_int16_t reserved;
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} MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
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#define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
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typedef struct _MRSAS_DRV_PCI_CAPABILITIES
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{
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MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
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MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
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}MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
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#define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
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/* PCI information */
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typedef struct _MRSAS_DRV_PCI_INFORMATION
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{
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u_int32_t busNumber;
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u_int8_t deviceNumber;
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u_int8_t functionNumber;
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u_int8_t interruptVector;
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u_int8_t reserved1;
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MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
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MRSAS_DRV_PCI_CAPABILITIES capability;
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u_int32_t domainID;
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u_int8_t reserved2[28];
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}MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
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/*******************************************************************
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* per-instance data
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********************************************************************/
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@ -64,6 +64,7 @@ __FBSDID("$FreeBSD$");
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* into a somewhat unique, 32-bit value.
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*/
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#define MRSAS_IOC_GET_PCI_INFO _IOR('M', 7, MRSAS_DRV_PCI_INFORMATION)
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#define MRSAS_IOC_FIRMWARE_PASS_THROUGH64 _IOWR('M', 1, struct mrsas_iocpacket)
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#ifdef COMPAT_FREEBSD32
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#define MRSAS_IOC_FIRMWARE_PASS_THROUGH32 _IOWR('M', 1, struct mrsas_iocpacket32)
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