Enable and disable the PMC unit at load/unload time, respectively.
MFC after: 3 weeks
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79d6ca331e
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8a00edea58
@ -580,6 +580,7 @@ mpc7xxx_pcpu_init(struct pmc_mdep *md, int cpu)
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/* Clear the MMCRs, and set FC, to disable all PMCs. */
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/* Clear the MMCRs, and set FC, to disable all PMCs. */
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mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE);
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mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE);
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mtspr(SPR_MMCR1, 0);
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mtspr(SPR_MMCR1, 0);
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mtmsr(mfmsr() | PSL_PMM);
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return 0;
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return 0;
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}
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}
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@ -589,10 +590,13 @@ mpc7xxx_pcpu_fini(struct pmc_mdep *md, int cpu)
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{
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{
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uint32_t mmcr0 = mfspr(SPR_MMCR0);
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uint32_t mmcr0 = mfspr(SPR_MMCR0);
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mtmsr(mfmsr() & ~PSL_PMM);
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mmcr0 |= SPR_MMCR0_FC;
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mmcr0 |= SPR_MMCR0_FC;
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mtspr(SPR_MMCR0, mmcr0);
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mtspr(SPR_MMCR0, mmcr0);
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free(powerpc_pcpu[cpu]->pc_ppcpmcs, M_PMC);
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free(powerpc_pcpu[cpu]->pc_ppcpmcs, M_PMC);
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free(powerpc_pcpu[cpu], M_PMC);
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free(powerpc_pcpu[cpu], M_PMC);
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return 0;
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return 0;
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}
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}
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@ -575,6 +575,7 @@ ppc970_pcpu_init(struct pmc_mdep *md, int cpu)
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mtspr(SPR_970MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | SPR_MMCR0_PMC1CE |
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mtspr(SPR_970MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | SPR_MMCR0_PMC1CE |
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SPR_MMCR0_PMCNCE | SPR_970MMCR0_PMC1SEL(0x8) | SPR_970MMCR0_PMC2SEL(0x8));
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SPR_MMCR0_PMCNCE | SPR_970MMCR0_PMC1SEL(0x8) | SPR_970MMCR0_PMC2SEL(0x8));
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mtspr(SPR_970MMCR1, 0x4218420);
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mtspr(SPR_970MMCR1, 0x4218420);
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mtmsr(mfmsr() | PSL_PMM);
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return 0;
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return 0;
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}
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}
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@ -584,11 +585,14 @@ ppc970_pcpu_fini(struct pmc_mdep *md, int cpu)
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{
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{
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register_t mmcr0 = mfspr(SPR_MMCR0);
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register_t mmcr0 = mfspr(SPR_MMCR0);
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mtmsr(mfmsr() & ~PSL_PMM);
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mmcr0 |= SPR_MMCR0_FC;
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mmcr0 |= SPR_MMCR0_FC;
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mmcr0 &= ~SPR_MMCR0_PMXE;
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mmcr0 &= ~SPR_MMCR0_PMXE;
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mtspr(SPR_MMCR0, mmcr0);
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mtspr(SPR_MMCR0, mmcr0);
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free(powerpc_pcpu[cpu]->pc_ppcpmcs, M_PMC);
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free(powerpc_pcpu[cpu]->pc_ppcpmcs, M_PMC);
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free(powerpc_pcpu[cpu], M_PMC);
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free(powerpc_pcpu[cpu], M_PMC);
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return 0;
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return 0;
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}
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}
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