Defragment the transmit mbuf chain only if necessary.
Use a method similar to the if_dwc driver. Use a wmb() before the flags of the first transmit buffer of a frame are written. Group transmit/receive structure members for better cache efficiency. Tested on P1020RDB. TCP transmit throughput increases from 60MiB/s to 90MiB/s. Submitted by: Sebastian Huber <sebastian.huber_AT_embedded-brains.de>
This commit is contained in:
jhibbits
parent
5b67ceb70e
commit
8a34c9b2ca
@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/bus_dma.h>
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#include <sys/endian.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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@ -71,8 +72,8 @@ static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
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bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
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const char *dname);
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static void tsec_dma_ctl(struct tsec_softc *sc, int state);
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static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head,
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int fcb_inserted);
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static void tsec_encap(struct ifnet *ifp, struct tsec_softc *sc,
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struct mbuf *m0, uint16_t fcb_flags, int *start_tx);
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static void tsec_free_dma(struct tsec_softc *sc);
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static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
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static int tsec_ifmedia_upd(struct ifnet *ifp);
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@ -119,8 +120,6 @@ tsec_attach(struct tsec_softc *sc)
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{
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uint8_t hwaddr[ETHER_ADDR_LEN];
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struct ifnet *ifp;
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bus_dmamap_t *map_ptr;
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bus_dmamap_t **map_pptr;
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int error = 0;
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int i;
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@ -175,7 +174,7 @@ tsec_attach(struct tsec_softc *sc)
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filtfunc, filtfuncarg */
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MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
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TSEC_TX_NUM_DESC - 1, /* nsegments */
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TSEC_TX_MAX_DMA_SEGS, /* nsegments */
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MCLBYTES, 0, /* maxsegsz, flags */
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NULL, NULL, /* lockfunc, lockfuncarg */
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&sc->tsec_tx_mtag); /* dmat */
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@ -205,17 +204,15 @@ tsec_attach(struct tsec_softc *sc)
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}
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/* Create TX busdma maps */
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map_ptr = sc->tx_map_data;
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map_pptr = sc->tx_map_unused_data;
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for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
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map_pptr[i] = &map_ptr[i];
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error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]);
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error = bus_dmamap_create(sc->tsec_tx_mtag, 0,
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&sc->tx_bufmap[i].map);
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if (error) {
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device_printf(sc->dev, "failed to init TX ring\n");
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tsec_detach(sc);
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return (ENXIO);
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}
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sc->tx_bufmap[i].map_initialized = 1;
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}
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/* Create RX busdma maps and zero mbuf handlers */
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@ -726,124 +723,135 @@ static void
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tsec_start_locked(struct ifnet *ifp)
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{
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struct tsec_softc *sc;
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struct mbuf *m0, *mtmp;
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struct mbuf *m0;
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struct tsec_tx_fcb *tx_fcb;
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unsigned int queued = 0;
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int csum_flags, fcb_inserted = 0;
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int csum_flags;
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int start_tx;
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uint16_t fcb_flags;
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sc = ifp->if_softc;
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start_tx = 0;
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TSEC_TRANSMIT_LOCK_ASSERT(sc);
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if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
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IFF_DRV_RUNNING)
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return;
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if (sc->tsec_link == 0)
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return;
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bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
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BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
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for (;;) {
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if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) {
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/* No free descriptors */
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ifp->if_drv_flags |= IFF_DRV_OACTIVE;
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break;
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}
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/* Get packet from the queue */
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IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
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if (m0 == NULL)
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break;
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/* Insert TCP/IP Off-load frame control block */
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fcb_flags = 0;
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csum_flags = m0->m_pkthdr.csum_flags;
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if (csum_flags) {
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M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
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if (m0 == NULL)
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break;
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tx_fcb = mtod(m0, struct tsec_tx_fcb *);
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tx_fcb->flags = 0;
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tx_fcb->l3_offset = ETHER_HDR_LEN;
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tx_fcb->l4_offset = sizeof(struct ip);
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if (csum_flags & CSUM_IP)
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tx_fcb->flags |= TSEC_TX_FCB_IP4 |
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fcb_flags |= TSEC_TX_FCB_IP4 |
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TSEC_TX_FCB_CSUM_IP;
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if (csum_flags & CSUM_TCP)
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tx_fcb->flags |= TSEC_TX_FCB_TCP |
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fcb_flags |= TSEC_TX_FCB_TCP |
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TSEC_TX_FCB_CSUM_TCP_UDP;
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if (csum_flags & CSUM_UDP)
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tx_fcb->flags |= TSEC_TX_FCB_UDP |
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fcb_flags |= TSEC_TX_FCB_UDP |
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TSEC_TX_FCB_CSUM_TCP_UDP;
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fcb_inserted = 1;
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tx_fcb = mtod(m0, struct tsec_tx_fcb *);
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tx_fcb->flags = fcb_flags;
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tx_fcb->l3_offset = ETHER_HDR_LEN;
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tx_fcb->l4_offset = sizeof(struct ip);
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}
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mtmp = m_defrag(m0, M_NOWAIT);
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if (mtmp)
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m0 = mtmp;
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if (tsec_encap(sc, m0, fcb_inserted)) {
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IFQ_DRV_PREPEND(&ifp->if_snd, m0);
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ifp->if_drv_flags |= IFF_DRV_OACTIVE;
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break;
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}
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queued++;
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BPF_MTAP(ifp, m0);
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tsec_encap(ifp, sc, m0, fcb_flags, &start_tx);
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}
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bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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if (queued) {
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if (start_tx) {
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/* Enable transmitter and watchdog timer */
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TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
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sc->tsec_watchdog = 5;
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}
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}
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static int
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tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
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static void
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tsec_encap(struct ifnet *ifp, struct tsec_softc *sc, struct mbuf *m0,
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uint16_t fcb_flags, int *start_tx)
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{
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struct tsec_desc *tx_desc = NULL;
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struct ifnet *ifp;
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bus_dma_segment_t segs[TSEC_TX_NUM_DESC];
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bus_dmamap_t *mapp;
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int csum_flag = 0, error, seg, nsegs;
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bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS];
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int error, i, nsegs;
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struct tsec_bufmap *tx_bufmap;
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uint32_t tx_idx;
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uint16_t flags;
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TSEC_TRANSMIT_LOCK_ASSERT(sc);
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ifp = sc->tsec_ifp;
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if (TSEC_FREE_TX_DESC(sc) == 0) {
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/* No free descriptors */
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return (-1);
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}
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/* Fetch unused map */
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mapp = TSEC_ALLOC_TX_MAP(sc);
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tx_idx = sc->tx_idx_head;
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tx_bufmap = &sc->tx_bufmap[tx_idx];
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/* Create mapping in DMA memory */
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error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
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*mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT);
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if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) {
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bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
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TSEC_FREE_TX_MAP(sc, mapp);
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return ((error != 0) ? error : -1);
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error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0,
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segs, &nsegs, BUS_DMA_NOWAIT);
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if (error == EFBIG) {
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/* Too many segments! Defrag and try again. */
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struct mbuf *m = m_defrag(m0, M_NOWAIT);
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if (m == NULL) {
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m_freem(m0);
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return;
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}
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m0 = m;
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error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
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tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
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}
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if (error != 0) {
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/* Give up. */
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m_freem(m0);
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return;
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}
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bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE);
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if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1))
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if_printf(ifp, "TX buffer has %d segments\n", nsegs);
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bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
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BUS_DMASYNC_PREWRITE);
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tx_bufmap->mbuf = m0;
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/*
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* Fill in the TX descriptors back to front so that READY bit in first
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* descriptor is set last.
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*/
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tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1);
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sc->tx_idx_head = tx_idx;
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flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC;
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for (i = nsegs - 1; i >= 0; i--) {
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struct tsec_desc *tx_desc;
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if (fcb_inserted)
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csum_flag = TSEC_TXBD_TOE;
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tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1);
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tx_desc = &sc->tsec_tx_vaddr[tx_idx];
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tx_desc->length = segs[i].ds_len;
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tx_desc->bufptr = segs[i].ds_addr;
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/* Everything is ok, now we can send buffers */
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for (seg = 0; seg < nsegs; seg++) {
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tx_desc = TSEC_GET_CUR_TX_DESC(sc);
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if (i == 0) {
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wmb();
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tx_desc->length = segs[seg].ds_len;
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tx_desc->bufptr = segs[seg].ds_addr;
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if (fcb_flags != 0)
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flags |= TSEC_TXBD_TOE;
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}
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/*
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* Set flags:
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@ -853,17 +861,14 @@ tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted)
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* - transmit the CRC sequence after the last data byte
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* - interrupt after the last buffer
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*/
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tx_desc->flags =
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(tx_desc->flags & TSEC_TXBD_W) |
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((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC |
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((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0);
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tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ?
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TSEC_TXBD_W : 0) | flags;
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flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I);
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}
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/* Save mbuf and DMA mapping for release at later stage */
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TSEC_PUT_TX_MBUF(sc, m0);
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TSEC_PUT_TX_MAP(sc, mapp);
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return (0);
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BPF_MTAP(ifp, m0);
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*start_tx = 1;
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}
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static void
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@ -1174,9 +1179,9 @@ tsec_free_dma(struct tsec_softc *sc)
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/* Free TX maps */
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for (i = 0; i < TSEC_TX_NUM_DESC; i++)
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if (sc->tx_map_data[i] != NULL)
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if (sc->tx_bufmap[i].map_initialized)
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bus_dmamap_destroy(sc->tsec_tx_mtag,
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sc->tx_map_data[i]);
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sc->tx_bufmap[i].map);
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/* Destroy tag for TX mbufs */
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bus_dma_tag_destroy(sc->tsec_tx_mtag);
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@ -1211,8 +1216,6 @@ static void
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tsec_stop(struct tsec_softc *sc)
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{
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struct ifnet *ifp;
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struct mbuf *m0;
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bus_dmamap_t *mapp;
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uint32_t tmpval;
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TSEC_GLOBAL_LOCK_ASSERT(sc);
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@ -1229,16 +1232,15 @@ tsec_stop(struct tsec_softc *sc)
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tsec_dma_ctl(sc, 0);
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/* Remove pending data from TX queue */
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while (!TSEC_EMPTYQ_TX_MBUF(sc)) {
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m0 = TSEC_GET_TX_MBUF(sc);
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mapp = TSEC_GET_TX_MAP(sc);
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bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
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while (sc->tx_idx_tail != sc->tx_idx_head) {
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bus_dmamap_sync(sc->tsec_tx_mtag,
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sc->tx_bufmap[sc->tx_idx_tail].map,
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BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
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TSEC_FREE_TX_MAP(sc, mapp);
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m_freem(m0);
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bus_dmamap_unload(sc->tsec_tx_mtag,
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sc->tx_bufmap[sc->tx_idx_tail].map);
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m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf);
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sc->tx_idx_tail = (sc->tx_idx_tail + 1)
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& (TSEC_TX_NUM_DESC - 1);
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}
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/* Disable RX and TX */
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@ -1362,7 +1364,7 @@ tsec_receive_intr_locked(struct tsec_softc *sc, int count)
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if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
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&rx_data[i].mbuf, &rx_data[i].paddr)) {
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if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
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if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
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/*
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* We ran out of mbufs; didn't consume current
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* descriptor and have to return it to the queue.
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@ -1432,11 +1434,8 @@ tsec_receive_intr(void *arg)
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static void
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tsec_transmit_intr_locked(struct tsec_softc *sc)
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{
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struct tsec_desc *tx_desc;
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struct ifnet *ifp;
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struct mbuf *m0;
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bus_dmamap_t *mapp;
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int send = 0;
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uint32_t tx_idx;
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TSEC_TRANSMIT_LOCK_ASSERT(sc);
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@ -1455,44 +1454,41 @@ tsec_transmit_intr_locked(struct tsec_softc *sc)
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bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
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BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
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while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) {
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tx_desc = TSEC_GET_DIRTY_TX_DESC(sc);
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tx_idx = sc->tx_idx_tail;
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while (tx_idx != sc->tx_idx_head) {
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struct tsec_desc *tx_desc;
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struct tsec_bufmap *tx_bufmap;
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tx_desc = &sc->tsec_tx_vaddr[tx_idx];
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if (tx_desc->flags & TSEC_TXBD_R) {
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TSEC_BACK_DIRTY_TX_DESC(sc);
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break;
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}
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if ((tx_desc->flags & TSEC_TXBD_L) == 0)
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tx_bufmap = &sc->tx_bufmap[tx_idx];
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tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1);
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if (tx_bufmap->mbuf == NULL)
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continue;
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/*
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* This is the last buf in this packet, so unmap and free it.
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*/
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m0 = TSEC_GET_TX_MBUF(sc);
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mapp = TSEC_GET_TX_MAP(sc);
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bus_dmamap_sync(sc->tsec_tx_mtag, *mapp,
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bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
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BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(sc->tsec_tx_mtag, *mapp);
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TSEC_FREE_TX_MAP(sc, mapp);
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m_freem(m0);
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bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map);
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m_freem(tx_bufmap->mbuf);
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tx_bufmap->mbuf = NULL;
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if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
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send = 1;
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}
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sc->tx_idx_tail = tx_idx;
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bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
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BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
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if (send) {
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/* Now send anything that was pending */
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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tsec_start_locked(ifp);
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
||||
tsec_start_locked(ifp);
|
||||
|
||||
/* Stop wathdog if all sent */
|
||||
if (TSEC_EMPTYQ_TX_MBUF(sc))
|
||||
sc->tsec_watchdog = 0;
|
||||
}
|
||||
if (sc->tx_idx_tail == sc->tx_idx_head)
|
||||
sc->tsec_watchdog = 0;
|
||||
}
|
||||
|
||||
void
|
||||
@ -1543,9 +1539,8 @@ tsec_error_intr_locked(struct tsec_softc *sc, int count)
|
||||
TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
|
||||
}
|
||||
|
||||
/* Check receiver errors */
|
||||
/* Check for discarded frame due to a lack of buffers */
|
||||
if (eflags & TSEC_IEVENT_BSY) {
|
||||
if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
|
||||
if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
|
||||
|
||||
/* Get data from RX buffers */
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
|
||||
#define TSEC_RX_NUM_DESC 256
|
||||
#define TSEC_TX_NUM_DESC 256
|
||||
#define TSEC_TX_MAX_DMA_SEGS 8
|
||||
|
||||
/* Interrupt Coalescing types */
|
||||
#define TSEC_IC_RX 0
|
||||
@ -44,6 +45,12 @@
|
||||
#define TSEC_MIN_FRAME_SIZE 64
|
||||
#define TSEC_MAX_FRAME_SIZE 9600
|
||||
|
||||
struct tsec_bufmap {
|
||||
bus_dmamap_t map;
|
||||
int map_initialized;
|
||||
struct mbuf *mbuf;
|
||||
};
|
||||
|
||||
struct tsec_softc {
|
||||
/* XXX MII bus requires that struct ifnet is first!!! */
|
||||
struct ifnet *tsec_ifp;
|
||||
@ -59,16 +66,16 @@ struct tsec_softc {
|
||||
|
||||
bus_dma_tag_t tsec_tx_dtag; /* TX descriptors tag */
|
||||
bus_dmamap_t tsec_tx_dmap; /* TX descriptors map */
|
||||
struct tsec_desc *tsec_tx_vaddr;/* vadress of TX descriptors */
|
||||
uint32_t tsec_tx_raddr; /* real address of TX descriptors */
|
||||
bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */
|
||||
uint32_t tx_idx_head; /* TX head descriptor/bufmap index */
|
||||
uint32_t tx_idx_tail; /* TX tail descriptor/bufmap index */
|
||||
struct tsec_desc *tsec_tx_vaddr;/* virtual address of TX descriptors */
|
||||
struct tsec_bufmap tx_bufmap[TSEC_TX_NUM_DESC];
|
||||
|
||||
bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */
|
||||
bus_dma_tag_t tsec_rx_dtag; /* RX descriptors tag */
|
||||
bus_dmamap_t tsec_rx_dmap; /* RX descriptors map */
|
||||
struct tsec_desc *tsec_rx_vaddr; /* vadress of RX descriptors */
|
||||
uint32_t tsec_rx_raddr; /* real address of RX descriptors */
|
||||
|
||||
bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */
|
||||
bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */
|
||||
|
||||
struct rx_data_type {
|
||||
bus_dmamap_t map; /* mbuf map */
|
||||
@ -76,8 +83,6 @@ struct tsec_softc {
|
||||
uint32_t paddr; /* DMA address of buffer */
|
||||
} rx_data[TSEC_RX_NUM_DESC];
|
||||
|
||||
uint32_t tx_cur_desc_cnt;
|
||||
uint32_t tx_dirty_desc_cnt;
|
||||
uint32_t rx_cur_desc_cnt;
|
||||
|
||||
struct resource *sc_rres; /* register resource */
|
||||
@ -104,24 +109,6 @@ struct tsec_softc {
|
||||
struct callout tsec_callout;
|
||||
int tsec_watchdog;
|
||||
|
||||
/* TX maps */
|
||||
bus_dmamap_t tx_map_data[TSEC_TX_NUM_DESC];
|
||||
|
||||
/* unused TX maps data */
|
||||
uint32_t tx_map_unused_get_cnt;
|
||||
uint32_t tx_map_unused_put_cnt;
|
||||
bus_dmamap_t *tx_map_unused_data[TSEC_TX_NUM_DESC];
|
||||
|
||||
/* used TX maps data */
|
||||
uint32_t tx_map_used_get_cnt;
|
||||
uint32_t tx_map_used_put_cnt;
|
||||
bus_dmamap_t *tx_map_used_data[TSEC_TX_NUM_DESC];
|
||||
|
||||
/* mbufs in TX queue */
|
||||
uint32_t tx_mbuf_used_get_cnt;
|
||||
uint32_t tx_mbuf_used_put_cnt;
|
||||
struct mbuf *tx_mbuf_used_data[TSEC_TX_NUM_DESC];
|
||||
|
||||
/* interrupt coalescing */
|
||||
struct mtx ic_lock;
|
||||
uint32_t rx_ic_time; /* RW, valid values 0..65535 */
|
||||
@ -136,6 +123,9 @@ struct tsec_softc {
|
||||
bus_space_tag_t phy_bst;
|
||||
bus_space_handle_t phy_bsh;
|
||||
int phy_regoff;
|
||||
|
||||
uint32_t tsec_rx_raddr; /* real address of RX descriptors */
|
||||
uint32_t tsec_tx_raddr; /* real address of TX descriptors */
|
||||
};
|
||||
|
||||
/* interface to get/put generic objects */
|
||||
@ -156,75 +146,8 @@ struct tsec_softc {
|
||||
(sc)->count = (wrap) - 1; \
|
||||
} while (0)
|
||||
|
||||
/* TX maps interface */
|
||||
#define TSEC_TX_MAP_CNT_INIT(sc) do { \
|
||||
TSEC_CNT_INIT((sc)->tx_map_unused_get_cnt, TSEC_TX_NUM_DESC); \
|
||||
TSEC_CNT_INIT((sc)->tx_map_unused_put_cnt, TSEC_TX_NUM_DESC); \
|
||||
TSEC_CNT_INIT((sc)->tx_map_used_get_cnt, TSEC_TX_NUM_DESC); \
|
||||
TSEC_CNT_INIT((sc)->tx_map_used_put_cnt, TSEC_TX_NUM_DESC); \
|
||||
} while (0)
|
||||
|
||||
/* interface to get/put unused TX maps */
|
||||
#define TSEC_ALLOC_TX_MAP(sc) \
|
||||
TSEC_GET_GENERIC(sc, tx_map_unused_data, tx_map_unused_get_cnt, \
|
||||
TSEC_TX_NUM_DESC)
|
||||
|
||||
#define TSEC_FREE_TX_MAP(sc, val) \
|
||||
TSEC_PUT_GENERIC(sc, tx_map_unused_data, tx_map_unused_put_cnt, \
|
||||
TSEC_TX_NUM_DESC, val)
|
||||
|
||||
/* interface to get/put used TX maps */
|
||||
#define TSEC_GET_TX_MAP(sc) \
|
||||
TSEC_GET_GENERIC(sc, tx_map_used_data, tx_map_used_get_cnt, \
|
||||
TSEC_TX_NUM_DESC)
|
||||
|
||||
#define TSEC_PUT_TX_MAP(sc, val) \
|
||||
TSEC_PUT_GENERIC(sc, tx_map_used_data, tx_map_used_put_cnt, \
|
||||
TSEC_TX_NUM_DESC, val)
|
||||
|
||||
/* interface to get/put TX mbufs in send queue */
|
||||
#define TSEC_TX_MBUF_CNT_INIT(sc) do { \
|
||||
TSEC_CNT_INIT((sc)->tx_mbuf_used_get_cnt, TSEC_TX_NUM_DESC); \
|
||||
TSEC_CNT_INIT((sc)->tx_mbuf_used_put_cnt, TSEC_TX_NUM_DESC); \
|
||||
} while (0)
|
||||
|
||||
#define TSEC_GET_TX_MBUF(sc) \
|
||||
TSEC_GET_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_get_cnt, \
|
||||
TSEC_TX_NUM_DESC)
|
||||
|
||||
#define TSEC_PUT_TX_MBUF(sc, val) \
|
||||
TSEC_PUT_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_put_cnt, \
|
||||
TSEC_TX_NUM_DESC, val)
|
||||
|
||||
#define TSEC_EMPTYQ_TX_MBUF(sc) \
|
||||
((sc)->tx_mbuf_used_get_cnt == (sc)->tx_mbuf_used_put_cnt)
|
||||
|
||||
/* interface for manage tx tsec_desc */
|
||||
#define TSEC_TX_DESC_CNT_INIT(sc) do { \
|
||||
TSEC_CNT_INIT((sc)->tx_cur_desc_cnt, TSEC_TX_NUM_DESC); \
|
||||
TSEC_CNT_INIT((sc)->tx_dirty_desc_cnt, TSEC_TX_NUM_DESC); \
|
||||
} while (0)
|
||||
|
||||
#define TSEC_GET_CUR_TX_DESC(sc) \
|
||||
&TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_cur_desc_cnt, \
|
||||
TSEC_TX_NUM_DESC)
|
||||
|
||||
#define TSEC_GET_DIRTY_TX_DESC(sc) \
|
||||
&TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_dirty_desc_cnt, \
|
||||
TSEC_TX_NUM_DESC)
|
||||
|
||||
#define TSEC_BACK_DIRTY_TX_DESC(sc) \
|
||||
TSEC_BACK_GENERIC(sc, tx_dirty_desc_cnt, TSEC_TX_NUM_DESC)
|
||||
|
||||
#define TSEC_CUR_DIFF_DIRTY_TX_DESC(sc) \
|
||||
((sc)->tx_cur_desc_cnt != (sc)->tx_dirty_desc_cnt)
|
||||
|
||||
#define TSEC_FREE_TX_DESC(sc) \
|
||||
(((sc)->tx_cur_desc_cnt < (sc)->tx_dirty_desc_cnt) ? \
|
||||
((sc)->tx_dirty_desc_cnt - (sc)->tx_cur_desc_cnt - 1) \
|
||||
: \
|
||||
(TSEC_TX_NUM_DESC - (sc)->tx_cur_desc_cnt \
|
||||
+ (sc)->tx_dirty_desc_cnt - 1))
|
||||
#define TSEC_FREE_TX_DESC(sc) \
|
||||
(((sc)->tx_idx_tail - (sc)->tx_idx_head - 1) & (TSEC_TX_NUM_DESC - 1))
|
||||
|
||||
/* interface for manage rx tsec_desc */
|
||||
#define TSEC_RX_DESC_CNT_INIT(sc) do { \
|
||||
@ -243,9 +166,8 @@ struct tsec_softc {
|
||||
|
||||
/* init all counters (for init only!) */
|
||||
#define TSEC_TX_RX_COUNTERS_INIT(sc) do { \
|
||||
TSEC_TX_MAP_CNT_INIT(sc); \
|
||||
TSEC_TX_MBUF_CNT_INIT(sc); \
|
||||
TSEC_TX_DESC_CNT_INIT(sc); \
|
||||
sc->tx_idx_head = 0; \
|
||||
sc->tx_idx_tail = 0; \
|
||||
TSEC_RX_DESC_CNT_INIT(sc); \
|
||||
} while (0)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user