Add accessors for the ARM CP15 performance monitor registers. Also ensure
that some #ifdef SMP code is also conditional on __ARM_ARCH >= 7; we don't support SMP on armv6, but some drivers and modules are compiled with it forced on via the compiler command line.
This commit is contained in:
Ian Lepore
parent
9cebfb86a7
commit
8a474d01ee
@ -150,6 +150,35 @@ _RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
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_RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
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_RF0(cp15_cbar_get, CP15_CBAR(%0))
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/* Performance Monitor registers */
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#if __ARM_ARCH == 6 && defined(CPU_ARM1176)
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_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
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_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
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#elif __ARM_ARCH > 6
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_RF0(cp15_pmcr_get, CP15_PMCR(%0))
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_WF1(cp15_pmcr_set, CP15_PMCR(%0))
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_RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0))
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_WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0))
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_WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0))
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_RF0(cp15_pmovsr_get, CP15_PMOVSR(%0))
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_WF1(cp15_pmovsr_set, CP15_PMOVSR(%0))
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_WF1(cp15_pmswinc_set, CP15_PMSWINC(%0))
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_RF0(cp15_pmselr_get, CP15_PMSELR(%0))
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_WF1(cp15_pmselr_set, CP15_PMSELR(%0))
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_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0))
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_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0))
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_RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0))
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_WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0))
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_RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0))
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_WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0))
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_RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0))
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_WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0))
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_RF0(cp15_pminten_get, CP15_PMINTENSET(%0))
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_WF1(cp15_pminten_set, CP15_PMINTENSET(%0))
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_WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0))
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#endif
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#undef _FX
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#undef _RF0
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#undef _WF0
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@ -205,14 +234,7 @@ tlb_flush_range_local(vm_offset_t sva, vm_size_t size)
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}
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/* Broadcasting operations. */
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#ifndef SMP
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#define tlb_flush_all() tlb_flush_all_local()
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#define tlb_flush_all_ng() tlb_flush_all_ng_local()
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#define tlb_flush(sva) tlb_flush_local(sva)
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#define tlb_flush_range(sva, size) tlb_flush_range_local(sva, size)
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#else /* SMP */
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#if __ARM_ARCH >= 7 && defined SMP
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static __inline void
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tlb_flush_all(void)
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@ -252,6 +274,13 @@ tlb_flush_range(vm_offset_t sva, vm_size_t size)
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_CP15_TLBIMVAAIS(va);
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dsb();
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}
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#else /* SMP */
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#define tlb_flush_all() tlb_flush_all_local()
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#define tlb_flush_all_ng() tlb_flush_all_ng_local()
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#define tlb_flush(sva) tlb_flush_local(sva)
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#define tlb_flush_range(sva, size) tlb_flush_range_local(sva, size)
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#endif /* SMP */
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/*
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@ -267,14 +296,14 @@ icache_sync(vm_offset_t sva, vm_size_t size)
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dsb();
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for (va = sva; va < eva; va += arm_dcache_align) {
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#ifdef SMP
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#if __ARM_ARCH >= 7 && defined SMP
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_CP15_DCCMVAU(va);
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#else
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_CP15_DCCMVAC(va);
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#endif
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}
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dsb();
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#ifdef SMP
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#if __ARM_ARCH >= 7 && defined SMP
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_CP15_ICIALLUIS();
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#else
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_CP15_ICIALLU();
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@ -287,7 +316,7 @@ icache_sync(vm_offset_t sva, vm_size_t size)
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static __inline void
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icache_inv_all(void)
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{
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#ifdef SMP
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#if __ARM_ARCH >= 7 && defined SMP
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_CP15_ICIALLUIS();
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#else
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_CP15_ICIALLU();
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@ -305,7 +334,7 @@ dcache_wb_pou(vm_offset_t sva, vm_size_t size)
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dsb();
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for (va = sva; va < eva; va += arm_dcache_align) {
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#ifdef SMP
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#if __ARM_ARCH >= 7 && defined SMP
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_CP15_DCCMVAU(va);
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#else
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_CP15_DCCMVAC(va);
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@ -4,9 +4,14 @@
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#ifndef MACHINE_CPU_H
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#define MACHINE_CPU_H
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#include <machine/acle-compat.h>
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#include <machine/armreg.h>
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#include <machine/frame.h>
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#if __ARM_ARCH >= 6
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#include <machine/cpu-v6.h>
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#endif
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void cpu_halt(void);
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void swi_vm(void *);
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@ -14,29 +19,8 @@ void swi_vm(void *);
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static __inline uint64_t
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get_cyclecount(void)
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{
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/* This '#if' asks the question 'Does CP15/SCC include performance counters?' */
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \
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|| defined(CPU_MV_PJ4B) \
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|| defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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uint32_t ccnt;
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uint64_t ccnt64;
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/*
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* Read PMCCNTR. Curses! Its only 32 bits.
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* TODO: Fix this by catching overflow with interrupt?
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*/
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/* The ARMv6 vs ARMv7 divide is going to need a better way of
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* distinguishing between them.
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*/
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
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/* ARMv6 - Earlier model SCCs */
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__asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=r" (ccnt));
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#else
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/* ARMv7 - Later model SCCs */
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__asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
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#endif
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ccnt64 = (uint64_t)ccnt;
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return (ccnt64);
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#if __ARM_ARCH >= 6
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return cp15_pmccntr_get();
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#else /* No performance counters, so use binuptime(9). This is slooooow */
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struct bintime bt;
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@ -29,6 +29,11 @@
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/*
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* Macros to make working with the System Control Registers simpler.
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*
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* Note that when register r0 is hard-coded in these definitions it means the
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* cp15 operation neither reads nor writes the register, and r0 is used only
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* because some syntatically-valid register name has to appear at that point to
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* keep the asm parser happy.
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*/
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#ifndef MACHINE_SYSREG_H
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@ -201,6 +206,26 @@
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#define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */
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#endif
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/*
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* CP15 C9 registers
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*/
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#if __ARM_ARCH == 6 && defined(CPU_ARM1176)
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#define CP15_PMCCNTR(rr) p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */
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#elif __ARM_ARCH > 6
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#define CP15_PMCR(rr) p15, 0, rr, c9, c12, 0 /* Performance Monitor Control Register */
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#define CP15_PMCNTENSET(rr) p15, 0, rr, c9, c12, 1 /* PM Count Enable Set Register */
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#define CP15_PMCNTENCLR(rr) p15, 0, rr, c9, c12, 2 /* PM Count Enable Clear Register */
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#define CP15_PMOVSR(rr) p15, 0, rr, c9, c12, 3 /* PM Overflow Flag Status Register */
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#define CP15_PMSWINC(rr) p15, 0, rr, c9, c12, 4 /* PM Software Increment Register */
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#define CP15_PMSELR(rr) p15, 0, rr, c9, c12, 5 /* PM Event Counter Selection Register */
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#define CP15_PMCCNTR(rr) p15, 0, rr, c9, c13, 0 /* PM Cycle Count Register */
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#define CP15_PMXEVTYPER(rr) p15, 0, rr, c9, c13, 1 /* PM Event Type Select Register */
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#define CP15_PMXEVCNTRR(rr) p15, 0, rr, c9, c13, 2 /* PM Event Count Register */
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#define CP15_PMUSERENR(rr) p15, 0, rr, c9, c14, 0 /* PM User Enable Register */
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#define CP15_PMINTENSET(rr) p15, 0, rr, c9, c14, 1 /* PM Interrupt Enable Set Register */
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#define CP15_PMINTENCLR(rr) p15, 0, rr, c9, c14, 2 /* PM Interrupt Enable Clear Register */
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#endif
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/*
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* CP15 C10 registers
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*/
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