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Use RSTCR for resetting the MPC8572 (the old way does not apply).

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Obtained from:	Freescale, Semihalf
This commit is contained in:
Rafal Jaworowski 2008-04-26 18:03:00 +00:00
parent a1cd472a40
commit 8b79898eb7
2 changed files with 25 additions and 7 deletions
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27
sys/powerpc/mpc85xx/mpc85xx.c
View File

@ -33,10 +33,16 @@ __FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/pio.h>
#include <machine/spr.h>
#include <powerpc/mpc85xx/ocpbus.h>
/*
* MPC85xx system specific routines
*/
@ -44,16 +50,23 @@ __FBSDID("$FreeBSD$");
void
cpu_reset()
{
uint32_t svr = mfsvr();
/* Clear DBCR0, disables debug interrupts and events. */
mtspr(SPR_DBCR0, 0);
__asm volatile("isync");
if (svr == SVR_MPC8572E || svr == SVR_MPC8572)
/* Systems with dedicated reset register */
out32(OCP85XX_RSTCR, 2);
else {
/* Clear DBCR0, disables debug interrupts and events. */
mtspr(SPR_DBCR0, 0);
__asm volatile("isync");
/* Enable Debug Interrupts in MSR. */
mtmsr(mfmsr() | PSL_DE);
/* Enable Debug Interrupts in MSR. */
mtmsr(mfmsr() | PSL_DE);
/* Enable debug interrupts and issue reset. */
mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
}
/* Enable debug interrupts and issue reset. */
mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
printf("Reset failed...\n");
while (1);
}

5
sys/powerpc/mpc85xx/ocpbus.h
View File

@ -51,6 +51,11 @@
#define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
#define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
/*
* Status Registers.
*/
#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
/*
* OCP Bus Definitions
*/