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Add support for the Freescale dTSEC DPAA-based ethernet controller.

Browse Source 
Freescale's QorIQ line includes a new ethernet controller, based on their
Datapath Acceleration Architecture (DPAA).  This uses a combination of a Frame
manager, Buffer manager, and Queue manager to improve performance across all
interfaces by being able to pass data directly between hardware acceleration
interfaces.

As part of this import, Freescale's Netcomm Software (ncsw) driver is imported.
This was an attempt by Freescale to create an OS-agnostic sub-driver for
managing the hardware, using shims to interface to the OS-specific APIs.  This
work was abandoned, and Freescale's primary work is in the Linux driver (dual
BSD/GPL license).  Hence, this was imported directly to sys/contrib, rather than
going through the vendor area.  Going forward, FreeBSD-specific changes may be
made to the ncsw code, diverging from the upstream in potentially incompatible
ways.  An alternative could be to import the Linux driver itself, using the
linuxKPI layer, as that would maintain parity with the vendor-maintained driver.
However, the Linux driver has not been evaluated for reliability yet, and may
have issues with the import, whereas the ncsw-based driver in this commit was
completed by Semihalf 4 years ago, and is very stable.

Other SoC modules based on DPAA, which could be added in the future:
* Security and Encryption engine (SEC4.x, SEC5.x)
* RAID engine

Additional work to be done:
* Implement polling mode
* Test vlan support
* Add support for the Pattern Matching Engine, which can do regular expression
  matching on packets.

This driver has been tested on the P5020 QorIQ SoC.  Others listed in the
dtsec(4) manual page are expected to work as the same DPAA engine is included in
all.

Obtained from:	Semihalf
Relnotes:	Yes
Sponsored by:	Alex Perez/Inertial Computing
This commit is contained in:
jhibbits 2016-02-29 03:38:00 +00:00
parent 52a73c8724
commit 8bf1194fe5
142 changed files with 79377 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

120
share/man/man4/man4.powerpc/dtsec.4 Normal file
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.\"
.\" Copyright (c) 2016 Justin Hibbits
.\"
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE DEVELOPERS ``AS IS'' AND ANY EXPRESS OR
.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
.\" IN NO EVENT SHALL THE DEVELOPERS BE LIABLE FOR ANY DIRECT, INDIRECT,
.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd February 28, 2016
.Dt DTSEC 4
.Os
.Sh NAME
.Nm dtsec
.Nd "Freescale Datapath Acceleration Architecture-based Three-Speed Ethernet Controller device driver"
.Sh SYNOPSIS
To compile this driver into the kernel, place the following lines in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "include ""dpaa/DPAA""
.Cd "options QORIQ_DPAA"
.Cd "device dpaa"
.Cd "device dtsec"
.Cd "device miibus"
.Ed
.Sh DESCRIPTION
The
.Nm
driver provides support for the DPAA-based gigabit Ethernet controller
integrated in some of the Freescale system-on-chip devices.
.Pp
The
.Nm
driver supports the following media types:
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It autoselect
Enable autoselection of the media type and options
.It 10baseT/UTP
Set 10Mbps operation
.It 100baseTX
Set 100Mbps operation
.It 1000baseT
Set 1000baseT operation
.El
.Pp
The
.Nm
driver supports the following media options:
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It full-duplex
Set full duplex operation
.El
.Pp
The
.Nm
driver supports two operating modes:
.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
.It Regular
Normal mode, utilizing the full datapath acceleration, Buffer Manager, and Queue
Manager.
.It Independent
Runs disconnected from the Buffer Manager and Queue Manager.
.El
.Sh HARDWARE
Gigabit Ethernet controllers built into the following Freescale
system-on-chip devices are known to work with the
.Nm
driver:
.Pp
.Bl -bullet -compact
.It
P2041, P3041
.It
P5010, P5020
.El
.Sh SEE ALSO
.Xr altq 4 ,
.Xr arp 4 ,
.Xr miibus 4 ,
.Xr netintro 4 ,
.Xr ng_ether 4 ,
.Xr ifconfig 8
.Sh BUGS
The
.Nm
driver assumes that there is only one Frame Manager, and that dtsec0 controls
the MDIO interface. Though this is the case for the supported devices, other
SoCs with the DPAA controller may not work correctly. Particularly, the P5040
and P4080 SoCs have two frame managers, which breaks this assumption.
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 11.0 .
.Sh AUTHORS
.An -nosplit
The base version of
.Nm
device driver was written by
.An Semihalf .
This manual page was written by
.An Justin Hibbits .

815
sys/contrib/ncsw/Peripherals/BM/bm.c Normal file
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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File bm.c
@Description BM
*//***************************************************************************/
#include "error_ext.h"
#include "std_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "debug_ext.h"
#include "mm_ext.h"
#include "bm.h"
t_Error BM_ConfigException(t_Handle h_Bm, e_BmExceptions exception, bool enable);
/****************************************/
/* static functions */
/****************************************/
static volatile bool blockingFlag = FALSE;
static void BmIpcMsgCompletionCB(t_Handle h_Module,
uint8_t *p_Msg,
uint8_t *p_Reply,
uint32_t replyLength,
t_Error status)
{
SANITY_CHECK_RETURN(h_Module, E_INVALID_HANDLE);
#ifdef DISABLE_SANITY_CHECKS
UNUSED(h_Module);
#endif /* DISABLE_SANITY_CHECKS */
UNUSED(p_Msg);UNUSED(p_Reply);UNUSED(replyLength);UNUSED(status);
blockingFlag = FALSE;
}
static t_Error BmHandleIpcMsgCB(t_Handle h_Bm,
uint8_t *p_Msg,
uint32_t msgLength,
uint8_t *p_Reply,
uint32_t *p_ReplyLength)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
t_BmIpcMsg *p_IpcMsg = (t_BmIpcMsg*)p_Msg;
t_BmIpcReply *p_IpcReply = (t_BmIpcReply *)p_Reply;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR((msgLength >= sizeof(uint32_t)), E_INVALID_VALUE);
#ifdef DISABLE_SANITY_CHECKS
UNUSED(msgLength);
#endif /* DISABLE_SANITY_CHECKS */
ASSERT_COND(p_IpcMsg);
memset(p_IpcReply, 0, (sizeof(uint8_t) * BM_IPC_MAX_REPLY_SIZE));
*p_ReplyLength = 0;
switch(p_IpcMsg->msgId)
{
case (BM_MASTER_IS_ALIVE):
*(uint8_t*)p_IpcReply->replyBody = 1;
*p_ReplyLength = sizeof(uint32_t) + sizeof(uint8_t);
break;
case (BM_SET_POOL_THRESH):
{
t_Error err;
t_BmIpcPoolThreshParams ipcPoolThresh;
memcpy((uint8_t*)&ipcPoolThresh, p_IpcMsg->msgBody, sizeof(t_BmIpcPoolThreshParams));
if ((err = BmSetPoolThresholds(p_Bm,
ipcPoolThresh.bpid,
ipcPoolThresh.thresholds)) != E_OK)
REPORT_ERROR(MINOR, err, NO_MSG);
break;
}
case (BM_UNSET_POOL_THRESH):
{
t_Error err;
t_BmIpcPoolThreshParams ipcPoolThresh;
memcpy((uint8_t*)&ipcPoolThresh, p_IpcMsg->msgBody, sizeof(t_BmIpcPoolThreshParams));
if ((err = BmUnSetPoolThresholds(p_Bm,
ipcPoolThresh.bpid)) != E_OK)
REPORT_ERROR(MINOR, err, NO_MSG);
break;
}
case (BM_GET_COUNTER):
{
t_BmIpcGetCounter ipcCounter;
uint32_t count;
memcpy((uint8_t*)&ipcCounter, p_IpcMsg->msgBody, sizeof(t_BmIpcGetCounter));
count = BmGetCounter(p_Bm,
(e_BmInterModuleCounters)ipcCounter.enumId,
ipcCounter.bpid);
memcpy(p_IpcReply->replyBody, (uint8_t*)&count, sizeof(uint32_t));
*p_ReplyLength = sizeof(uint32_t) + sizeof(uint32_t);
break;
}
case (BM_GET_REVISION):
{
t_BmRevisionInfo revInfo;
t_BmIpcRevisionInfo ipcRevInfo;
p_IpcReply->error = (uint32_t)BmGetRevision(h_Bm, &revInfo);
ipcRevInfo.majorRev = revInfo.majorRev;
ipcRevInfo.minorRev = revInfo.minorRev;
memcpy(p_IpcReply->replyBody, (uint8_t*)&ipcRevInfo, sizeof(t_BmIpcRevisionInfo));
*p_ReplyLength = sizeof(uint32_t) + sizeof(t_BmIpcRevisionInfo);
break;
}
case (BM_FORCE_BPID):
{
t_BmIpcBpidParams ipcBpid;
uint32_t tmp;
memcpy((uint8_t*)&ipcBpid, p_IpcMsg->msgBody, sizeof(t_BmIpcBpidParams));
tmp = BmBpidGet(p_Bm, TRUE, ipcBpid.bpid);
memcpy(p_IpcReply->replyBody, (uint8_t*)&tmp, sizeof(uint32_t));
*p_ReplyLength = sizeof(uint32_t) + sizeof(uint32_t);
break;
}
case (BM_PUT_BPID):
{
t_Error err;
t_BmIpcBpidParams ipcBpid;
memcpy((uint8_t*)&ipcBpid, p_IpcMsg->msgBody, sizeof(t_BmIpcBpidParams));
if ((err = BmBpidPut(p_Bm, ipcBpid.bpid)) != E_OK)
REPORT_ERROR(MINOR, err, NO_MSG);
break;
}
default:
*p_ReplyLength = 0;
RETURN_ERROR(MINOR, E_INVALID_SELECTION, ("command not found!!!"));
}
return E_OK;
}
static t_Error CheckBmParameters(t_Bm *p_Bm)
{
if ((p_Bm->p_BmDriverParams->partBpidBase + p_Bm->p_BmDriverParams->partNumOfPools) > BM_MAX_NUM_OF_POOLS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("partBpidBase+partNumOfPools out of range!!!"));
if (p_Bm->guestId == NCSW_MASTER_ID)
{
if (!p_Bm->p_BmDriverParams->totalNumOfBuffers)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("totalNumOfBuffers must be larger than '0'!!!"));
if (p_Bm->p_BmDriverParams->totalNumOfBuffers > (128*MEGABYTE))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("totalNumOfBuffers must be equal or smaller than 128M!!!"));
if(!p_Bm->f_Exception)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceptions callback not provided"));
}
return E_OK;
}
static __inline__ uint32_t GenerateThresh(uint32_t val, int roundup)
{
uint32_t e = 0; /* co-efficient, exponent */
uint32_t oddbit = 0;
while(val > 0xff) {
oddbit = val & 1;
val >>= 1;
e++;
if(roundup && oddbit)
val++;
}
return (val | (e << 8));
}
static t_Error BmSetPool(t_Handle h_Bm,
uint8_t bpid,
uint32_t swdet,
uint32_t swdxt,
uint32_t hwdet,
uint32_t hwdxt)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(bpid < BM_MAX_NUM_OF_POOLS, E_INVALID_VALUE);
WRITE_UINT32(p_Bm->p_BmRegs->swdet[bpid], GenerateThresh(swdet, 0));
WRITE_UINT32(p_Bm->p_BmRegs->swdxt[bpid], GenerateThresh(swdxt, 1));
WRITE_UINT32(p_Bm->p_BmRegs->hwdet[bpid], GenerateThresh(hwdet, 0));
WRITE_UINT32(p_Bm->p_BmRegs->hwdxt[bpid], GenerateThresh(hwdxt, 1));
return E_OK;
}
/****************************************/
/* Inter-Module functions */
/****************************************/
t_Error BmSetPoolThresholds(t_Handle h_Bm, uint8_t bpid, const uint32_t *thresholds)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(bpid < BM_MAX_NUM_OF_POOLS, E_INVALID_VALUE);
if (p_Bm->guestId == NCSW_MASTER_ID)
{
return BmSetPool(h_Bm,
bpid,
thresholds[0],
thresholds[1],
thresholds[2],
thresholds[3]);
}
else if (p_Bm->h_Session)
{
t_BmIpcMsg msg;
t_BmIpcPoolThreshParams ipcPoolThresh;
t_Error errCode = E_OK;
memset(&msg, 0, sizeof(t_BmIpcMsg));
ipcPoolThresh.bpid = bpid;
memcpy(ipcPoolThresh.thresholds, thresholds, sizeof(uintptr_t) * MAX_DEPLETION_THRESHOLDS);
msg.msgId = BM_SET_POOL_THRESH;
memcpy(msg.msgBody, &ipcPoolThresh, sizeof(t_BmIpcPoolThreshParams));
if ((errCode = XX_IpcSendMessage(p_Bm->h_Session,
(uint8_t*)&msg,
sizeof(msg.msgId) + sizeof(t_BmIpcPoolThreshParams),
NULL,
NULL,
NULL,
NULL)) != E_OK)
RETURN_ERROR(MAJOR, errCode, NO_MSG);
return E_OK;
}
else
RETURN_ERROR(WARNING, E_NOT_SUPPORTED, ("IPC"));
}
t_Error BmUnSetPoolThresholds(t_Handle h_Bm, uint8_t bpid)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(bpid < BM_MAX_NUM_OF_POOLS, E_INVALID_VALUE);
if (p_Bm->guestId == NCSW_MASTER_ID)
{
return BmSetPool(h_Bm,
bpid,
0,
0,
0,
0);
}
else if (p_Bm->h_Session)
{
t_BmIpcMsg msg;
t_BmIpcPoolThreshParams ipcPoolThresh;
t_Error errCode = E_OK;
memset(&msg, 0, sizeof(t_BmIpcMsg));
memset(&ipcPoolThresh, 0, sizeof(t_BmIpcPoolThreshParams));
ipcPoolThresh.bpid = bpid;
msg.msgId = BM_UNSET_POOL_THRESH;
memcpy(msg.msgBody, &ipcPoolThresh, sizeof(t_BmIpcPoolThreshParams));
if ((errCode = XX_IpcSendMessage(p_Bm->h_Session,
(uint8_t*)&msg,
sizeof(msg.msgId) + sizeof(t_BmIpcPoolThreshParams),
NULL,
NULL,
NULL,
NULL)) != E_OK)
RETURN_ERROR(MAJOR, errCode, NO_MSG);
return E_OK;
}
else
RETURN_ERROR(WARNING, E_NOT_SUPPORTED, ("IPC"));
}
uint32_t BmGetCounter(t_Handle h_Bm, e_BmInterModuleCounters counter, uint8_t bpid)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
SANITY_CHECK_RETURN_VALUE(p_Bm, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(bpid < BM_MAX_NUM_OF_POOLS, E_INVALID_VALUE, 0);
SANITY_CHECK_RETURN_VALUE((((p_Bm->guestId == NCSW_MASTER_ID) && p_Bm->p_BmRegs) ||
(p_Bm->guestId != NCSW_MASTER_ID)), E_INVALID_STATE, 0);
if ((p_Bm->guestId == NCSW_MASTER_ID) ||
(!p_Bm->h_Session && p_Bm->p_BmRegs))
{
switch(counter)
{
case(e_BM_IM_COUNTERS_POOL_CONTENT):
return GET_UINT32(p_Bm->p_BmRegs->content[bpid]);
case(e_BM_IM_COUNTERS_POOL_SW_DEPLETION):
return GET_UINT32(p_Bm->p_BmRegs->sdcnt[bpid]);
case(e_BM_IM_COUNTERS_POOL_HW_DEPLETION):
return GET_UINT32(p_Bm->p_BmRegs->hdcnt[bpid]);
case(e_BM_IM_COUNTERS_FBPR):
return GET_UINT32(p_Bm->p_BmRegs->fbpr_fpc);
default:
break;
}
/* should never get here */
ASSERT_COND(FALSE);
}
else if (p_Bm->h_Session)
{
t_BmIpcMsg msg;
t_BmIpcReply reply;
t_BmIpcGetCounter ipcCounter;
uint32_t replyLength;
uint32_t count;
t_Error errCode = E_OK;
memset(&msg, 0, sizeof(t_BmIpcMsg));
memset(&reply, 0, sizeof(t_BmIpcReply));
ipcCounter.bpid = bpid;
ipcCounter.enumId = (uint32_t)counter;
msg.msgId = BM_GET_COUNTER;
memcpy(msg.msgBody, &ipcCounter, sizeof(t_BmIpcGetCounter));
replyLength = sizeof(uint32_t) + sizeof(uint32_t);
if ((errCode = XX_IpcSendMessage(p_Bm->h_Session,
(uint8_t*)&msg,
sizeof(msg.msgId) + sizeof(t_BmIpcGetCounter),
(uint8_t*)&reply,
&replyLength,
NULL,
NULL)) != E_OK)
REPORT_ERROR(MAJOR, errCode, NO_MSG);
if (replyLength != (sizeof(uint32_t) + sizeof(uint32_t)))
{
REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch"));
errCode = E_INVALID_VALUE;
}
if (errCode == E_OK)
{
memcpy((uint8_t*)&count, reply.replyBody, sizeof(uint32_t));
return count;
}
}
else
REPORT_ERROR(WARNING, E_NOT_SUPPORTED,
("In 'guest', either IPC or 'baseAddress' is required!"));
return 0;
}
t_Error BmGetRevision(t_Handle h_Bm, t_BmRevisionInfo *p_BmRevisionInfo)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
uint32_t tmpReg;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BmRevisionInfo, E_NULL_POINTER);
SANITY_CHECK_RETURN_ERROR((((p_Bm->guestId == NCSW_MASTER_ID) && p_Bm->p_BmRegs) ||
(p_Bm->guestId != NCSW_MASTER_ID)), E_INVALID_STATE);
if ((p_Bm->guestId == NCSW_MASTER_ID) ||
(!p_Bm->h_Session && p_Bm->p_BmRegs))
{
/* read revision register 1 */
tmpReg = GET_UINT32(p_Bm->p_BmRegs->ip_rev_1);
p_BmRevisionInfo->majorRev = (uint8_t)((tmpReg & REV1_MAJOR_MASK) >> REV1_MAJOR_SHIFT);
p_BmRevisionInfo->minorRev = (uint8_t)((tmpReg & REV1_MINOR_MASK) >> REV1_MINOR_SHIFT);
}
else if (p_Bm->h_Session)
{
t_BmIpcMsg msg;
t_BmIpcReply reply;
t_BmIpcRevisionInfo ipcRevInfo;
uint32_t replyLength;
t_Error errCode = E_OK;
memset(&msg, 0, sizeof(t_BmIpcMsg));
memset(&reply, 0, sizeof(t_BmIpcReply));
msg.msgId = BM_GET_REVISION;
replyLength = sizeof(uint32_t) + sizeof(t_BmIpcRevisionInfo);
if ((errCode = XX_IpcSendMessage(p_Bm->h_Session,
(uint8_t*)&msg,
sizeof(msg.msgId),
(uint8_t*)&reply,
&replyLength,
NULL,
NULL)) != E_OK)
RETURN_ERROR(MAJOR, errCode, NO_MSG);
if (replyLength != (sizeof(uint32_t) + sizeof(t_BmIpcRevisionInfo)))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch"));
memcpy((uint8_t*)&ipcRevInfo, reply.replyBody, sizeof(t_BmIpcRevisionInfo));
p_BmRevisionInfo->majorRev = ipcRevInfo.majorRev;
p_BmRevisionInfo->minorRev = ipcRevInfo.minorRev;
return (t_Error)(reply.error);
}
else
RETURN_ERROR(WARNING, E_NOT_SUPPORTED,
("In 'guest', either IPC or 'baseAddress' is required!"));
return E_OK;
}
static void FreeInitResources(t_Bm *p_Bm)
{
if (p_Bm->p_FbprBase)
XX_FreeSmart(p_Bm->p_FbprBase);
if (p_Bm->h_Session)
XX_IpcFreeSession(p_Bm->h_Session);
if (p_Bm->h_BpidMm)
MM_Free(p_Bm->h_BpidMm);
}
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle BM_Config(t_BmParam *p_BmParam)
{
t_Bm *p_Bm;
SANITY_CHECK_RETURN_VALUE(p_BmParam, E_INVALID_HANDLE, NULL);
p_Bm = (t_Bm *)XX_Malloc(sizeof(t_Bm));
if (!p_Bm)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("BM obj!!!"));
return NULL;
}
memset(p_Bm, 0, sizeof(t_Bm));
p_Bm->p_BmDriverParams = (t_BmDriverParams *)XX_Malloc(sizeof(t_BmDriverParams));
if (!p_Bm->p_BmDriverParams)
{
XX_Free(p_Bm);
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Bm driver parameters"));
return NULL;
}
memset(p_Bm->p_BmDriverParams, 0, sizeof(t_BmDriverParams));
p_Bm->guestId = p_BmParam->guestId;
p_Bm->p_BmDriverParams->partNumOfPools = p_BmParam->partNumOfPools;
p_Bm->p_BmDriverParams->partBpidBase = p_BmParam->partBpidBase;
p_Bm->p_BmRegs = (t_BmRegs *)UINT_TO_PTR(p_BmParam->baseAddress);
if (p_Bm->guestId == NCSW_MASTER_ID)
{
p_Bm->exceptions = DEFAULT_exceptions;
p_Bm->f_Exception = p_BmParam->f_Exception;
p_Bm->h_App = p_BmParam->h_App;
p_Bm->errIrq = p_BmParam->errIrq;
p_Bm->p_BmDriverParams->totalNumOfBuffers = p_BmParam->totalNumOfBuffers;
p_Bm->p_BmDriverParams->fbprMemPartitionId = p_BmParam->fbprMemPartitionId;
p_Bm->p_BmDriverParams->fbprThreshold = DEFAULT_fbprThreshold;
p_Bm->p_BmDriverParams->liodn = p_BmParam->liodn;
}
/* build the BM partition IPC address */
memset(p_Bm->moduleName, 0, MODULE_NAME_SIZE);
if(Sprint (p_Bm->moduleName, "BM_0_%d",p_Bm->guestId) != (p_Bm->guestId<10 ? 6:7))
{
XX_Free(p_Bm->p_BmDriverParams);
XX_Free(p_Bm);
REPORT_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed"));
return NULL;
}
return p_Bm;
}
t_Error BM_Init(t_Handle h_Bm)
{
t_Bm *p_Bm = (t_Bm *)h_Bm;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Bm->p_BmDriverParams, E_INVALID_HANDLE);
CHECK_INIT_PARAMETERS(p_Bm, CheckBmParameters);
if (p_Bm->p_BmDriverParams->partNumOfPools)
if (MM_Init(&p_Bm->h_BpidMm, p_Bm->p_BmDriverParams->partBpidBase, p_Bm->p_BmDriverParams->partNumOfPools) != E_OK)
{
FreeInitResources(p_Bm);
RETURN_ERROR(MAJOR, E_INVALID_HANDLE, ("BM-BPIDS-MEM partition!!!"));
}
if (p_Bm->guestId == NCSW_MASTER_ID)
{
uint64_t phyAddr;
t_BmRevisionInfo revInfo;
uint32_t dsSize, exp;
BmGetRevision(p_Bm, &revInfo);
DBG(TRACE, ("Bman ver:%02x,%02x", revInfo.majorRev, revInfo.minorRev));
WRITE_UINT32(p_Bm->p_BmRegs->liodnr, (uint16_t)p_Bm->p_BmDriverParams->liodn);
/* FBPR memory */
dsSize = (uint32_t)(p_Bm->p_BmDriverParams->totalNumOfBuffers * (FBPR_ENTRY_SIZE / 8));
LOG2(dsSize, exp);
if (!POWER_OF_2(dsSize)) (exp++);
dsSize = (uint32_t)(1 << exp);
if (dsSize < (4*KILOBYTE))
{
dsSize = (4*KILOBYTE);
LOG2(dsSize, exp);
}
p_Bm->p_FbprBase = XX_MallocSmart(dsSize, (int)p_Bm->p_BmDriverParams->fbprMemPartitionId, dsSize);
if (!p_Bm->p_FbprBase)
{
FreeInitResources(p_Bm);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("FBPR obj!!!"));
}
phyAddr = XX_VirtToPhys(p_Bm->p_FbprBase);
WRITE_UINT32(p_Bm->p_BmRegs->fbpr_bare, ((uint32_t)(phyAddr >> 32) & 0xffff));
WRITE_UINT32(p_Bm->p_BmRegs->fbpr_bar, (uint32_t)phyAddr);
WRITE_UINT32(p_Bm->p_BmRegs->fbpr_ar, (exp - 1));
WRITE_UINT32(p_Bm->p_BmRegs->fbpr_fp_lwit, p_Bm->p_BmDriverParams->fbprThreshold);
WRITE_UINT32(p_Bm->p_BmRegs->err_isr, p_Bm->exceptions);
WRITE_UINT32(p_Bm->p_BmRegs->err_ier, p_Bm->exceptions);
WRITE_UINT32(p_Bm->p_BmRegs->err_isdr, 0x0);
if (p_Bm->errIrq != NO_IRQ)
{
XX_SetIntr(p_Bm->errIrq, BM_ErrorIsr, p_Bm);
XX_EnableIntr(p_Bm->errIrq);
}
if ((err = XX_IpcRegisterMsgHandler(p_Bm->moduleName, BmHandleIpcMsgCB, p_Bm, BM_IPC_MAX_REPLY_SIZE)) != E_OK)
{
FreeInitResources(p_Bm);
RETURN_ERROR(MAJOR, err, NO_MSG);
}
}
else /* guest mode */
{
char masterModuleName[MODULE_NAME_SIZE];
memset(masterModuleName, 0, MODULE_NAME_SIZE);
if(Sprint (masterModuleName, "BM_0_%d", NCSW_MASTER_ID) != (NCSW_MASTER_ID<10 ? 6:7))
{
FreeInitResources(p_Bm);
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Sprint failed"));
}
p_Bm->h_Session = XX_IpcInitSession(masterModuleName, p_Bm->moduleName);
if (p_Bm->h_Session)
{
t_BmIpcMsg msg;
uint8_t isMasterAlive = 0;
t_BmIpcReply reply;
uint32_t replyLength;
memset(&msg, 0, sizeof(t_BmIpcMsg));
memset(&reply, 0, sizeof(t_BmIpcReply));
msg.msgId = BM_MASTER_IS_ALIVE;
replyLength = sizeof(uint32_t) + sizeof(uint8_t);
do
{
blockingFlag = TRUE;
if ((err = XX_IpcSendMessage(p_Bm->h_Session,
(uint8_t*)&msg,
sizeof(msg.msgId),
(uint8_t*)&reply,
&replyLength,
BmIpcMsgCompletionCB,
p_Bm)) != E_OK)
REPORT_ERROR(MAJOR, err, NO_MSG);
while(blockingFlag) ;
if(replyLength != (sizeof(uint32_t) + sizeof(uint8_t)))
REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch"));
isMasterAlive = *(uint8_t*)(reply.replyBody);
} while (!isMasterAlive);
}
}
XX_Free(p_Bm->p_BmDriverParams);
p_Bm->p_BmDriverParams = NULL;
return E_OK;
}
t_Error BM_Free(t_Handle h_Bm)
{
t_Bm *p_Bm = (t_Bm *)h_Bm;
if (!p_Bm)
return ERROR_CODE(E_INVALID_HANDLE);
if (p_Bm->guestId == NCSW_MASTER_ID)
{
XX_IpcUnregisterMsgHandler(p_Bm->moduleName);
if (p_Bm->errIrq != NO_IRQ)
{
XX_DisableIntr(p_Bm->errIrq);
XX_FreeIntr(p_Bm->errIrq);
}
}
FreeInitResources(p_Bm);
if(p_Bm->p_BmDriverParams)
XX_Free(p_Bm->p_BmDriverParams);
XX_Free(p_Bm);
return E_OK;
}
t_Error BM_ConfigException(t_Handle h_Bm, e_BmExceptions exception, bool enable)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
uint32_t bitMask = 0;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Bm->p_BmDriverParams, E_INVALID_HANDLE);
GET_EXCEPTION_FLAG(bitMask, exception);
if(bitMask)
{
if (enable)
p_Bm->exceptions |= bitMask;
else
p_Bm->exceptions &= ~bitMask;
}
else
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
return E_OK;
}
t_Error BM_ConfigFbprThreshold(t_Handle h_Bm, uint32_t threshold)
{
t_Bm *p_Bm = (t_Bm *)h_Bm;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Bm->p_BmDriverParams, E_INVALID_HANDLE);
p_Bm->p_BmDriverParams->fbprThreshold = threshold;
return E_OK;
}
void BM_ErrorIsr(t_Handle h_Bm)
{
t_Bm *p_Bm = (t_Bm *)h_Bm;
uint32_t tmpReg;
SANITY_CHECK_RETURN(p_Bm, E_INVALID_HANDLE);
if (p_Bm->guestId != NCSW_MASTER_ID)
{
REPORT_ERROR(WARNING, E_INVALID_OPERATION, ("Master Only"));
return;
}
tmpReg = GET_UINT32(p_Bm->p_BmRegs->err_isr);
tmpReg &= GET_UINT32(p_Bm->p_BmRegs->err_ier);
WRITE_UINT32(p_Bm->p_BmRegs->err_isr, tmpReg);
if (tmpReg & BM_EX_INVALID_COMMAND)
p_Bm->f_Exception(p_Bm->h_App, e_BM_EX_INVALID_COMMAND);
if (tmpReg & BM_EX_FBPR_THRESHOLD)
p_Bm->f_Exception(p_Bm->h_App, e_BM_EX_FBPR_THRESHOLD);
if (tmpReg & BM_EX_MULTI_ECC)
p_Bm->f_Exception(p_Bm->h_App, e_BM_EX_MULTI_ECC);
if (tmpReg & BM_EX_SINGLE_ECC)
p_Bm->f_Exception(p_Bm->h_App, e_BM_EX_SINGLE_ECC);
}
uint32_t BM_GetCounter(t_Handle h_Bm, e_BmCounters counter)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
SANITY_CHECK_RETURN_VALUE(p_Bm, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_Bm->p_BmDriverParams, E_INVALID_STATE, 0);
switch(counter)
{
case(e_BM_COUNTERS_FBPR):
return BmGetCounter(p_Bm, e_BM_IM_COUNTERS_FBPR, 0);
default:
break;
}
/* should never get here */
ASSERT_COND(FALSE);
return 0;
}
t_Error BM_SetException(t_Handle h_Bm, e_BmExceptions exception, bool enable)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
uint32_t tmpReg, bitMask = 0;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
if (p_Bm->guestId != NCSW_MASTER_ID)
RETURN_ERROR(WARNING, E_INVALID_OPERATION, ("Master Only"));
BM_ConfigException(p_Bm, exception, enable);
tmpReg = GET_UINT32(p_Bm->p_BmRegs->err_ier);
if(enable)
tmpReg |= bitMask;
else
tmpReg &= ~bitMask;
WRITE_UINT32(p_Bm->p_BmRegs->err_ier, tmpReg);
return E_OK;
}
t_Error BM_GetRevision(t_Handle h_Bm, t_BmRevisionInfo *p_BmRevisionInfo)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BmRevisionInfo, E_NULL_POINTER);
return BmGetRevision(p_Bm, p_BmRevisionInfo);
}
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
t_Error BM_DumpRegs(t_Handle h_Bm)
{
t_Bm *p_Bm = (t_Bm *)h_Bm;
DECLARE_DUMP;
if (p_Bm->guestId != NCSW_MASTER_ID)
RETURN_ERROR(WARNING, E_INVALID_OPERATION, ("Master Only"));
SANITY_CHECK_RETURN_ERROR(p_Bm, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Bm->p_BmDriverParams, E_INVALID_STATE);
DUMP_SUBTITLE(("\n"));
DUMP_TITLE(p_Bm->p_BmRegs, ("BmRegs Regs"));
DUMP_ARR(p_Bm->p_BmRegs, swdet);
DUMP_ARR(p_Bm->p_BmRegs, hwdet);
DUMP_ARR(p_Bm->p_BmRegs, swdxt);
DUMP_ARR(p_Bm->p_BmRegs, hwdxt);
DUMP_ARR(p_Bm->p_BmRegs, sdcnt);
DUMP_ARR(p_Bm->p_BmRegs, hdcnt);
DUMP_ARR(p_Bm->p_BmRegs, content);
DUMP_ARR(p_Bm->p_BmRegs, hdptr);
DUMP_VAR(p_Bm->p_BmRegs,fbpr_fpc);
DUMP_VAR(p_Bm->p_BmRegs,fbpr_fp_lwit);
DUMP_ARR(p_Bm->p_BmRegs, cmd_pm_cfg);
DUMP_ARR(p_Bm->p_BmRegs, fl_pm_cfg);
DUMP_VAR(p_Bm->p_BmRegs, ecsr);
DUMP_VAR(p_Bm->p_BmRegs, ecir);
DUMP_VAR(p_Bm->p_BmRegs, eadr);
DUMP_ARR(p_Bm->p_BmRegs, edata);
DUMP_VAR(p_Bm->p_BmRegs,sbet);
DUMP_VAR(p_Bm->p_BmRegs,efcr);
DUMP_VAR(p_Bm->p_BmRegs,efar);
DUMP_VAR(p_Bm->p_BmRegs,sbec0);
DUMP_VAR(p_Bm->p_BmRegs,sbec1);
DUMP_VAR(p_Bm->p_BmRegs,ip_rev_1);
DUMP_VAR(p_Bm->p_BmRegs,ip_rev_2);
DUMP_VAR(p_Bm->p_BmRegs,fbpr_bare);
DUMP_VAR(p_Bm->p_BmRegs,fbpr_bar);
DUMP_VAR(p_Bm->p_BmRegs,fbpr_ar);
DUMP_VAR(p_Bm->p_BmRegs,srcidr);
DUMP_VAR(p_Bm->p_BmRegs,liodnr);
DUMP_VAR(p_Bm->p_BmRegs,err_isr);
DUMP_VAR(p_Bm->p_BmRegs,err_ier);
DUMP_VAR(p_Bm->p_BmRegs,err_isdr);
DUMP_VAR(p_Bm->p_BmRegs,err_iir);
DUMP_VAR(p_Bm->p_BmRegs,err_ifr);
return E_OK;
}
#endif /* (defined(DEBUG_ERRORS) && ... */

453
sys/contrib/ncsw/Peripherals/BM/bm.h Normal file
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@ -0,0 +1,453 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File bm.h
@Description BM header
*//***************************************************************************/
#ifndef __BM_H
#define __BM_H
#include "bm_ext.h"
#include "mm_ext.h"
#include "bman_private.h"
#include "bm_ipc.h"
#define __ERR_MODULE__ MODULE_BM
#define BM_NUM_OF_POOLS 64
#define BM_NUM_OF_PM 8
/**************************************************************************//**
@Description Exceptions
*//***************************************************************************/
#define BM_EX_INVALID_COMMAND 0x00000010
#define BM_EX_FBPR_THRESHOLD 0x00000008
#define BM_EX_MULTI_ECC 0x00000004
#define BM_EX_SINGLE_ECC 0x00000002
#define BM_EX_POOLS_AVAIL_STATE 0x00000001
#define GET_EXCEPTION_FLAG(bitMask, exception) \
switch(exception){ \
case e_BM_EX_INVALID_COMMAND: \
bitMask = BM_EX_INVALID_COMMAND; break; \
case e_BM_EX_FBPR_THRESHOLD: \
bitMask = BM_EX_FBPR_THRESHOLD; break; \
case e_BM_EX_SINGLE_ECC: \
bitMask = BM_EX_SINGLE_ECC; break; \
case e_BM_EX_MULTI_ECC: \
bitMask = BM_EX_MULTI_ECC; break; \
default: bitMask = 0;break; \
}
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
/* BM defaults */
#define DEFAULT_exceptions (BM_EX_INVALID_COMMAND |\
BM_EX_FBPR_THRESHOLD |\
BM_EX_MULTI_ECC |\
BM_EX_SINGLE_ECC )
#define DEFAULT_fbprThreshold 0
/* BM-Portal defaults */
#define DEFAULT_memAttr MEMORY_ATTR_CACHEABLE
/* BM-Pool defaults */
#define DEFAULT_dynamicBpid TRUE
#define DEFAULT_useDepletion FALSE
#define DEFAULT_useStockpile FALSE
#define DEFAULT_numOfBufsPerCmd 8
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct
{
/* BMan Buffer Pool Configuration & Status Registers */
volatile uint32_t swdet[BM_NUM_OF_POOLS]; /**< S/W Portal depletion entry threshold */
volatile uint32_t hwdet[BM_NUM_OF_POOLS]; /**< H/W Portal depletion entry threshold */
volatile uint32_t swdxt[BM_NUM_OF_POOLS]; /**< S/W Portal depletion exit threshold */
volatile uint32_t hwdxt[BM_NUM_OF_POOLS]; /**< H/W Portal depletion exit threshold */
volatile uint32_t sdcnt[BM_NUM_OF_POOLS]; /**< S/W Portal depletion count */
volatile uint32_t hdcnt[BM_NUM_OF_POOLS]; /**< H/W Portal depletion count */
volatile uint32_t content[BM_NUM_OF_POOLS]; /**< Snapshot of buffer count in Pool */
volatile uint32_t hdptr[BM_NUM_OF_POOLS]; /**< Head Pointer for Pool's FBPR list. */
/* Free Buffer Proxy Record (FBPR) Manager Query Registers */
volatile uint32_t fbpr_fpc; /**< FBPR Free Pool Count */
volatile uint32_t fbpr_fp_lwit; /**< FBPR Free Pool Low Watermark Interrupt Threshold */
volatile uint8_t res1[248]; /**< reserved */
/* Performance Monitor (PM) Configuration Register */
volatile uint32_t cmd_pm_cfg[BM_NUM_OF_PM]; /**< BMan Command Performance Monitor configuration registers. */
volatile uint32_t fl_pm_cfg[BM_NUM_OF_PM]; /**< BMan Free List Performance Monitor configuration registers */
volatile uint8_t res2[192]; /**< reserved */
/* BMan Error Capture Registers */
volatile uint32_t ecsr; /**< BMan Error Capture Status Register */
volatile uint32_t ecir; /**< BMan Error Capture Information Register */
volatile uint32_t eadr; /**< BMan Error Capture Address Register */
volatile uint8_t res3[4]; /**< reserved */
volatile uint32_t edata[8]; /**< BMan ECC Error Data Register */
volatile uint32_t sbet; /**< BMan Single Bit ECC Error Threshold Register */
volatile uint32_t efcr; /**< BMan Error Fetch Capture Register */
volatile uint32_t efar; /**< BMan Error Fetch Address Register */
volatile uint8_t res4[68]; /**< reserved */
volatile uint32_t sbec0; /**< BMan Single Bit ECC Error Count 0 Register */
volatile uint32_t sbec1; /**< BMan Single Bit ECC Error Count 1 Register */
volatile uint8_t res5[368]; /**< reserved */
/* BMan ID/Revision Registers */
volatile uint32_t ip_rev_1; /**< BMan IP Block Revision 1 register */
volatile uint32_t ip_rev_2; /**< BMan IP Block Revision 2 register */
/* CoreNet Initiator Interface Memory Window Configuration Registers */
volatile uint32_t fbpr_bare; /**< Data Structure Extended Base Address Register */
volatile uint32_t fbpr_bar; /**< Data Structure Base Address Register */
volatile uint8_t res6[8]; /**< reserved */
volatile uint32_t fbpr_ar; /**< Data Structure Attributes Register */
volatile uint8_t res7[240]; /**< reserved */
volatile uint32_t srcidr; /**< BMan Source ID Register */
volatile uint32_t liodnr; /**< BMan Logical I/O Device Number Register */
volatile uint8_t res8[244]; /**< reserved */
/* BMan Interrupt and Error Registers */
volatile uint32_t err_isr; /**< BMan Error Interrupt Status Register */
volatile uint32_t err_ier; /**< BMan Error Interrupt Enable Register */
volatile uint32_t err_isdr; /**< BMan Error Interrupt Status Disable Register */
volatile uint32_t err_iir; /**< BMan Error Interrupt Inhibit Register */
volatile uint32_t err_ifr; /**< BMan Error Interrupt Force Register */
} _PackedType t_BmRegs;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description General defines
*//***************************************************************************/
#define MODULE_NAME_SIZE 30
#define FBPR_ENTRY_SIZE 64 /* 64 bytes */
/* Compilation constants */
#define RCR_THRESH 2 /* reread h/w CI when running out of space */
#define RCR_ITHRESH 4 /* if RCR congests, interrupt threshold */
/* Lock/unlock portals, subject to "UNLOCKED" flag */
#define NCSW_PLOCK(p) ((t_BmPortal*)(p))->irq_flags = XX_DisableAllIntr()
#define PUNLOCK(p) XX_RestoreAllIntr(((t_BmPortal*)(p))->irq_flags)
#define BM_RCR_RING 0
#define BM_NUM_OF_RINGS 1
/**************************************************************************//**
@Description Register defines
*//***************************************************************************/
/* masks */
#define REV1_MAJOR_MASK 0x0000FF00
#define REV1_MINOR_MASK 0x000000FF
#define REV2_INTEG_MASK 0x00FF0000
#define REV2_ERR_MASK 0x0000FF00
#define REV2_CFG_MASK 0x000000FF
#define AR_PRIORITY 0x40000000
#define AR_SIZE_MASK 0x0000003f
/* shifts */
#define REV1_MAJOR_SHIFT 8
#define REV1_MINOR_SHIFT 0
#define REV2_INTEG_SHIFT 16
#define REV2_ERR_SHIFT 8
#define REV2_CFG_SHIFT 0
#define AR_SIZE_SHIFT 0
typedef uint8_t bmRingType_t;
typedef uint8_t (t_BmUpdateCb)(struct bm_portal *p_BmPortalLow);
typedef void (t_BmPrefetchCb)(struct bm_portal *p_BmPortalLow);
typedef void (t_BmCommitCb)(struct bm_portal *p_BmPortalLow, uint8_t myverb);
typedef struct {
bool useStockpile; /**< */
bool dynamicBpid; /**< boolean indicates use of dynamic Bpid */
bool useDepletion; /**< boolean indicates use of depletion */
uint32_t depletionThresholds[MAX_DEPLETION_THRESHOLDS]; /**< depletion-entry/exit thresholds, if useThresholds is set. NB:
this is only allowed if useThresholds is used and
when run in the control plane (which controls Bman CCSR) */
} t_BmPoolDriverParams;
typedef struct BmPool {
uint8_t bpid; /**< index of the buffer pool to encapsulate (0-63) */
t_Handle h_Bm;
t_Handle h_BmPortal;
bool shadowMode;
uint32_t numOfBuffers; /**< Number of buffers use by this pool */
t_BufferPoolInfo bufferPoolInfo; /**< Data buffers pool information */
uint32_t flags; /**< bit-mask of BMAN_POOL_FLAG_*** options */
t_Handle h_App; /**< opaque user value passed as a parameter to 'cb' */
t_BmDepletionCallback *f_Depletion; /**< depletion-entry/exit callback, if BMAN_POOL_FLAG_DEPLETION is set */
uint32_t swDepletionCount;
uint32_t hwDepletionCount;
/* stockpile state - NULL unless BMAN_POOL_FLAG_STOCKPILE is set */
struct bm_buffer *sp;
uint16_t spFill;
uint8_t spBufsCmd;
uint16_t spMaxBufs;
uint16_t spMinBufs;
bool noBuffCtxt;
t_BmPoolDriverParams *p_BmPoolDriverParams;
} t_BmPool;
typedef struct {
t_BmUpdateCb *f_BmUpdateCb;
t_BmPrefetchCb *f_BmPrefetchCb;
t_BmCommitCb *f_BmCommitCb;
} t_BmPortalCallbacks;
typedef struct {
uint32_t hwExtStructsMemAttr;
struct bman_depletion mask;
} t_BmPortalDriverParams;
typedef struct {
t_Handle h_Bm;
struct bm_portal *p_BmPortalLow;
t_BmPortalCallbacks cbs[BM_NUM_OF_RINGS];
int irq;
int cpu; /* This is used for any "core-affine" portals, ie. default portals
* associated to the corresponding cpu. -1 implies that there is no core
* affinity configured. */
struct bman_depletion pools[2]; /**< 2-element array. pools[0] is mask, pools[1] is snapshot. */
uint32_t flags; /**< BMAN_PORTAL_FLAG_*** - static, caller-provided */
uint32_t irq_flags;
int thresh_set;
uint32_t slowpoll;
uint32_t rcrProd; /**< The wrap-around rcr_[prod|cons] counters are used to support BMAN_RELEASE_FLAG_WAIT_SYNC. */
uint32_t rcrCons;
/**< 64-entry hash-table of pool objects that are tracking depletion
* entry/exit (ie. BMAN_POOL_FLAG_DEPLETION). This isn't fast-path, so
* we're not fussy about cache-misses and so forth - whereas the above
* members should all fit in one cacheline.
* BTW, with BM_MAX_NUM_OF_POOLS entries in the hash table and BM_MAX_NUM_OF_POOLS buffer pools to track,
* you'll never guess the hash-function ... */
t_BmPool *depletionPoolsTable[BM_MAX_NUM_OF_POOLS];
t_BmPortalDriverParams *p_BmPortalDriverParams;
} t_BmPortal;
typedef struct {
uint8_t partBpidBase;
uint8_t partNumOfPools;
uint32_t totalNumOfBuffers; /**< total number of buffers */
uint32_t fbprMemPartitionId;
uint32_t fbprThreshold;
uint16_t liodn;
} t_BmDriverParams;
typedef struct {
uint8_t guestId;
t_Handle h_BpidMm;
t_Handle h_SpinLock;
t_Handle h_Portals[DPAA_MAX_NUM_OF_SW_PORTALS];
t_Handle h_Session;
char moduleName[MODULE_NAME_SIZE];
t_BmRegs *p_BmRegs;
void *p_FbprBase;
uint32_t exceptions;
t_BmExceptionsCallback *f_Exception;
t_Handle h_App;
int errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */
t_BmDriverParams *p_BmDriverParams;
} t_Bm;
static __inline__ void BmSetPortalHandle(t_Handle h_Bm, t_Handle h_Portal, e_DpaaSwPortal portalId)
{
ASSERT_COND(!((t_Bm*)h_Bm)->h_Portals[portalId] || !h_Portal);
((t_Bm*)h_Bm)->h_Portals[portalId] = h_Portal;
}
static __inline__ t_Handle BmGetPortalHandle(t_Handle h_Bm)
{
t_Bm *p_Bm = (t_Bm*)h_Bm;
ASSERT_COND(p_Bm);
return p_Bm->h_Portals[CORE_GetId()];
}
static __inline__ uint8_t BmUpdate(t_BmPortal *p_BmPortal, bmRingType_t type)
{
return p_BmPortal->cbs[type].f_BmUpdateCb(p_BmPortal->p_BmPortalLow);
}
static __inline__ void BmPrefetch(t_BmPortal *p_BmPortal, bmRingType_t type)
{
if (p_BmPortal->cbs[type].f_BmPrefetchCb)
p_BmPortal->cbs[type].f_BmPrefetchCb(p_BmPortal->p_BmPortalLow);
}
static __inline__ void BmCommit(t_BmPortal *p_BmPortal, bmRingType_t type, uint8_t myverb)
{
p_BmPortal->cbs[type].f_BmCommitCb(p_BmPortal->p_BmPortalLow, myverb);
}
static __inline__ uint32_t BmBpidGet(t_Bm *p_Bm, bool force, uint32_t base)
{
uint64_t ans, size = 1;
uint32_t alignment = 1;
if (force)
{
if (MM_InRange(p_Bm->h_BpidMm, (uint64_t)base))
{
ans = MM_GetForce(p_Bm->h_BpidMm,
base,
(int)size,
"BM BPID MEM");
ans = base;
}
else if (p_Bm->h_Session)
{
t_BmIpcMsg msg;
t_BmIpcReply reply;
uint32_t replyLength;
t_BmIpcBpidParams ipcBpid;
t_Error errCode = E_OK;
memset(&msg, 0, sizeof(t_BmIpcMsg));
memset(&reply, 0, sizeof(t_BmIpcReply));
ipcBpid.bpid = (uint8_t)base;
msg.msgId = BM_FORCE_BPID;
memcpy(msg.msgBody, &ipcBpid, sizeof(t_BmIpcBpidParams));
replyLength = sizeof(uint32_t) + sizeof(uint32_t);
if ((errCode = XX_IpcSendMessage(p_Bm->h_Session,
(uint8_t*)&msg,
sizeof(msg.msgId) + sizeof(t_BmIpcBpidParams),
(uint8_t*)&reply,
&replyLength,
NULL,
NULL)) != E_OK)
{
REPORT_ERROR(MAJOR, errCode, NO_MSG);
return (uint32_t)ILLEGAL_BASE;
}
if (replyLength != (sizeof(uint32_t) + sizeof(uint32_t)))
{
REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch"));
return (uint32_t)ILLEGAL_BASE;
}
memcpy((uint8_t*)&ans, reply.replyBody, sizeof(uint32_t));
}
else
{
DBG(WARNING, ("No Ipc - can't validate bpid."));
ans = base;
}
}
else
ans = MM_Get(p_Bm->h_BpidMm,
size,
alignment,
"BM BPID MEM");
return (uint32_t)ans;
}
static __inline__ t_Error BmBpidPut(t_Bm *p_Bm, uint32_t base)
{
if (MM_InRange(p_Bm->h_BpidMm, (uint64_t)base))
{
if (MM_Put(p_Bm->h_BpidMm, (uint64_t)base) != base)
return E_OK;
else
return ERROR_CODE(E_NOT_FOUND);
}
else if (p_Bm->h_Session)
{
t_BmIpcMsg msg;
t_BmIpcBpidParams ipcBpid;
t_Error errCode = E_OK;
memset(&msg, 0, sizeof(t_BmIpcMsg));
ipcBpid.bpid = (uint8_t)base;
msg.msgId = BM_PUT_BPID;
memcpy(msg.msgBody, &ipcBpid, sizeof(t_BmIpcBpidParams));
if ((errCode = XX_IpcSendMessage(p_Bm->h_Session,
(uint8_t*)&msg,
sizeof(msg.msgId) + sizeof(t_BmIpcBpidParams),
NULL,
NULL,
NULL,
NULL)) != E_OK)
RETURN_ERROR(MAJOR, errCode, NO_MSG);
}
else
DBG(WARNING, ("No Ipc - can't validate bpid."));
return E_OK;
}
/****************************************/
/* Inter-Module functions */
/****************************************/
typedef enum e_BmInterModuleCounters {
e_BM_IM_COUNTERS_FBPR = 0,
e_BM_IM_COUNTERS_POOL_CONTENT,
e_BM_IM_COUNTERS_POOL_SW_DEPLETION,
e_BM_IM_COUNTERS_POOL_HW_DEPLETION
} e_BmInterModuleCounters;
t_Error BmSetPoolThresholds(t_Handle h_Bm, uint8_t bpid, const uint32_t *thresholds);
t_Error BmUnSetPoolThresholds(t_Handle h_Bm, uint8_t bpid);
uint8_t BmPortalAcquire(t_Handle h_BmPortal, uint8_t bpid, struct bm_buffer *bufs, uint8_t num);
t_Error BmPortalRelease(t_Handle h_BmPortal, uint8_t bpid, struct bm_buffer *bufs, uint8_t num, uint32_t flags);
t_Error BmPortalQuery(t_Handle h_BmPortal, struct bman_depletion *p_Pools, bool depletion);
uint32_t BmGetCounter(t_Handle h_Bm, e_BmInterModuleCounters counter, uint8_t bpid);
t_Error BmGetRevision(t_Handle h_Bm, t_BmRevisionInfo *p_BmRevisionInfo);
#endif /* __BM_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/**************************************************************************//**
@File bm_ipc.h
@Description BM Inter-Partition prototypes, structures and definitions.
*//***************************************************************************/
#ifndef __BM_IPC_H
#define __BM_IPC_H
#include "error_ext.h"
#include "std_ext.h"
/**************************************************************************//**
@Group BM_grp Frame Manager API
@Description BM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group BM_IPC_grp BM Inter-Partition messaging Unit
@Description BM Inter-Partition messaging unit API definitions and enums.
@{
*//***************************************************************************/
#define BM_SET_POOL_THRESH 1
#define BM_UNSET_POOL_THRESH 2
#define BM_GET_COUNTER 3
#define BM_GET_REVISION 4
#define BM_FORCE_BPID 5
#define BM_PUT_BPID 6
#define BM_MASTER_IS_ALIVE 7
#define BM_IPC_MAX_REPLY_BODY_SIZE 16
#define BM_IPC_MAX_REPLY_SIZE (BM_IPC_MAX_REPLY_BODY_SIZE + sizeof(uint32_t))
#define BM_IPC_MAX_MSG_SIZE 30
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct t_BmIpcMsg
{
uint32_t msgId;
uint8_t msgBody[BM_IPC_MAX_MSG_SIZE];
} _PackedType t_BmIpcMsg;
typedef _Packed struct t_BmIpcReply
{
uint32_t error;
uint8_t replyBody[BM_IPC_MAX_REPLY_BODY_SIZE];
} _PackedType t_BmIpcReply;
typedef _Packed struct t_BmIpcPoolThreshParams
{
uint8_t bpid; /**< IN */
uint32_t thresholds[MAX_DEPLETION_THRESHOLDS]; /**< IN */
} _PackedType t_BmIpcPoolThreshParams;
typedef _Packed struct t_BmIpcGetCounter
{
uint8_t bpid; /**< IN */
uint32_t enumId; /**< IN */
} _PackedType t_BmIpcGetCounter;
typedef _Packed struct t_BmIpcBpidParams
{
uint8_t bpid; /**< IN */
} _PackedType t_BmIpcBpidParams;
typedef _Packed struct t_BmIpcRevisionInfo {
uint8_t majorRev; /**< Major revision */
uint8_t minorRev; /**< Minor revision */
} _PackedType t_BmIpcRevisionInfo;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/** @} */ /* end of BM_IPC_grp group */
/** @} */ /* end of BM_grp group */
#endif /* __BM_IPC_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File bm.c
@Description BM
*//***************************************************************************/
#include "error_ext.h"
#include "std_ext.h"
#include "string_ext.h"
#include "mem_ext.h"
#include "core_ext.h"
#include "bm.h"
#define __ERR_MODULE__ MODULE_BM
/****************************************/
/* static functions */
/****************************************/
/* (De)Registration of depletion notification callbacks */
static void depletion_link(t_BmPool *p_BmPool)
{
t_BmPortal *p_Portal = (t_BmPortal *)p_BmPool->h_BmPortal;
NCSW_PLOCK(p_Portal);
p_Portal->depletionPoolsTable[p_BmPool->bpid] = p_BmPool;
bm_isr_bscn_mask(p_Portal->p_BmPortalLow, (uint8_t)p_BmPool->bpid, 1);
PUNLOCK(p_Portal);
}
static void depletion_unlink(t_BmPool *p_BmPool)
{
t_BmPortal *p_Portal = (t_BmPortal *)p_BmPool->h_BmPortal;
NCSW_PLOCK(p_Portal);
p_Portal->depletionPoolsTable[p_BmPool->bpid] = NULL;
bm_isr_bscn_mask(p_Portal->p_BmPortalLow, (uint8_t)p_BmPool->bpid, 0);
PUNLOCK(p_Portal);
}
static t_Error BmPoolRelease(t_BmPool *p_BmPool,
t_Handle h_BmPortal,
struct bm_buffer *bufs,
uint8_t num,
uint32_t flags)
{
ASSERT_COND(num && (num <= 8));
if (p_BmPool->flags & BMAN_POOL_FLAG_NO_RELEASE)
return ERROR_CODE(E_INVALID_VALUE);
/* Without stockpile, this API is a pass-through to the h/w operation */
if (!(p_BmPool->flags & BMAN_POOL_FLAG_STOCKPILE))
return BmPortalRelease(h_BmPortal, p_BmPool->bpid, bufs, num, flags);
/* This needs some explanation. Adding the given buffers may take the
* stockpile over the threshold, but in fact the stockpile may already
* *be* over the threshold if a previous release-to-hw attempt had
* failed. So we have 3 cases to cover;
* 1. we add to the stockpile and don't hit the threshold,
* 2. we add to the stockpile, hit the threshold and release-to-hw,
* 3. we have to release-to-hw before adding to the stockpile
* (not enough room in the stockpile for case 2).
* Our constraints on thresholds guarantee that in case 3, there must be
* at least 8 bufs already in the stockpile, so all release-to-hw ops
* are for 8 bufs. Despite all this, the API must indicate whether the
* given buffers were taken off the caller's hands, irrespective of
* whether a release-to-hw was attempted. */
while (num)
{
/* Add buffers to stockpile if they fit */
if ((p_BmPool->spFill + num) <= p_BmPool->spMaxBufs)
{
memcpy(PTR_MOVE(p_BmPool->sp, sizeof(struct bm_buffer) * (p_BmPool->spFill)),
bufs,
sizeof(struct bm_buffer) * num);
p_BmPool->spFill += num;
num = 0; /* --> will return success no matter what */
}
else
/* Do hw op if hitting the high-water threshold */
{
t_Error ret = BmPortalRelease(h_BmPortal,
p_BmPool->bpid,
(struct bm_buffer *)PTR_MOVE(p_BmPool->sp, sizeof(struct bm_buffer) * (p_BmPool->spFill - p_BmPool->spBufsCmd)),
p_BmPool->spBufsCmd,
flags);
if (ret)
return (num ? ret : E_OK);
p_BmPool->spFill -= p_BmPool->spBufsCmd;
}
}
return E_OK;
}
static int BmPoolAcquire(t_BmPool *p_BmPool,t_Handle h_BmPortal,
struct bm_buffer *bufs, uint8_t num, uint32_t flags)
{
ASSERT_COND(IN_RANGE(1, num, 8));
if (p_BmPool->flags & BMAN_POOL_FLAG_ONLY_RELEASE)
return 0;
/* Without stockpile, this API is a pass-through to the h/w operation */
if (!(p_BmPool->flags & BMAN_POOL_FLAG_STOCKPILE))
return BmPortalAcquire(h_BmPortal, p_BmPool->bpid, bufs, num);
/* Only need a h/w op if we'll hit the low-water thresh */
if (!(flags & BMAN_ACQUIRE_FLAG_STOCKPILE) &&
((p_BmPool->spFill - num) < p_BmPool->spMinBufs))
{
p_BmPool->spFill += BmPortalAcquire(h_BmPortal,
p_BmPool->bpid,
(struct bm_buffer *)PTR_MOVE(p_BmPool->sp, sizeof(struct bm_buffer) * (p_BmPool->spFill)),
p_BmPool->spBufsCmd);
}
else if (p_BmPool->spFill < num)
return 0;
if (!p_BmPool->spFill)
return 0;
memcpy(bufs,
PTR_MOVE(p_BmPool->sp, sizeof(struct bm_buffer) * (p_BmPool->spFill - num)),
sizeof(struct bm_buffer) * num);
p_BmPool->spFill -= num;
return num;
}
static t_Error BmPoolFree(t_BmPool *p_BmPool, bool discardBuffers)
{
t_Handle h_BufContext;
void *p_Data;
ASSERT_COND(p_BmPool);
if (!p_BmPool->shadowMode)
{
if (p_BmPool->flags & BMAN_POOL_FLAG_DEPLETION)
{
depletion_unlink(p_BmPool);
BmUnSetPoolThresholds(p_BmPool->h_Bm, p_BmPool->bpid);
}
while (TRUE)
{
p_Data = BM_POOL_GetBuf(p_BmPool, p_BmPool->h_BmPortal);
if (!p_Data)
break;
h_BufContext = BM_POOL_GetBufferContext(p_BmPool, p_Data);
if (!discardBuffers)
p_BmPool->bufferPoolInfo.f_PutBuf(p_BmPool->bufferPoolInfo.h_BufferPool, p_Data, h_BufContext);
}
BmBpidPut(p_BmPool->h_Bm, p_BmPool->bpid);
}
if (p_BmPool->sp)
XX_Free(p_BmPool->sp);
XX_Free(p_BmPool);
return E_OK;
}
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle BM_POOL_Config(t_BmPoolParam *p_BmPoolParam)
{
t_BmPool *p_BmPool;
SANITY_CHECK_RETURN_VALUE(p_BmPoolParam, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_BmPoolParam->h_Bm, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE((p_BmPoolParam->shadowMode ||
(p_BmPoolParam->bufferPoolInfo.h_BufferPool &&
p_BmPoolParam->bufferPoolInfo.f_GetBuf &&
p_BmPoolParam->bufferPoolInfo.f_PutBuf &&
p_BmPoolParam->bufferPoolInfo.bufferSize)), E_INVALID_STATE, NULL);
p_BmPool = (t_BmPool*)XX_Malloc(sizeof(t_BmPool));
if (!p_BmPool)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("BM Pool obj!!!"));
return NULL;
}
memset(p_BmPool, 0, sizeof(t_BmPool));
p_BmPool->p_BmPoolDriverParams = (t_BmPoolDriverParams *)XX_Malloc(sizeof(t_BmPoolDriverParams));
if (!p_BmPool->p_BmPoolDriverParams)
{
XX_Free(p_BmPool);
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Bm Pool driver parameters"));
return NULL;
}
memset(p_BmPool->p_BmPoolDriverParams, 0, sizeof(t_BmPoolDriverParams));
p_BmPool->h_Bm = p_BmPoolParam->h_Bm;
p_BmPool->h_BmPortal = p_BmPoolParam->h_BmPortal;
p_BmPool->h_App = p_BmPoolParam->h_App;
p_BmPool->numOfBuffers = p_BmPoolParam->numOfBuffers;
p_BmPool->shadowMode = p_BmPoolParam->shadowMode;
if (!p_BmPool->h_BmPortal)
{
p_BmPool->h_BmPortal = BmGetPortalHandle(p_BmPool->h_Bm);
SANITY_CHECK_RETURN_VALUE(p_BmPool->h_BmPortal, E_INVALID_HANDLE, NULL);
}
memcpy(&p_BmPool->bufferPoolInfo, &p_BmPoolParam->bufferPoolInfo, sizeof(t_BufferPoolInfo));
if (!p_BmPool->bufferPoolInfo.f_PhysToVirt)
p_BmPool->bufferPoolInfo.f_PhysToVirt = XX_PhysToVirt;
if (!p_BmPool->bufferPoolInfo.f_VirtToPhys)
p_BmPool->bufferPoolInfo.f_VirtToPhys = XX_VirtToPhys;
p_BmPool->p_BmPoolDriverParams->dynamicBpid = DEFAULT_dynamicBpid;
p_BmPool->p_BmPoolDriverParams->useDepletion = DEFAULT_useDepletion;
p_BmPool->p_BmPoolDriverParams->useStockpile = DEFAULT_useStockpile;
if (p_BmPool->shadowMode)
{
p_BmPool->numOfBuffers = 0;
BM_POOL_ConfigBpid(p_BmPool, p_BmPoolParam->bpid);
}
return p_BmPool;
}
t_Error BM_POOL_Init(t_Handle h_BmPool)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
t_Error err;
SANITY_CHECK_RETURN_ERROR(p_BmPool, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE);
p_BmPool->flags |= (p_BmPool->p_BmPoolDriverParams->dynamicBpid)?BMAN_POOL_FLAG_DYNAMIC_BPID:0;
p_BmPool->flags |= (p_BmPool->p_BmPoolDriverParams->useStockpile)?BMAN_POOL_FLAG_STOCKPILE:0;
p_BmPool->flags |= ((!p_BmPool->shadowMode) &&
(p_BmPool->p_BmPoolDriverParams->useDepletion))?BMAN_POOL_FLAG_DEPLETION:0;
if (p_BmPool->flags & BMAN_POOL_FLAG_DYNAMIC_BPID)
{
if((p_BmPool->bpid = (uint8_t)BmBpidGet(p_BmPool->h_Bm, FALSE, (uint32_t)0)) == (uint8_t)ILLEGAL_BASE)
{
BM_POOL_Free(p_BmPool);
RETURN_ERROR(CRITICAL, E_INVALID_STATE, ("can't allocate new dynamic pool id"));
}
}
else
{
if (BmBpidGet(p_BmPool->h_Bm, TRUE, (uint32_t)p_BmPool->bpid) == (uint32_t)ILLEGAL_BASE)
{
BM_POOL_Free(p_BmPool);
RETURN_ERROR(CRITICAL, E_INVALID_STATE, ("can't force pool id %d", p_BmPool->bpid));
}
}
if (p_BmPool->flags & BMAN_POOL_FLAG_DEPLETION)
{
if(BmSetPoolThresholds(p_BmPool->h_Bm, p_BmPool->bpid, p_BmPool->p_BmPoolDriverParams->depletionThresholds))
{
BM_POOL_Free(p_BmPool);
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("can't set thresh for pool bpid %d",p_BmPool->bpid));
}
depletion_link(p_BmPool);
}
if (p_BmPool->flags & BMAN_POOL_FLAG_STOCKPILE)
{
p_BmPool->sp = (struct bm_buffer *)XX_Malloc(sizeof(struct bm_buffer) * p_BmPool->spMaxBufs);
if (!p_BmPool->sp)
{
BM_POOL_Free(p_BmPool);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Bm Pool Stockpile"));
}
memset(p_BmPool->sp, 0, sizeof(struct bm_buffer) * p_BmPool->spMaxBufs);
}
XX_Free(p_BmPool->p_BmPoolDriverParams);
p_BmPool->p_BmPoolDriverParams = NULL;
/*******************/
/* Create buffers */
/*******************/
if ((err = BM_POOL_FillBufs (p_BmPool, p_BmPool->h_BmPortal, p_BmPool->numOfBuffers)) != E_OK)
{
BM_POOL_Free(p_BmPool);
RETURN_ERROR(MAJOR, err, NO_MSG);
}
return E_OK;
}
t_Error BM_POOL_Free(t_Handle h_BmPool)
{
SANITY_CHECK_RETURN_ERROR(h_BmPool, E_INVALID_HANDLE);
return BmPoolFree(h_BmPool, FALSE);
}
t_Error BM_POOL_ConfigBpid(t_Handle h_BmPool, uint8_t bpid)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_ERROR(p_BmPool, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(bpid < BM_MAX_NUM_OF_POOLS, E_INVALID_VALUE);
p_BmPool->p_BmPoolDriverParams->dynamicBpid = FALSE;
p_BmPool->bpid = bpid;
return E_OK;
}
t_Error BM_POOL_ConfigDepletion(t_Handle h_BmPool, t_BmDepletionCallback *f_Depletion, uint32_t *p_Thresholds)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_ERROR(p_BmPool, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(f_Depletion, E_INVALID_HANDLE);
p_BmPool->p_BmPoolDriverParams->useDepletion = TRUE;
p_BmPool->f_Depletion = f_Depletion;
memcpy(&p_BmPool->p_BmPoolDriverParams->depletionThresholds,
p_Thresholds,
sizeof(p_BmPool->p_BmPoolDriverParams->depletionThresholds));
return E_OK;
}
t_Error BM_POOL_ConfigStockpile(t_Handle h_BmPool, uint16_t maxBuffers, uint16_t minBuffers)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_ERROR(p_BmPool, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(maxBuffers, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(maxBuffers >= minBuffers, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR((p_BmPool->shadowMode ||
((maxBuffers * 2) <= p_BmPool->numOfBuffers)),
E_INVALID_STATE);
p_BmPool->p_BmPoolDriverParams->useStockpile = TRUE;
p_BmPool->spMaxBufs = maxBuffers;
p_BmPool->spMinBufs = minBuffers;
p_BmPool->spBufsCmd = DEFAULT_numOfBufsPerCmd;
SANITY_CHECK_RETURN_ERROR((p_BmPool->spMaxBufs >=
(p_BmPool->spMinBufs + p_BmPool->spBufsCmd)),
E_INVALID_STATE);
return E_OK;
}
t_Error BM_POOL_ConfigBuffContextMode(t_Handle h_BmPool, bool en)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_ERROR(p_BmPool, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE);
p_BmPool->noBuffCtxt = !en;
return E_OK;
}
void * BM_POOL_GetBuf(t_Handle h_BmPool, t_Handle h_BmPortal)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
struct bm_buffer bufs[1];
uint8_t retBufsNum;
uint64_t physAddr;
uint32_t flags = 0;
SANITY_CHECK_RETURN_VALUE(p_BmPool, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_BmPool->bufferPoolInfo.f_PhysToVirt, E_INVALID_STATE, NULL);
if (!h_BmPortal)
{
if (p_BmPool->h_BmPortal)
h_BmPortal = p_BmPool->h_BmPortal;
else
{
SANITY_CHECK_RETURN_VALUE(p_BmPool->h_Bm, E_INVALID_HANDLE, NULL);
h_BmPortal = BmGetPortalHandle(p_BmPool->h_Bm);
SANITY_CHECK_RETURN_VALUE(h_BmPortal, E_INVALID_HANDLE, NULL);
}
}
retBufsNum = (uint8_t)BmPoolAcquire(p_BmPool, h_BmPortal, bufs, 1, flags);
if (!retBufsNum)
{
REPORT_ERROR(TRACE, E_NOT_AVAILABLE, ("buffer"));
return NULL;
}
physAddr = (uint64_t)bufs[0].lo;
physAddr |= (uint64_t)(((uint64_t)bufs[0].hi << 32) & 0x000000ff00000000LL);
DBG(TRACE,("Get Buffer : poolId %d, address 0x%016llx",
p_BmPool->bpid,
p_BmPool->bufferPoolInfo.f_PhysToVirt((physAddress_t)physAddr)));
return p_BmPool->bufferPoolInfo.f_PhysToVirt((physAddress_t)physAddr);
}
t_Error BM_POOL_PutBuf(t_Handle h_BmPool, t_Handle h_BmPortal, void *p_Buff)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
uint64_t physAddress;
struct bm_buffer bufs[1];
SANITY_CHECK_RETURN_ERROR(p_BmPool, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_BmPool->p_BmPoolDriverParams, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_Buff, E_NULL_POINTER);
physAddress = (uint64_t)(XX_VirtToPhys(p_Buff));
bufs[0].bpid = p_BmPool->bpid;
bufs[0].hi = (uint8_t)((physAddress & 0x000000ff00000000LL) >> 32);
bufs[0].lo = (uint32_t)(physAddress & 0xffffffff);
DBG(TRACE,("Put Buffer : poolId %d, address 0x%016llx, phys 0x%016llx",
p_BmPool->bpid, (uint64_t)PTR_TO_UINT(p_Buff), physAddress));
if (!h_BmPortal)
{
if (p_BmPool->h_BmPortal)
h_BmPortal = p_BmPool->h_BmPortal;
else
{
SANITY_CHECK_RETURN_ERROR(p_BmPool->h_Bm, E_INVALID_HANDLE);
h_BmPortal = BmGetPortalHandle(p_BmPool->h_Bm);
SANITY_CHECK_RETURN_ERROR(h_BmPortal, E_INVALID_HANDLE);
}
}
return BmPoolRelease(p_BmPool, h_BmPortal, bufs, 1, BMAN_RELEASE_FLAG_WAIT);
}
t_Error BM_POOL_FillBufs(t_Handle h_BmPool, t_Handle h_BmPortal, uint32_t numBufs)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_ERROR(p_BmPool, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_BmPool->p_BmPoolDriverParams, E_INVALID_STATE);
if (!h_BmPortal)
{
if (p_BmPool->h_BmPortal)
h_BmPortal = p_BmPool->h_BmPortal;
else
{
SANITY_CHECK_RETURN_ERROR(p_BmPool->h_Bm, E_INVALID_HANDLE);
h_BmPortal = BmGetPortalHandle(p_BmPool->h_Bm);
SANITY_CHECK_RETURN_ERROR(h_BmPortal, E_INVALID_HANDLE);
}
}
while (numBufs--)
{
uint8_t *p_Data;
t_Error res;
t_Handle h_BufContext;
p_Data = p_BmPool->bufferPoolInfo.f_GetBuf(p_BmPool->bufferPoolInfo.h_BufferPool, &h_BufContext);
if(!p_Data)
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("run-out of buffers for bpid %d",p_BmPool->bpid));
if (!p_BmPool->noBuffCtxt)
*(t_Handle *)(p_Data - sizeof(t_Handle)) = h_BufContext;
if ((res = BM_POOL_PutBuf(p_BmPool, h_BmPortal, p_Data)) != E_OK)
RETURN_ERROR(CRITICAL, res, ("Seeding reserved buffer pool failed"));
}
return E_OK;
}
uint8_t BM_POOL_GetId(t_Handle h_BmPool)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_VALUE(p_BmPool, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE, 0);
return p_BmPool->bpid;
}
uint16_t BM_POOL_GetBufferSize(t_Handle h_BmPool)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_VALUE(p_BmPool, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE, 0);
return p_BmPool->bufferPoolInfo.bufferSize;
}
t_Handle BM_POOL_GetBufferContext(t_Handle h_BmPool, void *p_Buff)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_VALUE(p_BmPool, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_Buff, E_NULL_POINTER, NULL);
if (p_BmPool->noBuffCtxt)
return NULL;
return *(t_Handle *)PTR_MOVE(p_Buff, -(sizeof(t_Handle)));
}
void * BM_POOL_PhysToVirt(t_Handle h_BmPool, physAddress_t addr)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_VALUE(p_BmPool, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(!p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE, NULL);
return p_BmPool->bufferPoolInfo.f_PhysToVirt(addr);
}
physAddress_t BM_POOL_VirtToPhys(t_Handle h_BmPool, void *p_Buff)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_VALUE(p_BmPool, E_INVALID_HANDLE, (physAddress_t)0);
SANITY_CHECK_RETURN_VALUE(!p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE, (physAddress_t)0);
return p_BmPool->bufferPoolInfo.f_VirtToPhys(p_Buff);
}
uint32_t BM_POOL_GetCounter(t_Handle h_BmPool, e_BmPoolCounters counter)
{
t_BmPool *p_BmPool = (t_BmPool *)h_BmPool;
SANITY_CHECK_RETURN_VALUE(p_BmPool, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_BmPool->p_BmPoolDriverParams, E_INVALID_HANDLE, 0);
switch(counter)
{
case(e_BM_POOL_COUNTERS_CONTENT):
return BmGetCounter(p_BmPool->h_Bm, e_BM_IM_COUNTERS_POOL_CONTENT, p_BmPool->bpid);
case(e_BM_POOL_COUNTERS_SW_DEPLETION):
return (p_BmPool->swDepletionCount +=
BmGetCounter(p_BmPool->h_Bm, e_BM_IM_COUNTERS_POOL_SW_DEPLETION, p_BmPool->bpid));
case(e_BM_POOL_COUNTERS_HW_DEPLETION):
return (p_BmPool->hwDepletionCount +=
BmGetCounter(p_BmPool->h_Bm, e_BM_IM_COUNTERS_POOL_HW_DEPLETION, p_BmPool->bpid));
default:
break;
}
/* should never get here */
ASSERT_COND(FALSE);
return 0;
}

561
sys/contrib/ncsw/Peripherals/BM/bm_portal.c Normal file
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@ -0,0 +1,561 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File bm.c
@Description BM
*//***************************************************************************/
#include "error_ext.h"
#include "std_ext.h"
#include "string_ext.h"
#include "mem_ext.h"
#include "core_ext.h"
#include "bm.h"
#define __ERR_MODULE__ MODULE_BM
/****************************************/
/* static functions */
/****************************************/
static uint32_t __poll_portal_slow(t_BmPortal *p);
static void __poll_portal_fast(t_BmPortal *p);
/* Portal interrupt handler */
static void portal_isr(void *ptr)
{
t_BmPortal *portal = ptr;
/* Only do fast-path handling if it's required */
if (portal->flags & BMAN_PORTAL_FLAG_IRQ_FAST)
__poll_portal_fast(portal);
__poll_portal_slow(portal);
}
/**
* bman_create_portal - Manage a Bman s/w portal
* @portal: the s/w corenet portal to use
* @flags: bit-mask of BMAN_PORTAL_FLAG_*** options
* @pools: bit-array of buffer pools available to this portal
* @portal_ctx: opaque user-supplied data to be associated with the portal
*
* Creates a managed portal object. @irq is only used if @flags specifies
* BMAN_PORTAL_FLAG_IRQ. @pools is copied, so the caller can do as they please
* with it after the function returns. It will only be possible to configure
* buffer pool objects as "suppliers" if they are specified in @pools, and the
* driver will only track depletion state changes to the same subset of buffer
* pools. If @pools is NULL, buffer pool depletion state will not be tracked.
* If the BMAN_PORTAL_FLAG_RECOVER flag is specified, then the function will
* attempt to expire any existing RCR entries, otherwise the function will fail
* if RCR is non-empty. If the BMAN_PORTAL_FLAG_WAIT flag is set, the function
* is allowed to block waiting for expiration of RCR. BMAN_PORTAL_FLAG_WAIT_INT
* makes any blocking interruptible.
*/
static t_Error bman_create_portal(t_BmPortal *p_BmPortal,
uint32_t flags,
const struct bman_depletion *pools)
{
int ret = 0;
uint8_t bpid = 0;
e_BmPortalRcrConsumeMode rcr_cmode;
e_BmPortalProduceMode pmode;
pmode = e_BmPortalPVB;
rcr_cmode = (flags & BMAN_PORTAL_FLAG_CACHE) ? e_BmPortalRcrCCE : e_BmPortalRcrCCI;
switch (pmode)
{
case e_BmPortalPCI:
p_BmPortal->cbs[BM_RCR_RING].f_BmCommitCb = bm_rcr_pci_commit;
break;
case e_BmPortalPCE:
p_BmPortal->cbs[BM_RCR_RING].f_BmCommitCb = bm_rcr_pce_commit;
break;
case e_BmPortalPVB:
p_BmPortal->cbs[BM_RCR_RING].f_BmCommitCb = bm_rcr_pvb_commit;
break;
}
switch (rcr_cmode)
{
case e_BmPortalRcrCCI:
p_BmPortal->cbs[BM_RCR_RING].f_BmUpdateCb = bm_rcr_cci_update;
p_BmPortal->cbs[BM_RCR_RING].f_BmPrefetchCb = NULL;
break;
case e_BmPortalRcrCCE:
p_BmPortal->cbs[BM_RCR_RING].f_BmUpdateCb = bm_rcr_cce_update;
p_BmPortal->cbs[BM_RCR_RING].f_BmPrefetchCb = bm_rcr_cce_prefetch;
break;
}
if (bm_rcr_init(p_BmPortal->p_BmPortalLow, pmode, rcr_cmode)) {
REPORT_ERROR(MAJOR, E_INVALID_STATE, ("RCR initialization failed"));
goto fail_rcr;
}
if (bm_mc_init(p_BmPortal->p_BmPortalLow)) {
REPORT_ERROR(MAJOR, E_INVALID_STATE, ("MC initialization failed"));
goto fail_mc;
}
p_BmPortal->pools[0] = *pools;
bman_depletion_init(&p_BmPortal->pools[1]);
while (bpid < BM_MAX_NUM_OF_POOLS) {
/* Default to all BPIDs disabled, we enable as required
* at run-time. */
bm_isr_bscn_mask(p_BmPortal->p_BmPortalLow, bpid, 0);
bpid++;
}
p_BmPortal->flags = flags;
p_BmPortal->slowpoll = 0;
p_BmPortal->rcrProd = p_BmPortal->rcrCons = 0;
memset(&p_BmPortal->depletionPoolsTable, 0, sizeof(p_BmPortal->depletionPoolsTable));
/* Write-to-clear any stale interrupt status bits */
bm_isr_disable_write(p_BmPortal->p_BmPortalLow, 0xffffffff);
bm_isr_status_clear(p_BmPortal->p_BmPortalLow, 0xffffffff);
bm_isr_enable_write(p_BmPortal->p_BmPortalLow, BM_PIRQ_RCRI | BM_PIRQ_BSCN);
if (flags & BMAN_PORTAL_FLAG_IRQ)
{
XX_SetIntr(p_BmPortal->irq, portal_isr, p_BmPortal);
XX_EnableIntr(p_BmPortal->irq);
/* Enable the bits that make sense */
bm_isr_uninhibit(p_BmPortal->p_BmPortalLow);
} else
/* without IRQ, we can't block */
flags &= ~BMAN_PORTAL_FLAG_WAIT;
/* Need RCR to be empty before continuing */
bm_isr_disable_write(p_BmPortal->p_BmPortalLow, (uint32_t)~BM_PIRQ_RCRI);
if (!(flags & BMAN_PORTAL_FLAG_RECOVER) ||
!(flags & BMAN_PORTAL_FLAG_WAIT))
ret = bm_rcr_get_fill(p_BmPortal->p_BmPortalLow);
if (ret) {
REPORT_ERROR(MAJOR, E_INVALID_STATE, ("RCR unclean, need recovery"));
goto fail_rcr_empty;
}
bm_isr_disable_write(p_BmPortal->p_BmPortalLow, 0);
return E_OK;
fail_rcr_empty:
bm_mc_finish(p_BmPortal->p_BmPortalLow);
fail_mc:
bm_rcr_finish(p_BmPortal->p_BmPortalLow);
fail_rcr:
XX_Free(p_BmPortal);
return ERROR_CODE(E_INVALID_STATE);
}
static void bman_destroy_portal(t_BmPortal* p_BmPortal)
{
BmUpdate(p_BmPortal, BM_RCR_RING);
if (p_BmPortal->flags & BMAN_PORTAL_FLAG_IRQ)
{
XX_DisableIntr(p_BmPortal->irq);
XX_FreeIntr(p_BmPortal->irq);
}
bm_mc_finish(p_BmPortal->p_BmPortalLow);
bm_rcr_finish(p_BmPortal->p_BmPortalLow);
XX_Free(p_BmPortal->p_BmPortalLow);
}
/* When release logic waits on available RCR space, we need a global waitqueue
* in the case of "affine" use (as the waits wake on different cpus which means
* different portals - so we can't wait on any per-portal waitqueue). */
static uint32_t __poll_portal_slow(t_BmPortal* p_BmPortal)
{
struct bman_depletion tmp;
t_BmPool *p_BmPool;
uint32_t ret,is = bm_isr_status_read(p_BmPortal->p_BmPortalLow);
ret = is;
/* There is a gotcha to be aware of. If we do the query before clearing
* the status register, we may miss state changes that occur between the
* two. If we write to clear the status register before the query, the
* cache-enabled query command may overtake the status register write
* unless we use a heavyweight sync (which we don't want). Instead, we
* write-to-clear the status register then *read it back* before doing
* the query, hence the odd while loop with the 'is' accumulation. */
if (is & BM_PIRQ_BSCN) {
uint32_t i, j;
uint32_t __is;
bm_isr_status_clear(p_BmPortal->p_BmPortalLow, BM_PIRQ_BSCN);
while ((__is = bm_isr_status_read(p_BmPortal->p_BmPortalLow)) & BM_PIRQ_BSCN) {
is |= __is;
bm_isr_status_clear(p_BmPortal->p_BmPortalLow, BM_PIRQ_BSCN);
}
is &= ~BM_PIRQ_BSCN;
BmPortalQuery(p_BmPortal, &tmp, TRUE);
for (i = 0; i < 2; i++) {
uint32_t idx = i * 32;
/* tmp is a mask of currently-depleted pools.
* pools[0] is mask of those we care about.
* pools[1] is our previous view (we only want to
* be told about changes). */
tmp.__state[i] &= p_BmPortal->pools[0].__state[i];
if (tmp.__state[i] == p_BmPortal->pools[1].__state[i])
/* fast-path, nothing to see, move along */
continue;
for (j = 0; j <= 31; j++, idx++) {
int b4 = bman_depletion_get(&p_BmPortal->pools[1], (uint8_t)idx);
int af = bman_depletion_get(&tmp, (uint8_t)idx);
if (b4 == af)
continue;
p_BmPool = p_BmPortal->depletionPoolsTable[idx];
ASSERT_COND(p_BmPool->f_Depletion);
p_BmPool->f_Depletion(p_BmPool->h_App, (bool)af);
}
}
p_BmPortal->pools[1] = tmp;
}
if (is & BM_PIRQ_RCRI) {
NCSW_PLOCK(p_BmPortal);
p_BmPortal->rcrCons += BmUpdate(p_BmPortal, BM_RCR_RING);
bm_rcr_set_ithresh(p_BmPortal->p_BmPortalLow, 0);
PUNLOCK(p_BmPortal);
bm_isr_status_clear(p_BmPortal->p_BmPortalLow, BM_PIRQ_RCRI);
is &= ~BM_PIRQ_RCRI;
}
/* There should be no status register bits left undefined */
ASSERT_COND(!is);
return ret;
}
static void __poll_portal_fast(t_BmPortal* p_BmPortal)
{
UNUSED(p_BmPortal);
/* nothing yet, this is where we'll put optimised RCR consumption
* tracking */
}
static __inline__ void rel_set_thresh(t_BmPortal *p_BmPortal, int check)
{
if (!check || !bm_rcr_get_ithresh(p_BmPortal->p_BmPortalLow))
bm_rcr_set_ithresh(p_BmPortal->p_BmPortalLow, RCR_ITHRESH);
}
/* Used as a wait_event() expression. If it returns non-NULL, any lock will
* remain held. */
static struct bm_rcr_entry *try_rel_start(t_BmPortal *p_BmPortal)
{
struct bm_rcr_entry *r;
NCSW_PLOCK(p_BmPortal);
if (bm_rcr_get_avail((p_BmPortal)->p_BmPortalLow) < RCR_THRESH)
BmUpdate(p_BmPortal, BM_RCR_RING);
r = bm_rcr_start((p_BmPortal)->p_BmPortalLow);
if (!r) {
rel_set_thresh(p_BmPortal, 1);
PUNLOCK(p_BmPortal);
}
return r;
}
static __inline__ t_Error wait_rel_start(t_BmPortal *p_BmPortal,
struct bm_rcr_entry **rel,
uint32_t flags)
{
int tries = 100;
UNUSED(flags);
do {
*rel = try_rel_start(p_BmPortal);
XX_Sleep(1);
} while (!*rel && --tries);
if (!(*rel))
return ERROR_CODE(E_BUSY);
return E_OK;
}
/* This copies Qman's eqcr_completed() routine, see that for details */
static int rel_completed(t_BmPortal *p_BmPortal, uint32_t rcr_poll)
{
uint32_t tr_cons = p_BmPortal->rcrCons;
if (rcr_poll & 0xc0000000) {
rcr_poll &= 0x7fffffff;
tr_cons ^= 0x80000000;
}
if (tr_cons >= rcr_poll)
return 1;
if ((rcr_poll - tr_cons) > BM_RCR_SIZE)
return 1;
if (!bm_rcr_get_fill(p_BmPortal->p_BmPortalLow))
/* If RCR is empty, we must have completed */
return 1;
rel_set_thresh(p_BmPortal, 0);
return 0;
}
static __inline__ void rel_commit(t_BmPortal *p_BmPortal, uint32_t flags,uint8_t num)
{
uint32_t rcr_poll;
BmCommit(p_BmPortal, BM_RCR_RING, (uint8_t)(BM_RCR_VERB_CMD_BPID_SINGLE | (num & BM_RCR_VERB_BUFCOUNT_MASK)));
/* increment the producer count and capture it for SYNC */
rcr_poll = ++p_BmPortal->rcrProd;
if ((flags & BMAN_RELEASE_FLAG_WAIT_SYNC) ==
BMAN_RELEASE_FLAG_WAIT_SYNC)
rel_set_thresh(p_BmPortal, 1);
PUNLOCK(p_BmPortal);
if ((flags & BMAN_RELEASE_FLAG_WAIT_SYNC) !=
BMAN_RELEASE_FLAG_WAIT_SYNC)
return;
rel_completed(p_BmPortal, rcr_poll);
}
/****************************************/
/* Inter-Module functions */
/****************************************/
/**
* bman_release - Release buffer(s) to the buffer pool
* @p_BmPool: the buffer pool object to release to
* @bufs: an array of buffers to release
* @num: the number of buffers in @bufs (1-8)
* @flags: bit-mask of BMAN_RELEASE_FLAG_*** options
*
* Adds the given buffers to RCR entries. If the portal @p_BmPortal was created with the
* "COMPACT" flag, then it will be using a compaction algorithm to improve
* utilization of RCR. As such, these buffers may join an existing ring entry
* and/or it may not be issued right away so as to allow future releases to join
* the same ring entry. Use the BMAN_RELEASE_FLAG_NOW flag to override this
* behavior by committing the RCR entry (or entries) right away. If the RCR
* ring is full, the function will return -EBUSY unless BMAN_RELEASE_FLAG_WAIT
* is selected, in which case it will sleep waiting for space to become
* available in RCR. If the function receives a signal before such time (and
* BMAN_RELEASE_FLAG_WAIT_INT is set), the function returns -EINTR. Otherwise,
* it returns zero.
*/
t_Error BmPortalRelease(t_Handle h_BmPortal,
uint8_t bpid,
struct bm_buffer *bufs,
uint8_t num,
uint32_t flags)
{
t_BmPortal *p_BmPortal = (t_BmPortal *)h_BmPortal;
struct bm_rcr_entry *r;
uint8_t i;
SANITY_CHECK_RETURN_ERROR(p_BmPortal, E_INVALID_HANDLE);
/* TODO: I'm ignoring BMAN_PORTAL_FLAG_COMPACT for now. */
r = try_rel_start(p_BmPortal);
if (!r) {
if (flags & BMAN_RELEASE_FLAG_WAIT) {
t_Error ret = wait_rel_start(p_BmPortal, &r, flags);
if (ret)
return ret;
} else
return ERROR_CODE(E_BUSY);
ASSERT_COND(r != NULL);
}
r->bpid = bpid;
for (i = 0; i < num; i++) {
r->bufs[i].hi = bufs[i].hi;
r->bufs[i].lo = bufs[i].lo;
}
/* Issue the release command and wait for sync if requested. NB: the
* commit can't fail, only waiting can. Don't propagate any failure if a
* signal arrives, otherwise the caller can't distinguish whether the
* release was issued or not. Code for user-space can check
* signal_pending() after we return. */
rel_commit(p_BmPortal, flags, num);
return E_OK;
}
uint8_t BmPortalAcquire(t_Handle h_BmPortal,
uint8_t bpid,
struct bm_buffer *bufs,
uint8_t num)
{
t_BmPortal *p_BmPortal = (t_BmPortal *)h_BmPortal;
struct bm_mc_command *mcc;
struct bm_mc_result *mcr;
uint8_t ret = 0;
SANITY_CHECK_RETURN_VALUE(p_BmPortal, E_INVALID_HANDLE, 0);
NCSW_PLOCK(p_BmPortal);
mcc = bm_mc_start(p_BmPortal->p_BmPortalLow);
mcc->acquire.bpid = bpid;
bm_mc_commit(p_BmPortal->p_BmPortalLow,
(uint8_t)(BM_MCC_VERB_CMD_ACQUIRE |
(num & BM_MCC_VERB_ACQUIRE_BUFCOUNT)));
while (!(mcr = bm_mc_result(p_BmPortal->p_BmPortalLow))) ;
ret = num = (uint8_t)(mcr->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT);
ASSERT_COND(num <= 8);
while (num--) {
bufs[num].bpid = bpid;
bufs[num].hi = mcr->acquire.bufs[num].hi;
bufs[num].lo = mcr->acquire.bufs[num].lo;
}
PUNLOCK(p_BmPortal);
return ret;
}
t_Error BmPortalQuery(t_Handle h_BmPortal, struct bman_depletion *p_Pools, bool depletion)
{
t_BmPortal *p_BmPortal = (t_BmPortal *)h_BmPortal;
struct bm_mc_result *mcr;
SANITY_CHECK_RETURN_ERROR(p_BmPortal, E_INVALID_HANDLE);
NCSW_PLOCK(p_BmPortal);
bm_mc_start(p_BmPortal->p_BmPortalLow);
bm_mc_commit(p_BmPortal->p_BmPortalLow, BM_MCC_VERB_CMD_QUERY);
while (!(mcr = bm_mc_result(p_BmPortal->p_BmPortalLow))) ;
if (depletion)
*p_Pools = mcr->query.ds.state;
else
*p_Pools = mcr->query.as.state;
PUNLOCK(p_BmPortal);
return E_OK;
}
/****************************************/
/* API Init unit functions */
/****************************************/
t_Handle BM_PORTAL_Config(t_BmPortalParam *p_BmPortalParam)
{
t_BmPortal *p_BmPortal;
SANITY_CHECK_RETURN_VALUE(p_BmPortalParam, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_BmPortalParam->h_Bm, E_INVALID_HANDLE, NULL);
p_BmPortal = (t_BmPortal *)XX_Malloc(sizeof(t_BmPortal));
if (!p_BmPortal)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Bm Portal obj!!!"));
return NULL;
}
memset(p_BmPortal, 0, sizeof(t_BmPortal));
p_BmPortal->p_BmPortalLow = (struct bm_portal *)XX_Malloc(sizeof(struct bm_portal));
if (!p_BmPortal->p_BmPortalLow)
{
XX_Free(p_BmPortal);
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Low bm portal obj!!!"));
return NULL;
}
memset(p_BmPortal->p_BmPortalLow, 0, sizeof(struct bm_portal));
p_BmPortal->p_BmPortalDriverParams = (t_BmPortalDriverParams *)XX_Malloc(sizeof(t_BmPortalDriverParams));
if (!p_BmPortal->p_BmPortalDriverParams)
{
XX_Free(p_BmPortal);
XX_Free(p_BmPortal->p_BmPortalLow);
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Bm Portal driver parameters"));
return NULL;
}
memset(p_BmPortal->p_BmPortalDriverParams, 0, sizeof(t_BmPortalDriverParams));
p_BmPortal->p_BmPortalLow->addr.addr_ce = UINT_TO_PTR(p_BmPortalParam->ceBaseAddress);
p_BmPortal->p_BmPortalLow->addr.addr_ci = UINT_TO_PTR(p_BmPortalParam->ciBaseAddress);
p_BmPortal->cpu = (int)p_BmPortalParam->swPortalId;
p_BmPortal->irq = p_BmPortalParam->irq;
p_BmPortal->h_Bm = p_BmPortalParam->h_Bm;
p_BmPortal->p_BmPortalDriverParams->hwExtStructsMemAttr = DEFAULT_memAttr;
bman_depletion_fill(&p_BmPortal->p_BmPortalDriverParams->mask);
return p_BmPortal;
}
t_Error BM_PORTAL_Init(t_Handle h_BmPortal)
{
t_BmPortal *p_BmPortal = (t_BmPortal *)h_BmPortal;
uint32_t flags;
SANITY_CHECK_RETURN_ERROR(p_BmPortal, E_INVALID_HANDLE);
flags = (uint32_t)((p_BmPortal->irq != NO_IRQ) ? BMAN_PORTAL_FLAG_IRQ : 0);
flags |= ((p_BmPortal->p_BmPortalDriverParams->hwExtStructsMemAttr & MEMORY_ATTR_CACHEABLE) ?
BMAN_PORTAL_FLAG_CACHE : 0);
if (bman_create_portal(p_BmPortal,flags,&p_BmPortal->p_BmPortalDriverParams->mask)!=E_OK)
{
BM_PORTAL_Free(p_BmPortal);
RETURN_ERROR(MAJOR, E_NULL_POINTER, ("create portal failed"));
}
BmSetPortalHandle(p_BmPortal->h_Bm, (t_Handle)p_BmPortal, (e_DpaaSwPortal)p_BmPortal->cpu);
XX_Free(p_BmPortal->p_BmPortalDriverParams);
p_BmPortal->p_BmPortalDriverParams = NULL;
DBG(TRACE,("Bman-Portal (%d) @ %p:%p\n",
p_BmPortal->cpu,
p_BmPortal->p_BmPortalLow->addr.addr_ce,
p_BmPortal->p_BmPortalLow->addr.addr_ci
));
DBG(TRACE,("Bman-Portal (%d) @ 0x%016llx:0x%016llx",
p_BmPortal->cpu,
(uint64_t)XX_VirtToPhys(p_BmPortal->p_BmPortalLow->addr.addr_ce),
(uint64_t)XX_VirtToPhys(p_BmPortal->p_BmPortalLow->addr.addr_ci)
));
return E_OK;
}
t_Error BM_PORTAL_Free(t_Handle h_BmPortal)
{
t_BmPortal *p_BmPortal = (t_BmPortal *)h_BmPortal;
if (!p_BmPortal)
return ERROR_CODE(E_INVALID_HANDLE);
BmSetPortalHandle(p_BmPortal->h_Bm, NULL, (e_DpaaSwPortal)p_BmPortal->cpu);
bman_destroy_portal(p_BmPortal);
XX_Free(p_BmPortal);
return E_OK;
}
t_Error BM_PORTAL_ConfigMemAttr(t_Handle h_BmPortal, uint32_t hwExtStructsMemAttr)
{
t_BmPortal *p_BmPortal = (t_BmPortal *)h_BmPortal;
SANITY_CHECK_RETURN_ERROR(p_BmPortal, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_BmPortal->p_BmPortalDriverParams, E_INVALID_HANDLE);
p_BmPortal->p_BmPortalDriverParams->hwExtStructsMemAttr = hwExtStructsMemAttr;
return E_OK;
}

494
sys/contrib/ncsw/Peripherals/BM/bman_low.c Normal file
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@ -0,0 +1,494 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File bman_low.c
@Description BM low-level implementation
*//***************************************************************************/
#include "std_ext.h"
#include "core_ext.h"
#include "xx_ext.h"
#include "error_ext.h"
#include "bman_private.h"
/***************************/
/* Portal register assists */
/***************************/
/* Cache-inhibited register offsets */
#define REG_RCR_PI_CINH (void *)0x0000
#define REG_RCR_CI_CINH (void *)0x0004
#define REG_RCR_ITR (void *)0x0008
#define REG_CFG (void *)0x0100
#define REG_SCN(n) ((void *)(0x0200 + ((n) << 2)))
#define REG_ISR (void *)0x0e00
#define REG_IER (void *)0x0e04
#define REG_ISDR (void *)0x0e08
#define REG_IIR (void *)0x0e0c
/* Cache-enabled register offsets */
#define CL_CR (void *)0x0000
#define CL_RR0 (void *)0x0100
#define CL_RR1 (void *)0x0140
#define CL_RCR (void *)0x1000
#define CL_RCR_PI_CENA (void *)0x3000
#define CL_RCR_CI_CENA (void *)0x3100
/* The h/w design requires mappings to be size-aligned so that "add"s can be
* reduced to "or"s. The primitives below do the same for s/w. */
static __inline__ void *ptr_ADD(void *a, void *b)
{
return (void *)((uintptr_t)a + (uintptr_t)b);
}
/* Bitwise-OR two pointers */
static __inline__ void *ptr_OR(void *a, void *b)
{
return (void *)((uintptr_t)a | (uintptr_t)b);
}
/* Cache-inhibited register access */
static __inline__ uint32_t __bm_in(struct bm_addr *bm, void *offset)
{
uint32_t *tmp = (uint32_t *)ptr_ADD(bm->addr_ci, offset);
return GET_UINT32(*tmp);
}
static __inline__ void __bm_out(struct bm_addr *bm, void *offset, uint32_t val)
{
uint32_t *tmp = (uint32_t *)ptr_ADD(bm->addr_ci, offset);
WRITE_UINT32(*tmp, val);
}
#define bm_in(reg) __bm_in(&portal->addr, REG_##reg)
#define bm_out(reg, val) __bm_out(&portal->addr, REG_##reg, val)
/* Convert 'n' cachelines to a pointer value for bitwise OR */
#define bm_cl(n) (void *)((n) << 6)
/* Cache-enabled (index) register access */
static __inline__ void __bm_cl_touch_ro(struct bm_addr *bm, void *offset)
{
dcbt_ro(ptr_ADD(bm->addr_ce, offset));
}
static __inline__ void __bm_cl_touch_rw(struct bm_addr *bm, void *offset)
{
dcbt_rw(ptr_ADD(bm->addr_ce, offset));
}
static __inline__ uint32_t __bm_cl_in(struct bm_addr *bm, void *offset)
{
uint32_t *tmp = (uint32_t *)ptr_ADD(bm->addr_ce, offset);
return GET_UINT32(*tmp);
}
static __inline__ void __bm_cl_out(struct bm_addr *bm, void *offset, uint32_t val)
{
uint32_t *tmp = (uint32_t *)ptr_ADD(bm->addr_ce, offset);
WRITE_UINT32(*tmp, val);
dcbf(tmp);
}
static __inline__ void __bm_cl_invalidate(struct bm_addr *bm, void *offset)
{
dcbi(ptr_ADD(bm->addr_ce, offset));
}
#define bm_cl_touch_ro(reg) __bm_cl_touch_ro(&portal->addr, CL_##reg##_CENA)
#define bm_cl_touch_rw(reg) __bm_cl_touch_rw(&portal->addr, CL_##reg##_CENA)
#define bm_cl_in(reg) __bm_cl_in(&portal->addr, CL_##reg##_CENA)
#define bm_cl_out(reg, val) __bm_cl_out(&portal->addr, CL_##reg##_CENA, val)
#define bm_cl_invalidate(reg) __bm_cl_invalidate(&portal->addr, CL_##reg##_CENA)
/* Cyclic helper for rings. TODO: once we are able to do fine-grain perf
* analysis, look at using the "extra" bit in the ring index registers to avoid
* cyclic issues. */
static __inline__ uint8_t cyc_diff(uint8_t ringsize, uint8_t first, uint8_t last)
{
/* 'first' is included, 'last' is excluded */
if (first <= last)
return (uint8_t)(last - first);
return (uint8_t)(ringsize + last - first);
}
/* --------------- */
/* --- RCR API --- */
/* It's safer to code in terms of the 'rcr' object than the 'portal' object,
* because the latter runs the risk of copy-n-paste errors from other code where
* we could manipulate some other structure within 'portal'. */
/* #define RCR_API_START() register struct bm_rcr *rcr = &portal->rcr */
/* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
#define RCR_CARRYCLEAR(p) \
(void *)((uintptr_t)(p) & (~(uintptr_t)(BM_RCR_SIZE << 6)))
/* Bit-wise logic to convert a ring pointer to a ring index */
static __inline__ uint8_t RCR_PTR2IDX(struct bm_rcr_entry *e)
{
return (uint8_t)(((uint32_t)e >> 6) & (BM_RCR_SIZE - 1));
}
/* Increment the 'cursor' ring pointer, taking 'vbit' into account */
static __inline__ void RCR_INC(struct bm_rcr *rcr)
{
/* NB: this is odd-looking, but experiments show that it generates
* fast code with essentially no branching overheads. We increment to
* the next RCR pointer and handle overflow and 'vbit'. */
struct bm_rcr_entry *partial = rcr->cursor + 1;
rcr->cursor = RCR_CARRYCLEAR(partial);
if (partial != rcr->cursor)
rcr->vbit ^= BM_RCR_VERB_VBIT;
}
t_Error bm_rcr_init(struct bm_portal *portal,
e_BmPortalProduceMode pmode,
e_BmPortalRcrConsumeMode cmode)
{
register struct bm_rcr *rcr = &portal->rcr;
uint32_t cfg;
uint8_t pi;
rcr->ring = ptr_ADD(portal->addr.addr_ce, CL_RCR);
rcr->ci = (uint8_t)(bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1));
pi = (uint8_t)(bm_in(RCR_PI_CINH) & (BM_RCR_SIZE - 1));
rcr->cursor = rcr->ring + pi;
rcr->vbit = (uint8_t)((bm_in(RCR_PI_CINH) & BM_RCR_SIZE) ? BM_RCR_VERB_VBIT : 0);
rcr->available = (uint8_t)(BM_RCR_SIZE - 1 - cyc_diff(BM_RCR_SIZE, rcr->ci, pi));
rcr->ithresh = (uint8_t)bm_in(RCR_ITR);
#ifdef BM_CHECKING
rcr->busy = 0;
rcr->pmode = pmode;
rcr->cmode = cmode;
#else
UNUSED(cmode);
#endif /* BM_CHECKING */
cfg = (bm_in(CFG) & 0xffffffe0) | (pmode & 0x3); /* BCSP_CFG::RPM */
bm_out(CFG, cfg);
return 0;
}
void bm_rcr_finish(struct bm_portal *portal)
{
register struct bm_rcr *rcr = &portal->rcr;
uint8_t pi = (uint8_t)(bm_in(RCR_PI_CINH) & (BM_RCR_SIZE - 1));
uint8_t ci = (uint8_t)(bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1));
ASSERT_COND(!rcr->busy);
if (pi != RCR_PTR2IDX(rcr->cursor))
REPORT_ERROR(WARNING, E_INVALID_STATE, ("losing uncommitted RCR entries"));
if (ci != rcr->ci)
REPORT_ERROR(WARNING, E_INVALID_STATE, ("missing existing RCR completions"));
if (rcr->ci != RCR_PTR2IDX(rcr->cursor))
REPORT_ERROR(WARNING, E_INVALID_STATE, ("RCR destroyed unquiesced"));
}
struct bm_rcr_entry *bm_rcr_start(struct bm_portal *portal)
{
register struct bm_rcr *rcr = &portal->rcr;
ASSERT_COND(!rcr->busy);
if (!rcr->available)
return NULL;
#ifdef BM_CHECKING
rcr->busy = 1;
#endif /* BM_CHECKING */
dcbz_64(rcr->cursor);
return rcr->cursor;
}
void bm_rcr_abort(struct bm_portal *portal)
{
register struct bm_rcr *rcr = &portal->rcr;
ASSERT_COND(rcr->busy);
#ifdef BM_CHECKING
rcr->busy = 0;
#else
UNUSED(rcr);
#endif /* BM_CHECKING */
}
struct bm_rcr_entry *bm_rcr_pend_and_next(struct bm_portal *portal, uint8_t myverb)
{
register struct bm_rcr *rcr = &portal->rcr;
ASSERT_COND(rcr->busy);
ASSERT_COND(rcr->pmode != e_BmPortalPVB);
if (rcr->available == 1)
return NULL;
rcr->cursor->__dont_write_directly__verb = (uint8_t)(myverb | rcr->vbit);
dcbf_64(rcr->cursor);
RCR_INC(rcr);
rcr->available--;
dcbz_64(rcr->cursor);
return rcr->cursor;
}
void bm_rcr_pci_commit(struct bm_portal *portal, uint8_t myverb)
{
register struct bm_rcr *rcr = &portal->rcr;
ASSERT_COND(rcr->busy);
ASSERT_COND(rcr->pmode == e_BmPortalPCI);
rcr->cursor->__dont_write_directly__verb = (uint8_t)(myverb | rcr->vbit);
RCR_INC(rcr);
rcr->available--;
hwsync();
bm_out(RCR_PI_CINH, RCR_PTR2IDX(rcr->cursor));
#ifdef BM_CHECKING
rcr->busy = 0;
#endif /* BM_CHECKING */
}
void bm_rcr_pce_prefetch(struct bm_portal *portal)
{
ASSERT_COND(((struct bm_rcr *)&portal->rcr)->pmode == e_BmPortalPCE);
bm_cl_invalidate(RCR_PI);
bm_cl_touch_rw(RCR_PI);
}
void bm_rcr_pce_commit(struct bm_portal *portal, uint8_t myverb)
{
register struct bm_rcr *rcr = &portal->rcr;
ASSERT_COND(rcr->busy);
ASSERT_COND(rcr->pmode == e_BmPortalPCE);
rcr->cursor->__dont_write_directly__verb = (uint8_t)(myverb | rcr->vbit);
RCR_INC(rcr);
rcr->available--;
lwsync();
bm_cl_out(RCR_PI, RCR_PTR2IDX(rcr->cursor));
#ifdef BM_CHECKING
rcr->busy = 0;
#endif /* BM_CHECKING */
}
void bm_rcr_pvb_commit(struct bm_portal *portal, uint8_t myverb)
{
register struct bm_rcr *rcr = &portal->rcr;
struct bm_rcr_entry *rcursor;
ASSERT_COND(rcr->busy);
ASSERT_COND(rcr->pmode == e_BmPortalPVB);
lwsync();
rcursor = rcr->cursor;
rcursor->__dont_write_directly__verb = (uint8_t)(myverb | rcr->vbit);
dcbf_64(rcursor);
RCR_INC(rcr);
rcr->available--;
#ifdef BM_CHECKING
rcr->busy = 0;
#endif /* BM_CHECKING */
}
uint8_t bm_rcr_cci_update(struct bm_portal *portal)
{
register struct bm_rcr *rcr = &portal->rcr;
uint8_t diff, old_ci = rcr->ci;
ASSERT_COND(rcr->cmode == e_BmPortalRcrCCI);
rcr->ci = (uint8_t)(bm_in(RCR_CI_CINH) & (BM_RCR_SIZE - 1));
diff = cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci);
rcr->available += diff;
return diff;
}
void bm_rcr_cce_prefetch(struct bm_portal *portal)
{
ASSERT_COND(((struct bm_rcr *)&portal->rcr)->cmode == e_BmPortalRcrCCE);
bm_cl_touch_ro(RCR_CI);
}
uint8_t bm_rcr_cce_update(struct bm_portal *portal)
{
register struct bm_rcr *rcr = &portal->rcr;
uint8_t diff, old_ci = rcr->ci;
ASSERT_COND(rcr->cmode == e_BmPortalRcrCCE);
rcr->ci = (uint8_t)(bm_cl_in(RCR_CI) & (BM_RCR_SIZE - 1));
bm_cl_invalidate(RCR_CI);
diff = cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci);
rcr->available += diff;
return diff;
}
uint8_t bm_rcr_get_ithresh(struct bm_portal *portal)
{
register struct bm_rcr *rcr = &portal->rcr;
return rcr->ithresh;
}
void bm_rcr_set_ithresh(struct bm_portal *portal, uint8_t ithresh)
{
register struct bm_rcr *rcr = &portal->rcr;
rcr->ithresh = ithresh;
bm_out(RCR_ITR, ithresh);
}
uint8_t bm_rcr_get_avail(struct bm_portal *portal)
{
register struct bm_rcr *rcr = &portal->rcr;
return rcr->available;
}
uint8_t bm_rcr_get_fill(struct bm_portal *portal)
{
register struct bm_rcr *rcr = &portal->rcr;
return (uint8_t)(BM_RCR_SIZE - 1 - rcr->available);
}
/* ------------------------------ */
/* --- Management command API --- */
/* It's safer to code in terms of the 'mc' object than the 'portal' object,
* because the latter runs the risk of copy-n-paste errors from other code where
* we could manipulate some other structure within 'portal'. */
/* #define MC_API_START() register struct bm_mc *mc = &portal->mc */
t_Error bm_mc_init(struct bm_portal *portal)
{
register struct bm_mc *mc = &portal->mc;
mc->cr = ptr_ADD(portal->addr.addr_ce, CL_CR);
mc->rr = ptr_ADD(portal->addr.addr_ce, CL_RR0);
mc->rridx = (uint8_t)((mc->cr->__dont_write_directly__verb & BM_MCC_VERB_VBIT) ?
0 : 1);
mc->vbit = (uint8_t)(mc->rridx ? BM_MCC_VERB_VBIT : 0);
#ifdef BM_CHECKING
mc->state = mc_idle;
#endif /* BM_CHECKING */
return 0;
}
void bm_mc_finish(struct bm_portal *portal)
{
register struct bm_mc *mc = &portal->mc;
ASSERT_COND(mc->state == mc_idle);
#ifdef BM_CHECKING
if (mc->state != mc_idle)
REPORT_ERROR(WARNING, E_INVALID_STATE, ("Losing incomplete MC command"));
#else
UNUSED(mc);
#endif /* BM_CHECKING */
}
struct bm_mc_command *bm_mc_start(struct bm_portal *portal)
{
register struct bm_mc *mc = &portal->mc;
ASSERT_COND(mc->state == mc_idle);
#ifdef BM_CHECKING
mc->state = mc_user;
#endif /* BM_CHECKING */
dcbz_64(mc->cr);
return mc->cr;
}
void bm_mc_abort(struct bm_portal *portal)
{
register struct bm_mc *mc = &portal->mc;
ASSERT_COND(mc->state == mc_user);
#ifdef BM_CHECKING
mc->state = mc_idle;
#else
UNUSED(mc);
#endif /* BM_CHECKING */
}
void bm_mc_commit(struct bm_portal *portal, uint8_t myverb)
{
register struct bm_mc *mc = &portal->mc;
ASSERT_COND(mc->state == mc_user);
lwsync();
mc->cr->__dont_write_directly__verb = (uint8_t)(myverb | mc->vbit);
dcbf_64(mc->cr);
dcbit_ro(mc->rr + mc->rridx);
#ifdef BM_CHECKING
mc->state = mc_hw;
#endif /* BM_CHECKING */
}
struct bm_mc_result *bm_mc_result(struct bm_portal *portal)
{
register struct bm_mc *mc = &portal->mc;
struct bm_mc_result *rr = mc->rr + mc->rridx;
ASSERT_COND(mc->state == mc_hw);
/* The inactive response register's verb byte always returns zero until
* its command is submitted and completed. This includes the valid-bit,
* in case you were wondering... */
if (!rr->verb) {
dcbit_ro(rr);
return NULL;
}
mc->rridx ^= 1;
mc->vbit ^= BM_MCC_VERB_VBIT;
#ifdef BM_CHECKING
mc->state = mc_idle;
#endif /* BM_CHECKING */
return rr;
}
/* ------------------------------------- */
/* --- Portal interrupt register API --- */
#define SCN_REG(bpid) REG_SCN((bpid) / 32)
#define SCN_BIT(bpid) (0x80000000 >> (bpid & 31))
void bm_isr_bscn_mask(struct bm_portal *portal, uint8_t bpid, int enable)
{
uint32_t val;
ASSERT_COND(bpid < BM_MAX_NUM_OF_POOLS);
/* REG_SCN for bpid=0..31, REG_SCN+4 for bpid=32..63 */
val = __bm_in(&portal->addr, SCN_REG(bpid));
if (enable)
val |= SCN_BIT(bpid);
else
val &= ~SCN_BIT(bpid);
__bm_out(&portal->addr, SCN_REG(bpid), val);
}
uint32_t __bm_isr_read(struct bm_portal *portal, enum bm_isr_reg n)
{
return __bm_in(&portal->addr, PTR_MOVE(REG_ISR, (n << 2)));
}
void __bm_isr_write(struct bm_portal *portal, enum bm_isr_reg n, uint32_t val)
{
__bm_out(&portal->addr, PTR_MOVE(REG_ISR, (n << 2)), val);
}

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File bman_private.h
@Description BM header
*//***************************************************************************/
#ifndef __BMAN_PRIV_H
#define __BMAN_PRIV_H
#include "fsl_bman.h"
#define __ERR_MODULE__ MODULE_BM
#if defined(DEBUG) || !defined(DISABLE_ASSERTIONS)
/* Optionally compile-in assertion-checking */
#define BM_CHECKING
#endif /* defined(DEBUG) || ... */
/* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers
* and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or
* execution reordering with respect to other code/instructions that manipulate
* the same cacheline. */
#ifdef CORE_E500MC
#if defined(_DIAB_TOOL)
#define hwsync() \
do { \
__asm__ __volatile__ ("sync"); \
} while(0)
#define lwsync() \
do { \
__asm__ __volatile__ ("lwsync"); \
} while(0)
__asm__ __volatile__ void dcbf (volatile void * addr)
{
%reg addr
dcbf r0, addr
}
__asm__ __volatile__ void dcbt_ro (volatile void * addr)
{
%reg addr
dcbt r0, addr
}
__asm__ __volatile__ void dcbt_rw (volatile void * addr)
{
%reg addr
dcbtst r0, addr
}
__asm__ __volatile__ void dcbzl (volatile void * addr)
{
%reg addr
dcbzl r0, addr
}
#define dcbz_64(p) \
do { \
dcbzl(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbt_ro(p); \
} while (0)
#else /* GNU C */
#define hwsync() \
do { \
__asm__ __volatile__ ("sync" : : : "memory"); \
} while(0)
#define lwsync() \
do { \
__asm__ __volatile__ ("lwsync" : : : "memory"); \
} while(0)
#define dcbf(addr) \
do { \
__asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \
} while(0)
#define dcbt_ro(addr) \
do { \
__asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \
} while(0)
#define dcbt_rw(addr) \
do { \
__asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \
} while(0)
#define dcbzl(p) \
do { \
__asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \
} while(0)
#define dcbz_64(p) \
do { \
dcbzl(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbt_ro(p); \
} while (0)
#endif /* _DIAB_TOOL */
#else
#define hwsync CORE_MemoryBarrier
#define lwsync hwsync
#define dcbf(p) \
do { \
__asm__ __volatile__ ("dcbf 0,%0" : : "r" (p)); \
} while(0)
#define dcbt_ro(p) \
do { \
__asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \
lwsync(); \
} while(0)
#define dcbt_rw(p) \
do { \
__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \
} while(0)
#define dcbz(p) \
do { \
__asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \
} while (0)
#define dcbz_64(p) \
do { \
dcbz((uint32_t)p + 32); \
dcbz(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf((uint32_t)p + 32); \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbi((uint32_t)p + 32); \
dcbt_ro(p); \
dcbt_ro((uint32_t)p + 32); \
} while (0)
#endif /* CORE_E500MC */
#define dcbi(p) dcbf(p)
struct bm_addr {
void *addr_ce; /* cache-enabled */
void *addr_ci; /* cache-inhibited */
};
/* RCR state */
struct bm_rcr {
struct bm_rcr_entry *ring, *cursor;
uint8_t ci, available, ithresh, vbit;
#ifdef BM_CHECKING
uint32_t busy;
e_BmPortalProduceMode pmode;
e_BmPortalRcrConsumeMode cmode;
#endif /* BM_CHECKING */
};
/* MC state */
struct bm_mc {
struct bm_mc_command *cr;
struct bm_mc_result *rr;
uint8_t rridx, vbit;
#ifdef BM_CHECKING
enum {
/* Can only be _mc_start()ed */
mc_idle,
/* Can only be _mc_commit()ed or _mc_abort()ed */
mc_user,
/* Can only be _mc_retry()ed */
mc_hw
} state;
#endif /* BM_CHECKING */
};
/********************/
/* Portal structure */
/********************/
struct bm_portal {
struct bm_addr addr;
struct bm_rcr rcr;
struct bm_mc mc;
};
#endif /* __BMAN_PRIV_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File fsl_bman.h
@Description BM header
*//***************************************************************************/
#ifndef __FSL_BMAN_H
#define __FSL_BMAN_H
#include "std_ext.h"
/*************************************************/
/* BMan s/w corenet portal, low-level i/face */
/*************************************************/
typedef enum {
e_BmPortalPCI = 0, /* PI index, cache-inhibited */
e_BmPortalPCE, /* PI index, cache-enabled */
e_BmPortalPVB /* valid-bit */
} e_BmPortalProduceMode;
typedef enum {
e_BmPortalRcrCCI = 0, /* CI index, cache-inhibited */
e_BmPortalRcrCCE /* CI index, cache-enabled */
} e_BmPortalRcrConsumeMode;
/* Portal constants */
#define BM_RCR_SIZE 8
/* Hardware constants */
enum bm_isr_reg {
bm_isr_status = 0,
bm_isr_enable = 1,
bm_isr_disable = 2,
bm_isr_inhibit = 3
};
/* Represents s/w corenet portal mapped data structures */
struct bm_rcr_entry; /* RCR (Release Command Ring) entries */
struct bm_mc_command; /* MC (Management Command) command */
struct bm_mc_result; /* MC result */
/* This type represents a s/w corenet portal space, and is used for creating the
* portal objects within it (RCR, etc) */
struct bm_portal;
/* This wrapper represents a bit-array for the depletion state of the 64 Bman
* buffer pools. */
struct bman_depletion {
uint32_t __state[2];
};
#define __bmdep_word(x) ((x) >> 5)
#define __bmdep_shift(x) ((x) & 0x1f)
#define __bmdep_bit(x) (0x80000000 >> __bmdep_shift(x))
static __inline__ void bman_depletion_init(struct bman_depletion *c)
{
c->__state[0] = c->__state[1] = 0;
}
static __inline__ void bman_depletion_fill(struct bman_depletion *c)
{
c->__state[0] = c->__state[1] = (uint32_t)~0;
}
static __inline__ int bman_depletion_get(const struct bman_depletion *c, uint8_t bpid)
{
return (int)(c->__state[__bmdep_word(bpid)] & __bmdep_bit(bpid));
}
static __inline__ void bman_depletion_set(struct bman_depletion *c, uint8_t bpid)
{
c->__state[__bmdep_word(bpid)] |= __bmdep_bit(bpid);
}
static __inline__ void bman_depletion_unset(struct bman_depletion *c, uint8_t bpid)
{
c->__state[__bmdep_word(bpid)] &= ~__bmdep_bit(bpid);
}
/* ------------------------------ */
/* --- Portal enumeration API --- */
/* ------------------------------ */
/* --- Buffer pool allocation --- */
#define BM_POOL_THRESH_SW_ENTER 0
#define BM_POOL_THRESH_SW_EXIT 1
#define BM_POOL_THRESH_HW_ENTER 2
#define BM_POOL_THRESH_HW_EXIT 3
/* --------------- */
/* --- RCR API --- */
/* Create/destroy */
t_Error bm_rcr_init(struct bm_portal *portal,
e_BmPortalProduceMode pmode,
e_BmPortalRcrConsumeMode cmode);
void bm_rcr_finish(struct bm_portal *portal);
/* Start/abort RCR entry */
struct bm_rcr_entry *bm_rcr_start(struct bm_portal *portal);
void bm_rcr_abort(struct bm_portal *portal);
/* For PI modes only. This presumes a started but uncommitted RCR entry. If
* there's no more room in the RCR, this function returns NULL. Otherwise it
* returns the next RCR entry and increments an internal PI counter without
* flushing it to h/w. */
struct bm_rcr_entry *bm_rcr_pend_and_next(struct bm_portal *portal, uint8_t myverb);
/* Commit RCR entries, including pending ones (aka "write PI") */
void bm_rcr_pci_commit(struct bm_portal *portal, uint8_t myverb);
void bm_rcr_pce_prefetch(struct bm_portal *portal);
void bm_rcr_pce_commit(struct bm_portal *portal, uint8_t myverb);
void bm_rcr_pvb_commit(struct bm_portal *portal, uint8_t myverb);
/* Track h/w consumption. Returns non-zero if h/w had consumed previously
* unconsumed RCR entries. */
uint8_t bm_rcr_cci_update(struct bm_portal *portal);
void bm_rcr_cce_prefetch(struct bm_portal *portal);
uint8_t bm_rcr_cce_update(struct bm_portal *portal);
/* Returns the number of available RCR entries */
uint8_t bm_rcr_get_avail(struct bm_portal *portal);
/* Returns the number of unconsumed RCR entries */
uint8_t bm_rcr_get_fill(struct bm_portal *portal);
/* Read/write the RCR interrupt threshold */
uint8_t bm_rcr_get_ithresh(struct bm_portal *portal);
void bm_rcr_set_ithresh(struct bm_portal *portal, uint8_t ithresh);
/* ------------------------------ */
/* --- Management command API --- */
/* Create/destroy */
t_Error bm_mc_init(struct bm_portal *portal);
void bm_mc_finish(struct bm_portal *portal);
/* Start/abort mgmt command */
struct bm_mc_command *bm_mc_start(struct bm_portal *portal);
void bm_mc_abort(struct bm_portal *portal);
/* Writes 'verb' with appropriate 'vbit'. Invalidates and pre-fetches the
* response. */
void bm_mc_commit(struct bm_portal *portal, uint8_t myverb);
/* Poll for result. If NULL, invalidates and prefetches for the next call. */
struct bm_mc_result *bm_mc_result(struct bm_portal *portal);
/* ------------------------------------- */
/* --- Portal interrupt register API --- */
/* For a quick explanation of the Bman interrupt model, see the comments in the
* equivalent section of the qman_portal.h header.
*/
/* Create/destroy */
t_Error bm_isr_init(struct bm_portal *portal);
void bm_isr_finish(struct bm_portal *portal);
/* BSCN masking is a per-portal configuration */
void bm_isr_bscn_mask(struct bm_portal *portal, uint8_t bpid, int enable);
/* Used by all portal interrupt registers except 'inhibit' */
#define BM_PIRQ_RCRI 0x00000002 /* RCR Ring (below threshold) */
#define BM_PIRQ_BSCN 0x00000001 /* Buffer depletion State Change */
/* These are bm_<reg>_<verb>(). So for example, bm_disable_write() means "write
* the disable register" rather than "disable the ability to write". */
#define bm_isr_status_read(bm) __bm_isr_read(bm, bm_isr_status)
#define bm_isr_status_clear(bm, m) __bm_isr_write(bm, bm_isr_status, m)
#define bm_isr_enable_read(bm) __bm_isr_read(bm, bm_isr_enable)
#define bm_isr_enable_write(bm, v) __bm_isr_write(bm, bm_isr_enable, v)
#define bm_isr_disable_read(bm) __bm_isr_read(bm, bm_isr_disable)
#define bm_isr_disable_write(bm, v) __bm_isr_write(bm, bm_isr_disable, v)
#define bm_isr_inhibit(bm) __bm_isr_write(bm, bm_isr_inhibit, 1)
#define bm_isr_uninhibit(bm) __bm_isr_write(bm, bm_isr_inhibit, 0)
/* Don't use these, use the wrappers above*/
uint32_t __bm_isr_read(struct bm_portal *portal, enum bm_isr_reg n);
void __bm_isr_write(struct bm_portal *portal, enum bm_isr_reg n, uint32_t val);
/* ------------------------------------------------------- */
/* --- Bman data structures (and associated constants) --- */
/* Code-reduction, define a wrapper for 48-bit buffers. In cases where a buffer
* pool id specific to this buffer is needed (BM_RCR_VERB_CMD_BPID_MULTI,
* BM_MCC_VERB_ACQUIRE), the 'bpid' field is used. */
#define BM_RCR_VERB_VBIT 0x80
#define BM_RCR_VERB_CMD_MASK 0x70 /* one of two values; */
#define BM_RCR_VERB_CMD_BPID_SINGLE 0x20
#define BM_RCR_VERB_CMD_BPID_MULTI 0x30
#define BM_RCR_VERB_BUFCOUNT_MASK 0x0f /* values 1..8 */
#define BM_MCC_VERB_VBIT 0x80
#define BM_MCC_VERB_CMD_MASK 0x70 /* where the verb contains; */
#define BM_MCC_VERB_CMD_ACQUIRE 0x10
#define BM_MCC_VERB_CMD_QUERY 0x40
#define BM_MCC_VERB_ACQUIRE_BUFCOUNT 0x0f /* values 1..8 go here */
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
_Packed struct bm_buffer {
volatile uint8_t reserved1;
volatile uint8_t bpid;
volatile uint16_t hi; /* High 16-bits of 48-bit address */
volatile uint32_t lo; /* Low 32-bits of 48-bit address */
} _PackedType;
/* See 1.5.3.5.4: "Release Command" */
_Packed struct bm_rcr_entry {
_Packed union {
_Packed struct {
volatile uint8_t __dont_write_directly__verb;
volatile uint8_t bpid; /* used with BM_RCR_VERB_CMD_BPID_SINGLE */
volatile uint8_t reserved1[62];
} _PackedType;
volatile struct bm_buffer bufs[8];
} _PackedType;
} _PackedType;
/* See 1.5.3.1: "Acquire Command" */
/* See 1.5.3.2: "Query Command" */
_Packed struct bm_mc_command {
volatile uint8_t __dont_write_directly__verb;
_Packed union {
_Packed struct bm_mcc_acquire {
volatile uint8_t bpid;
volatile uint8_t reserved1[62];
} _PackedType acquire;
_Packed struct bm_mcc_query {
volatile uint8_t reserved1[63];
} _PackedType query;
} _PackedType;
} _PackedType;
/* See 1.5.3.3: "Acquire Reponse" */
/* See 1.5.3.4: "Query Reponse" */
_Packed struct bm_mc_result {
_Packed union {
_Packed struct {
volatile uint8_t verb;
volatile uint8_t reserved1[63];
} _PackedType;
_Packed union {
_Packed struct {
volatile uint8_t reserved1;
volatile uint8_t bpid;
volatile uint8_t reserved2[62];
} _PackedType;
volatile struct bm_buffer bufs[8];
} _PackedType acquire;
_Packed struct {
volatile uint8_t reserved1[32];
/* "availability state" and "depletion state" */
_Packed struct {
volatile uint8_t reserved1[8];
/* Access using bman_depletion_***() */
volatile struct bman_depletion state;
} _PackedType as, ds;
} _PackedType query;
} _PackedType;
} _PackedType;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
#define BM_MCR_VERB_VBIT 0x80
#define BM_MCR_VERB_CMD_MASK BM_MCC_VERB_CMD_MASK
#define BM_MCR_VERB_CMD_ACQUIRE BM_MCC_VERB_CMD_ACQUIRE
#define BM_MCR_VERB_CMD_QUERY BM_MCC_VERB_CMD_QUERY
#define BM_MCR_VERB_CMD_ERR_INVALID 0x60
#define BM_MCR_VERB_CMD_ERR_ECC 0x70
#define BM_MCR_VERB_ACQUIRE_BUFCOUNT BM_MCC_VERB_ACQUIRE_BUFCOUNT /* 0..8 */
/* Determine the "availability state" of pool 'p' from a query result 'r' */
#define BM_MCR_QUERY_AVAILABILITY(r,p) bman_depletion_get(&r->query.as.state,p)
/* Determine the "depletion state" of pool 'p' from a query result 'r' */
#define BM_MCR_QUERY_DEPLETION(r,p) bman_depletion_get(&r->query.ds.state,p)
/* Portal and Buffer Pools */
/* ----------------------- */
/* Flags to bman_create_portal() */
#define BMAN_PORTAL_FLAG_IRQ 0x00000001 /* use interrupt handler */
#define BMAN_PORTAL_FLAG_IRQ_FAST 0x00000002 /* ... for fast-path too! */
#define BMAN_PORTAL_FLAG_COMPACT 0x00000004 /* use compaction algorithm */
#define BMAN_PORTAL_FLAG_RECOVER 0x00000008 /* recovery mode */
#define BMAN_PORTAL_FLAG_WAIT 0x00000010 /* wait if RCR is full */
#define BMAN_PORTAL_FLAG_WAIT_INT 0x00000020 /* if wait, interruptible? */
#define BMAN_PORTAL_FLAG_CACHE 0x00000400 /* use cache-able area for rings */
/* Flags to bman_new_pool() */
#define BMAN_POOL_FLAG_NO_RELEASE 0x00000001 /* can't release to pool */
#define BMAN_POOL_FLAG_ONLY_RELEASE 0x00000002 /* can only release to pool */
#define BMAN_POOL_FLAG_DEPLETION 0x00000004 /* track depletion entry/exit */
#define BMAN_POOL_FLAG_DYNAMIC_BPID 0x00000008 /* (de)allocate bpid */
#define BMAN_POOL_FLAG_THRESH 0x00000010 /* set depletion thresholds */
#define BMAN_POOL_FLAG_STOCKPILE 0x00000020 /* stockpile to reduce hw ops */
/* Flags to bman_release() */
#define BMAN_RELEASE_FLAG_WAIT 0x00000001 /* wait if RCR is full */
#define BMAN_RELEASE_FLAG_WAIT_INT 0x00000002 /* if we wait, interruptible? */
#define BMAN_RELEASE_FLAG_WAIT_SYNC 0x00000004 /* if wait, until consumed? */
#define BMAN_RELEASE_FLAG_NOW 0x00000008 /* issue immediate release */
/* Flags to bman_acquire() */
#define BMAN_ACQUIRE_FLAG_STOCKPILE 0x00000001 /* no hw op, stockpile only */
#endif /* __FSL_BMAN_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File dtsec.h
@Description FM dTSEC ...
*//***************************************************************************/
#ifndef __DTSEC_H
#define __DTSEC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "dtsec_mii_acc.h"
#include "fm_mac.h"
#define PEMASK_TSRE 0x00010000
#define IMASK_BREN 0x80000000
#define IMASK_RXCEN 0x40000000
#define IMASK_MSROEN 0x04000000
#define IMASK_GTSCEN 0x02000000
#define IMASK_BTEN 0x01000000
#define IMASK_TXCEN 0x00800000
#define IMASK_TXEEN 0x00400000
#define IMASK_LCEN 0x00040000
#define IMASK_CRLEN 0x00020000
#define IMASK_XFUNEN 0x00010000
#define IMASK_ABRTEN 0x00008000
#define IMASK_IFERREN 0x00004000
#define IMASK_MAGEN 0x00000800
#define IMASK_MMRDEN 0x00000400
#define IMASK_MMWREN 0x00000200
#define IMASK_GRSCEN 0x00000100
#define IMASK_TDPEEN 0x00000002
#define IMASK_RDPEEN 0x00000001
#define EVENTS_MASK ((uint32_t)(IMASK_BREN | \
IMASK_RXCEN | \
IMASK_MSROEN | \
IMASK_GTSCEN | \
IMASK_BTEN | \
IMASK_TXCEN | \
IMASK_TXEEN | \
IMASK_ABRTEN | \
IMASK_LCEN | \
IMASK_CRLEN | \
IMASK_XFUNEN | \
IMASK_IFERREN | \
IMASK_MAGEN | \
IMASK_MMRDEN | \
IMASK_MMWREN | \
IMASK_GRSCEN | \
IMASK_TDPEEN | \
IMASK_RDPEEN))
#define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \
case e_FM_MAC_EX_1G_BAB_RX: \
bitMask = IMASK_BREN; break; \
case e_FM_MAC_EX_1G_RX_CTL: \
bitMask = IMASK_RXCEN; break; \
case e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET: \
bitMask = IMASK_GTSCEN ; break; \
case e_FM_MAC_EX_1G_BAB_TX: \
bitMask = IMASK_BTEN ; break; \
case e_FM_MAC_EX_1G_TX_CTL: \
bitMask = IMASK_TXCEN ; break; \
case e_FM_MAC_EX_1G_TX_ERR: \
bitMask = IMASK_TXEEN ; break; \
case e_FM_MAC_EX_1G_LATE_COL: \
bitMask = IMASK_LCEN ; break; \
case e_FM_MAC_EX_1G_COL_RET_LMT: \
bitMask = IMASK_CRLEN ; break; \
case e_FM_MAC_EX_1G_TX_FIFO_UNDRN: \
bitMask = IMASK_XFUNEN ; break; \
case e_FM_MAC_EX_1G_MAG_PCKT: \
bitMask = IMASK_MAGEN ; break; \
case e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET: \
bitMask = IMASK_MMRDEN; break; \
case e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET: \
bitMask = IMASK_MMWREN ; break; \
case e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET: \
bitMask = IMASK_GRSCEN; break; \
case e_FM_MAC_EX_1G_TX_DATA_ERR: \
bitMask = IMASK_TDPEEN; break; \
case e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL: \
bitMask = IMASK_MSROEN ; break; \
default: bitMask = 0;break;}
#define MAX_PACKET_ALIGNMENT 31
#define MAX_INTER_PACKET_GAP 0x7f
#define MAX_INTER_PALTERNATE_BEB 0x0f
#define MAX_RETRANSMISSION 0x0f
#define MAX_COLLISION_WINDOW 0x03ff
/********************* From mac ext ******************************************/
typedef uint32_t t_ErrorDisable;
#define ERROR_DISABLE_TRANSMIT 0x00400000
#define ERROR_DISABLE_LATE_COLLISION 0x00040000
#define ERROR_DISABLE_COLLISION_RETRY_LIMIT 0x00020000
#define ERROR_DISABLE_TxFIFO_UNDERRUN 0x00010000
#define ERROR_DISABLE_TxABORT 0x00008000
#define ERROR_DISABLE_INTERFACE 0x00004000
#define ERROR_DISABLE_TxDATA_PARITY 0x00000002
#define ERROR_DISABLE_RxDATA_PARITY 0x00000001
/*****************************************************************************/
#define DTSEC_NUM_OF_PADDRS 15 /* number of pattern match registers (entries) */
#define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */
#define HASH_TABLE_SIZE 256 /* Hash table size (= 32 bits * 8 regs) */
#define DTSEC_TO_MII_OFFSET 0x1120 /* number of pattern match registers (entries) */
#define DEFAULT_errorDisabled 0
#define DEFAULT_promiscuousEnable FALSE
#define DEFAULT_pauseExtended 0x0
#define DEFAULT_pauseTime 0xf000
#define DEFAULT_halfDuplex FALSE
#define DEFAULT_halfDulexFlowControlEn FALSE
#define DEFAULT_txTimeStampEn FALSE
#define DEFAULT_rxTimeStampEn FALSE
#define DEFAULT_packetAlignment 0
#define DEFAULT_controlFrameAccept FALSE
#define DEFAULT_groupHashExtend FALSE
#define DEFAULT_broadcReject FALSE
#define DEFAULT_rxShortFrame TRUE
#define DEFAULT_exactMatch FALSE
#define DEFAULT_debugMode FALSE
#define DEFAULT_loopback FALSE
#define DEFAULT_actOnRxPauseFrame TRUE
#define DEFAULT_actOnTxPauseFrame TRUE
#define DEFAULT_PreAmLength 0x7
#define DEFAULT_PreAmRxEn FALSE
#define DEFAULT_PreAmTxEn FALSE
#define DEFAULT_lengthCheckEnable FALSE
#define DEFAULT_padAndCrcEnable TRUE
#define DEFAULT_crcEnable FALSE
#define DEFAULT_nonBackToBackIpg1 0x40
#define DEFAULT_nonBackToBackIpg2 0x60
#define DEFAULT_minIfgEnforcement 0x50
#define DEFAULT_backToBackIpg 0x60
#define DEFAULT_altBackoffVal 0x0A
#define DEFAULT_altBackoffEnable FALSE
#define DEFAULT_backPressureNoBackoff FALSE
#define DEFAULT_noBackoff FALSE
#define DEFAULT_excessDefer TRUE
#define DEFAULT_maxRetransmission 0x0F
#define DEFAULT_collisionWindow 0x37
#define DEFAULT_maxFrameLength 0x600
#define DEFAULT_collisionWindow 0x37
#define DEFAULT_fifoTxThr 0x10
#define DEFAULT_fifoTxWatermarkH 0x7e
#define DEFAULT_fifoRxWatermarkL 0x08
#define DEFAULT_tbiPhyAddr 5
#define DEFAULT_exceptions ((uint32_t)(IMASK_BREN | \
IMASK_RXCEN | \
IMASK_BTEN | \
IMASK_TXCEN | \
IMASK_TXEEN | \
IMASK_ABRTEN | \
IMASK_LCEN | \
IMASK_CRLEN | \
IMASK_XFUNEN | \
IMASK_IFERREN | \
IMASK_MAGEN | \
IMASK_TDPEEN | \
IMASK_RDPEEN))
#define MAX_PHYS 32 /* maximum number of phys */
#define DTSEC_ID1_ID 0xffff0000
#define DTSEC_ID1_REV_MJ 0x0000FF00
#define DTSEC_ID1_REV_MN 0x000000ff
#define ID2_INT_REDUCED_OFF 0x00010000
#define ID2_INT_NORMAL_OFF 0x00020000
#define ECNTRL_CLRCNT 0x00004000
#define ECNTRL_AUTOZ 0x00002000
#define ECNTRL_STEN 0x00001000
#define ECNTRL_CFG_RO 0x80000000
#define ECNTRL_GMIIM 0x00000040
#define ECNTRL_TBIM 0x00000020
#define ECNTRL_SGMIIM 0x00000002
#define ECNTRL_RPM 0x00000010
#define ECNTRL_R100M 0x00000008
#define ECNTRL_RMM 0x00000004
#define ECNTRL_QSGMIIM 0x00000001
#define TCTRL_THDF 0x00000800
#define TCTRL_TTSE 0x00000040
#define TCTRL_GTS 0x00000020
#define TCTRL_TFC_PAUSE 0x00000010
/* PTV offsets */
#define PTV_PTE_OFST 16
#define RCTRL_CFA 0x00008000
#define RCTRL_GHTX 0x00000400
#define RCTRL_RTSE 0x00000040
#define RCTRL_GRS 0x00000020
#define RCTRL_BC_REJ 0x00000010
#define RCTRL_MPROM 0x00000008
#define RCTRL_RSF 0x00000004
#define RCTRL_EMEN 0x00000002
#define RCTRL_UPROM 0x00000001
#define RCTRL_PROM (RCTRL_UPROM | RCTRL_MPROM)
#define TMR_CTL_ESFDP 0x00000800
#define TMR_CTL_ESFDE 0x00000400
#define TSEC_ID1_DEBUG 0x00e00c00
#define DEBUG_ENABLE 0x80000000
#define DPERROR_Tx_ERROR_ON_SEC 0x00400000
#define DPERROR_Tx_ERROR_ON_WRITE 0x10000000
#define DPERROR_Rx_ERROR_ON_SEC 0x00000040
#define DPERROR_Rx_ERROR_ON_WRITE 0x00001000
#define DPERROR_STT 0x80000000
#define DPERROR_STR 0x00008000
#define MACCFG1_SOFT_RESET 0x80000000
#define MACCFG1_LOOPBACK 0x00000100
#define MACCFG1_RX_FLOW 0x00000020
#define MACCFG1_TX_FLOW 0x00000010
#define MACCFG1_TX_EN 0x00000001
#define MACCFG1_RX_EN 0x00000004
#define MACCFG1_RESET_RxMC 0x00080000
#define MACCFG1_RESET_TxMC 0x00040000
#define MACCFG1_RESET_RxFUN 0x00020000
#define MACCFG1_RESET_TxFUN 0x00010000
#define MACCFG2_NIBBLE_MODE 0x00000100
#define MACCFG2_BYTE_MODE 0x00000200
#define MACCFG2_PRE_AM_Rx_EN 0x00000080
#define MACCFG2_PRE_AM_Tx_EN 0x00000040
#define MACCFG2_LENGTH_CHECK 0x00000010
#define MACCFG2_MAGIC_PACKET_EN 0x00000008
#define MACCFG2_PAD_CRC_EN 0x00000004
#define MACCFG2_CRC_EN 0x00000002
#define MACCFG2_FULL_DUPLEX 0x00000001
#define PREAMBLE_LENGTH_SHIFT 12
#define IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT 24
#define IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT 16
#define IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT 8
#define IPGIFG_NON_BACK_TO_BACK_IPG_1 0x7F000000
#define IPGIFG_NON_BACK_TO_BACK_IPG_2 0x007F0000
#define IPGIFG_MIN_IFG_ENFORCEMENT 0x0000FF00
#define IPGIFG_BACK_TO_BACK_IPG 0x0000007F
#define HAFDUP_ALT_BEB 0x00080000
#define HAFDUP_BP_NO_BACKOFF 0x00040000
#define HAFDUP_NO_BACKOFF 0x00020000
#define HAFDUP_EXCESS_DEFER 0x00010000
#define HAFDUP_COLLISION_WINDOW 0x000003ff
#define HAFDUP_ALTERNATE_BEB_TRUNCATION_SHIFT 20
#define HAFDUP_RETRANSMISSION_MAX_SHIFT 12
#define HAFDUP_RETRANSMISSION_MAX 0x0000f000
#define NUM_OF_HASH_REGS 8 /* Number of hash table registers */
#define DEBUG_GET_FIFO_READ_INDEX 0x007f0000
#define DEBUG_GET_FIFO_WRITE_INDEX 0x0000007f
/* Pause Time Value Register */
#define PTV_PTE_SHIFT 16
#define MASK22BIT 0x003FFFFF
#define MASK16BIT 0x0000FFFF
#define MASK12BIT 0x00000FFF
#define MASK8BIT 0x000000FF
#define VAL32BIT 0x100000000LL
#define VAL22BIT 0x00400000
#define VAL16BIT 0x00010000
#define VAL12BIT 0x00001000
/* PHY Control Register */
#define PHY_CR_LOOPBACK 0x4000
#define PHY_CR_SPEED0 0x2000
#define PHY_CR_ANE 0x1000
#define PHY_CR_FULLDUPLEX 0x0100
#define PHY_CR_SPEED1 0x0040
#define PHY_TBICON_SRESET 0x8000
#define PHY_TBICON_SPEED2 0x0020
/* CAR1/2 bits */
#define CAR1_TR64 0x80000000
#define CAR1_TR127 0x40000000
#define CAR1_TR255 0x20000000
#define CAR1_TR511 0x10000000
#define CAR1_TRK1 0x08000000
#define CAR1_TRMAX 0x04000000
#define CAR1_TRMGV 0x02000000
#define CAR1_RBYT 0x00010000
#define CAR1_RPKT 0x00008000
#define CAR1_RMCA 0x00002000
#define CAR1_RBCA 0x00001000
#define CAR1_RXPF 0x00000400
#define CAR1_RALN 0x00000100
#define CAR1_RFLR 0x00000080
#define CAR1_RCDE 0x00000040
#define CAR1_RCSE 0x00000020
#define CAR1_RUND 0x00000010
#define CAR1_ROVR 0x00000008
#define CAR1_RFRG 0x00000004
#define CAR1_RJBR 0x00000002
#define CAR1_RDRP 0x00000001
#define CAR2_TFCS 0x00040000
#define CAR2_TBYT 0x00002000
#define CAR2_TPKT 0x00001000
#define CAR2_TMCA 0x00000800
#define CAR2_TBCA 0x00000400
#define CAR2_TXPF 0x00000200
#define CAR2_TDRP 0x00000001
#define CAM1_ERRORS_ONLY (CAR1_RXPF | \
CAR1_RALN | \
CAR1_RFLR | \
CAR1_RCDE | \
CAR1_RCSE | \
CAR1_RUND | \
CAR1_ROVR | \
CAR1_RFRG | \
CAR1_RJBR | \
CAR1_RDRP)
#define CAM2_ERRORS_ONLY (CAR2_TFCS | CAR2_TXPF | CAR2_TDRP)
typedef struct t_InternalStatistics
{
uint64_t tr64;
uint64_t tr127;
uint64_t tr255;
uint64_t tr511;
uint64_t tr1k;
uint64_t trmax;
uint64_t trmgv;
uint64_t rfrg;
uint64_t rjbr;
uint64_t rdrp;
uint64_t raln;
uint64_t rund;
uint64_t rovr;
uint64_t rxpf;
uint64_t txpf;
uint64_t rbyt;
uint64_t rpkt;
uint64_t rmca;
uint64_t rbca;
uint64_t rflr;
uint64_t rcde;
uint64_t rcse;
uint64_t tbyt;
uint64_t tpkt;
uint64_t tmca;
uint64_t tbca;
uint64_t tdrp;
uint64_t tfcs;
} t_InternalStatistics;
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct
{
uint32_t exact_match1; /* octets 1-4 */
uint32_t exact_match2; /* octets 5-6 */
} _PackedType macRegs;
typedef _Packed struct
{
volatile uint32_t tsec_id1; /* 0x000 ETSEC_ID register */
volatile uint32_t tsec_id2; /* 0x004 ETSEC_ID2 register */
volatile uint32_t ievent; /* 0x008 Interrupt event register */
volatile uint32_t imask; /* 0x00C Interrupt mask register */
volatile uint32_t edis; /* 0x010 Error disabled register */
volatile uint32_t ecntrl; /* 0x014 E control register */
volatile uint32_t ptv; /* 0x018 Pause time value register */
volatile uint32_t tbipa; /* 0x01C TBI PHY address register */
volatile uint32_t tmr_ctrl; /* 0x020 Time-stamp Control register */
volatile uint32_t tmr_pevent; /* 0x024 Time-stamp event register */
volatile uint32_t tmr_pemask; /* 0x028 Timer event mask register */
volatile uint32_t DTSEC_RESERVED2; /* 0x02C */
volatile uint32_t iobistctl; /* 0x030 IO BIST Control register */
volatile uint32_t DTSEC_RESERVED3[3]; /* 0x034 */
volatile uint32_t tctrl; /* 0x040 Transmit control register */
volatile uint32_t DTSEC_RESERVED4[3]; /* 0x044-0x04C */
volatile uint32_t rctrl; /* 0x050 Receive control register */
volatile uint32_t DTSEC_RESERVED5[11]; /* 0x054- 0x07C */
volatile uint32_t igaddr[8]; /* 0x080-0x09C Individual/group address registers 0-7 */
volatile uint32_t gaddr[8]; /* 0x0A0-0x0BC Group address registers 0-7 */
volatile uint32_t ETSEC_RESERVED6[16]; /* 0x0C0-0x0FC */
volatile uint32_t maccfg1; /* 0x100 MAC configuration #1 */
volatile uint32_t maccfg2; /* 0x104 MAC configuration #2 */
volatile uint32_t ipgifg; /* 0x108 IPG/IFG */
volatile uint32_t hafdup; /* 0x10C Half-duplex */
volatile uint32_t maxfrm; /* 0x110 Maximum frame */
volatile uint32_t DTSEC_RESERVED7[3]; /* 0x114-0x11C register */
t_MiiAccessMemMap miiMemMap;
volatile uint32_t ifctrl; /* 0x138 MII Mgmt:interface control */
volatile uint32_t ifstat; /* 0x13C Interface status */
volatile uint32_t macstnaddr1; /* 0x140 Station Address,part 1 */
volatile uint32_t macstnaddr2; /* 0x144 Station Address,part 2 */
volatile macRegs macaddr[DTSEC_NUM_OF_PADDRS]; /* 0x148-0x1BC mac exact match addresses 1-15, parts 1-2 */
volatile uint32_t DTSEC_RESERVED8[16]; /* 0x1C0-0x1FC register */
/* RMON MIB REGISTERS */
/* TRANSMIT and RECEIVE COUNTERS */
volatile uint32_t tr64; /* 0x200 transmit and receive 64 byte frame counter */
volatile uint32_t tr127; /* 0x204 transmit and receive 65 to 127 byte frame counter */
volatile uint32_t tr255; /* 0x208 transmit and receive 128 to 255 byte frame counter */
volatile uint32_t tr511; /* 0x20C transmit and receive 256 to 511 byte frame counter */
volatile uint32_t tr1k; /* 0x210 transmit and receive 512 to 1023 byte frame counter */
volatile uint32_t trmax; /* 0x214 transmit and receive 1024 to 1518 byte frame counter */
volatile uint32_t trmgv; /* 0x218 transmit and receive 1519 to 1522 byte good VLAN frame count */
/* RECEIVE COUNTERS */
volatile uint32_t rbyt; /* 0x21C receive byte counter */
volatile uint32_t rpkt; /* 0x220 receive packet counter */
volatile uint32_t rfcs; /* 0x224 receive FCS error counter */
volatile uint32_t rmca; /* 0x228 RMCA receive multicast packet counter */
volatile uint32_t rbca; /* 0x22C receive broadcast packet counter */
volatile uint32_t rxcf; /* 0x230 receive control frame packet counter */
volatile uint32_t rxpf; /* 0x234 receive PAUSE frame packet counter */
volatile uint32_t rxuo; /* 0x238 receive unknown OP code counter */
volatile uint32_t raln; /* 0x23C receive alignment error counter */
volatile uint32_t rflr; /* 0x240 receive frame length error counter */
volatile uint32_t rcde; /* 0x244 receive code error counter */
volatile uint32_t rcse; /* 0x248 receive carrier sense error counter */
volatile uint32_t rund; /* 0x24C receive undersize packet counter */
volatile uint32_t rovr; /* 0x250 receive oversize packet counter */
volatile uint32_t rfrg; /* 0x254 receive fragments counter */
volatile uint32_t rjbr; /* 0x258 receive jabber counter */
volatile uint32_t rdrp; /* 0x25C receive drop */
/* TRANSMIT COUNTERS */
volatile uint32_t tbyt; /* 0x260 transmit byte counter */
volatile uint32_t tpkt; /* 0x264 transmit packet counter */
volatile uint32_t tmca; /* 0x268 transmit multicast packet counter */
volatile uint32_t tbca; /* 0x26C transmit broadcast packet counter */
volatile uint32_t txpf; /* 0x270 transmit PAUSE control frame counter */
volatile uint32_t tdfr; /* 0x274 transmit deferral packet counter */
volatile uint32_t tedf; /* 0x278 transmit excessive deferral packet counter */
volatile uint32_t tscl; /* 0x27C transmit single collision packet counter */
volatile uint32_t tmcl; /* 0x280 transmit multiple collision packet counter */
volatile uint32_t tlcl; /* 0x284 transmit late collision packet counter */
volatile uint32_t txcl; /* 0x288 transmit excessive collision packet counter */
volatile uint32_t tncl; /* 0x28C transmit total collision counter */
volatile uint32_t DTSEC_RESERVED9; /* 0x290 */
volatile uint32_t tdrp; /* 0x294 transmit drop frame counter */
volatile uint32_t tjbr; /* 0x298 transmit jabber frame counter */
volatile uint32_t tfcs; /* 0x29C transmit FCS error counter */
volatile uint32_t txcf; /* 0x2A0 transmit control frame counter */
volatile uint32_t tovr; /* 0x2A4 transmit oversize frame counter */
volatile uint32_t tund; /* 0x2A8 transmit undersize frame counter */
volatile uint32_t tfrg; /* 0x2AC transmit fragments frame counter */
/* GENERAL REGISTERS */
volatile uint32_t car1; /* 0x2B0 carry register one register* */
volatile uint32_t car2; /* 0x2B4 carry register two register* */
volatile uint32_t cam1; /* 0x2B8 carry register one mask register */
volatile uint32_t cam2; /* 0x2BC carry register two mask register */
volatile uint32_t DTSEC_RESERVED10[16]; /* 0x2C0-0x2FC */
/* Debug and Factory Test Registers */
volatile uint32_t debug; /* 0x300 DEBUG - Debug Register */
volatile uint32_t dperror; /* 0x304 DPERROR - Parity Error Register */
volatile uint32_t hwassert; /* 0x308 HWASSERT */
volatile uint32_t RESERVED11; /* 0x30C Reserved */
volatile uint32_t rx_fifo_ptr; /* 0x310 RXFIFOPTR - Rx FIFO R/W Pointer Register */
volatile uint32_t rx_fifo_dath; /* 0x314 RXFIFODATH - Rx FIFO Data Register */
volatile uint32_t rx_fifo_datl; /* 0x318 RXFIFODATL - Rx FIFO Data Register */
volatile uint32_t rx_fifo_stat; /* 0x31C RXFIFOSTAT - Rx FIFO Status Register */
volatile uint32_t tx_fifo_ptr; /* 0x320 TXFIFOPTR - Tx FIFO R/W Pointer Register */
volatile uint32_t tx_fifo_dath; /* 0x324 TXFIFODATH - Rx FIFO Data Register */
volatile uint32_t tx_fifo_datl; /* 0x328 TXFIFODATL - Rx FIFO Data Register */
volatile uint32_t tx_fifo_stat; /* 0x32C TXFIFOSTAT - Tx FIFO Status Register */
volatile uint32_t pkt_rcv_cnt; /* 0x330 PKTRCVCNT - Number of packets accepted and written to Rx FIFO */
volatile uint32_t RESERVED12[3]; /* 0x334-0x33C Reserved */
volatile uint32_t tx_threshold; /* 0x340 Transmit threshold; Number of entries (4 bytes units) before starting to transmit to the MAC */
volatile uint32_t tx_watermark_high;/* 0x344 Transmit watermark high; Number of entries (4 byte units) before de-asserting Ready to packet Interface */
volatile uint32_t rx_watermark_low; /* 0x348 Receive watermark low; Number of entries (4 byte units) before unloading to packet Interface */
} _PackedType t_DtsecMemMap;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
typedef struct {
uint32_t errorDisabled;
bool halfDuplex;
uint16_t pauseTime;
uint16_t pauseExtended;
uint8_t tbiPhyAddr; /**< TBI Physical address (1-31) [DEFAULT_tbiPhyAddr] */
bool autoZeroCounters;
bool promiscuousEnable;
bool halfDulexFlowControlEn;
bool txTimeStampEn;
bool rxTimeStampEn;
uint8_t packetAlignmentPadding;
bool controlFrameAccept;
bool groupHashExtend;
bool broadcReject;
bool rxShortFrame;
bool exactMatch;
bool debugMode;
bool loopback;
bool actOnRxPauseFrame;
bool actOnTxPauseFrame;
uint8_t nonBackToBackIpg1;
uint8_t nonBackToBackIpg2;
uint8_t minIfgEnforcement;
uint8_t backToBackIpg;
uint8_t preambleLength;
bool preambleRxEn;
bool preambleTxEn;
bool lengthCheckEnable;
bool magicPacketEnable;
bool padAndCrcEnable;
bool crcEnable;
bool alternateBackoffEnable;
uint8_t alternateBackoffVal;
bool backPressureNoBackoff;
bool noBackoff;
bool excessDefer;
uint8_t maxRetransmission;
uint16_t collisionWindow;
uint16_t maxFrameLength;
uint8_t fifoTxThr;
uint8_t fifoTxWatermarkH;
uint8_t fifoRxWatermarkL;
} t_DtsecDriverParam;
typedef struct {
t_FmMacControllerDriver fmMacControllerDriver;
t_Handle h_App; /**< Handle to the upper layer application */
t_DtsecMemMap *p_MemMap; /**< pointer to dTSEC memory mapped registers. */
t_MiiAccessMemMap *p_MiiMemMap; /**< pointer to dTSEC MII memory mapped registers. */
uint64_t addr; /**< MAC address of device; */
e_EnetMode enetMode; /**< Ethernet physical interface */
t_FmMacExceptionCallback *f_Exception;
int mdioIrq;
t_FmMacExceptionCallback *f_Event;
bool indAddrRegUsed[DTSEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
uint64_t paddr[DTSEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
bool debugMode;
bool halfDuplex;
t_InternalStatistics internalStatistics;
t_EthHash *p_MulticastAddrHash; /* pointer to driver's global address hash table */
t_EthHash *p_UnicastAddrHash; /* pointer to driver's individual address hash table */
uint8_t macId;
uint32_t exceptions;
bool ptpTsuEnabled;
bool enTsuErrExeption;
e_FmMacStatisticsLevel statisticsLevel;
t_DtsecDriverParam *p_DtsecDriverParam;
} t_Dtsec;
t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#endif /* __DTSEC_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File dtsec_mii_acc.c
@Description FM dtsec MII register access MAC ...
*//***************************************************************************/
#include "error_ext.h"
#include "std_ext.h"
#include "fm_mac.h"
#include "dtsec.h"
/*****************************************************************************/
t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec,
uint8_t phyAddr,
uint8_t reg,
uint16_t data)
{
t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
t_MiiAccessMemMap *p_MiiAccess;
uint32_t tmpReg;
SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Dtsec->p_MiiMemMap;
/* Stop the MII management read cycle */
WRITE_UINT32(p_MiiAccess->miimcom, 0);
/* Dummy read to make sure MIIMCOM is written */
tmpReg = GET_UINT32(p_MiiAccess->miimcom);
/* Setting up MII Management Address Register */
tmpReg = (uint32_t)((phyAddr << MIIMADD_PHY_ADDR_SHIFT) | reg);
WRITE_UINT32(p_MiiAccess->miimadd, tmpReg);
/* Setting up MII Management Control Register with data */
WRITE_UINT32(p_MiiAccess->miimcon, (uint32_t)data);
/* Dummy read to make sure MIIMCON is written */
tmpReg = GET_UINT32(p_MiiAccess->miimcon);
/* Wait till MII management write is complete */
while ((GET_UINT32(p_MiiAccess->miimind)) & MIIMIND_BUSY) ;
return E_OK;
}
/*****************************************************************************/
t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec,
uint8_t phyAddr,
uint8_t reg,
uint16_t *p_Data)
{
t_Dtsec *p_Dtsec = (t_Dtsec *)h_Dtsec;
t_MiiAccessMemMap *p_MiiAccess;
uint32_t tmpReg;
SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Dtsec->p_MiiMemMap;
/* Setting up the MII Management Address Register */
tmpReg = (uint32_t)((phyAddr << MIIMADD_PHY_ADDR_SHIFT) | reg);
WRITE_UINT32(p_MiiAccess->miimadd, tmpReg);
/* Perform an MII management read cycle */
WRITE_UINT32(p_MiiAccess->miimcom, MIIMCOM_READ_CYCLE);
/* Dummy read to make sure MIIMCOM is written */
tmpReg = GET_UINT32(p_MiiAccess->miimcom);
/* Wait till MII management read is complete */
while ((GET_UINT32(p_MiiAccess->miimind)) & MIIMIND_BUSY) ;
/* Read MII management status */
*p_Data = (uint16_t)GET_UINT32(p_MiiAccess->miimstat);
WRITE_UINT32(p_MiiAccess->miimcom, 0);
/* Dummy read to make sure MIIMCOM is written */
tmpReg = GET_UINT32(p_MiiAccess->miimcom);
if (*p_Data == 0xffff)
RETURN_ERROR(MINOR, E_NO_DEVICE,
("Read wrong data (0xffff): phyAddr 0x%x, reg 0x%x",
phyAddr, reg));
return E_OK;
}

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DTSEC_MII_ACC_H
#define __DTSEC_MII_ACC_H
#include "std_ext.h"
/* MII Management Configuration Register */
#define MIIMCFG_RESET_MGMT 0x80000000
#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
/* MII Management Command Register */
#define MIIMCOM_READ_CYCLE 0x00000001
#define MIIMCOM_SCAN_CYCLE 0x00000002
/* MII Management Address Register */
#define MIIMADD_PHY_ADDR_SHIFT 8
/* MII Management Indicator Register */
#define MIIMIND_BUSY 0x00000001
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/*----------------------------------------------------*/
/* MII Configuration Control Memory Map Registers */
/*----------------------------------------------------*/
typedef _Packed struct t_MiiAccessMemMap
{
volatile uint32_t miimcfg; /* MII Mgmt:configuration */
volatile uint32_t miimcom; /* MII Mgmt:command */
volatile uint32_t miimadd; /* MII Mgmt:address */
volatile uint32_t miimcon; /* MII Mgmt:control 3 */
volatile uint32_t miimstat; /* MII Mgmt:status */
volatile uint32_t miimind; /* MII Mgmt:indicators */
} _PackedType t_MiiAccessMemMap ;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
#endif /* __DTSEC_MII_ACC_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_mac.c
@Description FM MAC ...
*//***************************************************************************/
#include "std_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "error_ext.h"
#include "fm_ext.h"
#include "fm_common.h"
#include "fm_mac.h"
/* ........................................................................... */
t_Handle FM_MAC_Config (t_FmMacParams *p_FmMacParam)
{
t_FmMacControllerDriver *p_FmMacControllerDriver;
SANITY_CHECK_RETURN_VALUE(p_FmMacParam, E_INVALID_HANDLE, NULL);
if(ENET_SPEED_FROM_MODE(p_FmMacParam->enetMode) < e_ENET_SPEED_10000)
p_FmMacControllerDriver = (t_FmMacControllerDriver *)DTSEC_Config(p_FmMacParam);
else
p_FmMacControllerDriver = (t_FmMacControllerDriver *)TGEC_Config(p_FmMacParam);
if (!p_FmMacControllerDriver)
return NULL;
p_FmMacControllerDriver->h_Fm = p_FmMacParam->h_Fm;
p_FmMacControllerDriver->enetMode = p_FmMacParam->enetMode;
p_FmMacControllerDriver->macId = p_FmMacParam->macId;
p_FmMacControllerDriver->resetOnInit = DEFAULT_resetOnInit;
return (t_Handle)p_FmMacControllerDriver;
}
/* ........................................................................... */
t_Error FM_MAC_Init (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->resetOnInit &&
(FmResetMac(p_FmMacControllerDriver->h_Fm,
((ENET_INTERFACE_FROM_MODE(p_FmMacControllerDriver->enetMode) == e_ENET_IF_XGMII) ? e_FM_MAC_10G : e_FM_MAC_1G),
p_FmMacControllerDriver->macId) != E_OK))
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't reset MAC!"));
if ((p_FmMacControllerDriver->clkFreq = FmGetClockFreq(p_FmMacControllerDriver->h_Fm)) == 0)
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't get clock for MAC!"));
if (p_FmMacControllerDriver->f_FM_MAC_Init)
return p_FmMacControllerDriver->f_FM_MAC_Init(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_Free (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Free)
return p_FmMacControllerDriver->f_FM_MAC_Free(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_ConfigResetOnInit (t_Handle h_FmMac, bool enable)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
p_FmMacControllerDriver->resetOnInit = enable;
return E_OK;
}
/* ........................................................................... */
t_Error FM_MAC_ConfigLoopback (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback)
return p_FmMacControllerDriver->f_FM_MAC_ConfigLoopback(h_FmMac, newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_ConfigMaxFrameLength (t_Handle h_FmMac, uint16_t newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength)
return p_FmMacControllerDriver->f_FM_MAC_ConfigMaxFrameLength(h_FmMac, newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_ConfigWan (t_Handle h_FmMac, bool flag)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigWan)
return p_FmMacControllerDriver->f_FM_MAC_ConfigWan(h_FmMac, flag);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_ConfigPadAndCrc (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc)
return p_FmMacControllerDriver->f_FM_MAC_ConfigPadAndCrc(h_FmMac, newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_ConfigHalfDuplex (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex)
return p_FmMacControllerDriver->f_FM_MAC_ConfigHalfDuplex(h_FmMac,newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_ConfigLengthCheck (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck)
return p_FmMacControllerDriver->f_FM_MAC_ConfigLengthCheck(h_FmMac,newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_ConfigException (t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigException)
return p_FmMacControllerDriver->f_FM_MAC_ConfigException(h_FmMac, ex, enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
/* ........................................................................... */
t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround)
return p_FmMacControllerDriver->f_FM_MAC_ConfigSkipFman11Workaround(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
/*****************************************************************************/
/* Run Time Control */
/*****************************************************************************/
/* ........................................................................... */
t_Error FM_MAC_Enable (t_Handle h_FmMac, e_CommMode mode)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Enable)
return p_FmMacControllerDriver->f_FM_MAC_Enable(h_FmMac, mode);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_Disable (t_Handle h_FmMac, e_CommMode mode)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Disable)
return p_FmMacControllerDriver->f_FM_MAC_Disable(h_FmMac, mode);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_Enable1588TimeStamp (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp)
return p_FmMacControllerDriver->f_FM_MAC_Enable1588TimeStamp(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_Disable1588TimeStamp (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp)
return p_FmMacControllerDriver->f_FM_MAC_Disable1588TimeStamp(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_SetTxAutoPauseFrames (t_Handle h_FmMac, uint16_t pauseTime)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames)
return p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames(h_FmMac, pauseTime);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_SetRxIgnorePauseFrames (t_Handle h_FmMac, bool en)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames)
return p_FmMacControllerDriver->f_FM_MAC_SetRxIgnorePauseFrames(h_FmMac, en);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_ResetCounters (t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ResetCounters)
return p_FmMacControllerDriver->f_FM_MAC_ResetCounters(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetException)
return p_FmMacControllerDriver->f_FM_MAC_SetException(h_FmMac, ex, enable);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_SetStatistics (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetStatistics)
return p_FmMacControllerDriver->f_FM_MAC_SetStatistics(h_FmMac, statisticsLevel);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_GetStatistics (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_GetStatistics)
return p_FmMacControllerDriver->f_FM_MAC_GetStatistics(h_FmMac, p_Statistics);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_ModifyMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_ModifyMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_AddHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_AddHashMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_RemoveHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_RemoveHashMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_AddExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_AddExactMatchMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_RemovelExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr)
return p_FmMacControllerDriver->f_FM_MAC_RemovelExactMatchMacAddr(h_FmMac, p_EnetAddr);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_GetVesrion (t_Handle h_FmMac, uint32_t *macVresion)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_GetVersion)
return p_FmMacControllerDriver->f_FM_MAC_GetVersion(h_FmMac, macVresion);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_GetId (t_Handle h_FmMac, uint32_t *macId)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_GetId)
return p_FmMacControllerDriver->f_FM_MAC_GetId(h_FmMac, macId);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_SetPromiscuous (t_Handle h_FmMac, bool newVal)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous)
return p_FmMacControllerDriver->f_FM_MAC_SetPromiscuous(h_FmMac, newVal);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_AdjustLink)
return p_FmMacControllerDriver->f_FM_MAC_AdjustLink(h_FmMac, speed, fullDuplex);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_MII_WritePhyReg (t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg)
return p_FmMacControllerDriver->f_FM_MAC_MII_WritePhyReg(h_FmMac, phyAddr, reg, data);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
t_Error FM_MAC_MII_ReadPhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg)
return p_FmMacControllerDriver->f_FM_MAC_MII_ReadPhyReg(h_FmMac, phyAddr, reg, p_Data);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
/* ........................................................................... */
uint16_t FM_MAC_GetMaxFrameLength(t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_VALUE(p_FmMacControllerDriver, E_INVALID_HANDLE, 0);
if (p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength)
return p_FmMacControllerDriver->f_FM_MAC_GetMaxFrameLength(h_FmMac);
REPORT_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
return 0;
}
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
/*****************************************************************************/
t_Error FM_MAC_DumpRegs(t_Handle h_FmMac)
{
t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
if (p_FmMacControllerDriver->f_FM_MAC_DumpRegs)
return p_FmMacControllerDriver->f_FM_MAC_DumpRegs(h_FmMac);
RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
}
#endif /* (defined(DEBUG_ERRORS) && ... */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_mac.h
@Description FM MAC ...
*//***************************************************************************/
#ifndef __FM_MAC_H
#define __FM_MAC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_mac_ext.h"
#define __ERR_MODULE__ MODULE_FM_MAC
#define DEFAULT_resetOnInit FALSE
typedef struct {
uint64_t addr; /* Ethernet Address */
t_List node;
} t_EthHashEntry;
#define ETH_HASH_ENTRY_OBJ(ptr) LIST_OBJECT(ptr, t_EthHashEntry, node)
typedef struct {
uint16_t size;
t_List *p_Lsts;
} t_EthHash;
typedef struct {
t_Error (*f_FM_MAC_Init) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Free) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_SetStatistics) (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel);
t_Error (*f_FM_MAC_ConfigLoopback) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigMaxFrameLength) (t_Handle h_FmMac, uint16_t newVal);
t_Error (*f_FM_MAC_ConfigWan) (t_Handle h_FmMac, bool flag);
t_Error (*f_FM_MAC_ConfigPadAndCrc) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigHalfDuplex) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigLengthCheck) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_ConfigException) (t_Handle h_FmMac, e_FmMacExceptions, bool enable);
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
t_Error (*f_FM_MAC_ConfigSkipFman11Workaround) (t_Handle h_FmMac);
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
t_Error (*f_FM_MAC_SetException) (t_Handle h_FmMac, e_FmMacExceptions ex, bool enable);
t_Error (*f_FM_MAC_Enable) (t_Handle h_FmMac, e_CommMode mode);
t_Error (*f_FM_MAC_Disable) (t_Handle h_FmMac, e_CommMode mode);
t_Error (*f_FM_MAC_Enable1588TimeStamp) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Disable1588TimeStamp) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_Reset) (t_Handle h_FmMac, bool wait);
t_Error (*f_FM_MAC_SetTxAutoPauseFrames) (t_Handle h_FmMac, uint16_t pauseTime);
t_Error (*f_FM_MAC_SetRxIgnorePauseFrames) (t_Handle h_FmMac, bool en);
t_Error (*f_FM_MAC_ResetCounters) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_GetStatistics) (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics);
t_Error (*f_FM_MAC_ModifyMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_AddHashMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_RemoveHashMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_AddExactMatchMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_RemovelExactMatchMacAddr) (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
t_Error (*f_FM_MAC_SetPromiscuous) (t_Handle h_FmMac, bool newVal);
t_Error (*f_FM_MAC_AdjustLink) (t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex);
t_Error (*f_FM_MAC_GetId) (t_Handle h_FmMac, uint32_t *macId);
t_Error (*f_FM_MAC_GetVersion) (t_Handle h_FmMac, uint32_t *macVersion);
uint16_t (*f_FM_MAC_GetMaxFrameLength) (t_Handle h_FmMac);
t_Error (*f_FM_MAC_MII_WritePhyReg)(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error (*f_FM_MAC_MII_ReadPhyReg)(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
t_Error (*f_FM_MAC_DumpRegs) (t_Handle h_FmMac);
#endif /* (defined(DEBUG_ERRORS) && ... */
t_Handle h_Fm;
e_EnetMode enetMode;
uint8_t macId;
bool resetOnInit;
uint16_t clkFreq;
} t_FmMacControllerDriver;
t_Handle DTSEC_Config(t_FmMacParams *p_FmMacParam);
t_Handle TGEC_Config(t_FmMacParams *p_FmMacParams);
uint16_t FM_MAC_GetMaxFrameLength(t_Handle FmMac);
/* ........................................................................... */
static __inline__ t_EthHashEntry *DequeueAddrFromHashEntry(t_List *p_AddrLst)
{
t_EthHashEntry *p_HashEntry = NULL;
if (!LIST_IsEmpty(p_AddrLst))
{
p_HashEntry = ETH_HASH_ENTRY_OBJ(p_AddrLst->p_Next);
LIST_DelAndInit(&p_HashEntry->node);
}
return p_HashEntry;
}
/* ........................................................................... */
static __inline__ void FreeHashTable(t_EthHash *p_Hash)
{
t_EthHashEntry *p_HashEntry;
int i = 0;
if (!p_Hash || !p_Hash->p_Lsts)
return;
for(i=0; i<p_Hash->size; i++)
{
p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
while (p_HashEntry)
{
XX_Free(p_HashEntry);
p_HashEntry = DequeueAddrFromHashEntry(&p_Hash->p_Lsts[i]);
}
}
XX_Free(p_Hash->p_Lsts);
XX_Free(p_Hash);
}
/* ........................................................................... */
static __inline__ t_EthHash * AllocHashTable(uint16_t size)
{
uint32_t i;
t_EthHash *p_Hash;
/* Allocate address hash table */
p_Hash = (t_EthHash *)XX_Malloc(size*sizeof(t_EthHash *));
if (!p_Hash)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Address hash table"));
return NULL;
}
p_Hash->size = size;
p_Hash->p_Lsts = (t_List *)XX_Malloc(p_Hash->size*sizeof(t_List));
if (!p_Hash->p_Lsts)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("Address hash table"));
XX_Free(p_Hash);
return NULL;
}
for(i=0 ; i<p_Hash->size; i++)
INIT_LIST(&p_Hash->p_Lsts[i]);
return p_Hash;
}
#endif /* __FM_MAC_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File tgec.h
@Description FM 10G MAC ...
*//***************************************************************************/
#ifndef __TGEC_H
#define __TGEC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "tgec_mii_acc.h"
#include "fm_mac.h"
/* Interrupt Mask Register (IMASK) */
#define IMASK_MDIO_SCAN_EVENTMDIO 0x00010000 /* MDIO_SCAN_EVENTMDIO scan event interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_MDIO_CMD_CMPL 0x00008000 /* 16 MDIO_CMD_CMPL MDIO command completion interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_REM_FAULT 0x00004000 /* 17 REM_FAULT Remote fault interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_LOC_FAULT 0x00002000 /* 18 LOC_FAULT Local fault interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_1TX_ECC_ER 0x00001000 /* 19 TX_ECC_ER Transmit frame ECC error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_TX_FIFO_UNFL 0x00000800 /* 20 TX_FIFO_UNFL Transmit FIFO underflow interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_TX_FIFO_OVFL 0x00000400 /* 21 TX_FIFO_OVFL Transmit FIFO overflow interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_TX_ER 0x00000200 /* 22 TX_ER Transmit frame error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_FIFO_OVFL 0x00000100 /* 23 RX_FIFO_OVFL Receive FIFO overflow interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_ECC_ER 0x00000080 /* 24 RX_ECC_ER Receive frame ECC error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_JAB_FRM 0x00000040 /* 25 RX_JAB_FRM Receive jabber frame interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_OVRSZ_FRM 0x00000020 /* 26 RX_OVRSZ_FRM Receive oversized frame interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_RUNT_FRM 0x00000010 /* 27 RX_RUNT_FRM Receive runt frame interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_FRAG_FRM 0x00000008 /* 28 RX_FRAG_FRM Receive fragment frame interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_LEN_ER 0x00000004 /* 29 RX_LEN_ER Receive payload length error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_CRC_ER 0x00000002 /* 30 RX_CRC_ER Receive CRC error interrupt mask.
* 0 masked
* 1 enabled
*/
#define IMASK_RX_ALIGN_ER 0x00000001 /* 31 RX_ALIGN_ER Receive alignment error interrupt mask.
* 0 masked
* 1 enabled
*/
#define EVENTS_MASK ((uint32_t)(IMASK_MDIO_SCAN_EVENTMDIO | \
IMASK_MDIO_CMD_CMPL | \
IMASK_REM_FAULT | \
IMASK_LOC_FAULT | \
IMASK_1TX_ECC_ER | \
IMASK_TX_FIFO_UNFL | \
IMASK_TX_FIFO_OVFL | \
IMASK_TX_ER | \
IMASK_RX_FIFO_OVFL | \
IMASK_RX_ECC_ER | \
IMASK_RX_JAB_FRM | \
IMASK_RX_OVRSZ_FRM | \
IMASK_RX_RUNT_FRM | \
IMASK_RX_FRAG_FRM | \
IMASK_RX_LEN_ER | \
IMASK_RX_CRC_ER | \
IMASK_RX_ALIGN_ER))
#define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \
case e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO: \
bitMask = IMASK_MDIO_SCAN_EVENTMDIO; break; \
case e_FM_MAC_EX_10G_MDIO_CMD_CMPL: \
bitMask = IMASK_MDIO_CMD_CMPL ; break; \
case e_FM_MAC_EX_10G_REM_FAULT: \
bitMask = IMASK_REM_FAULT ; break; \
case e_FM_MAC_EX_10G_LOC_FAULT: \
bitMask = IMASK_LOC_FAULT ; break; \
case e_FM_MAC_EX_10G_1TX_ECC_ER: \
bitMask = IMASK_1TX_ECC_ER ; break; \
case e_FM_MAC_EX_10G_TX_FIFO_UNFL: \
bitMask = IMASK_TX_FIFO_UNFL ; break; \
case e_FM_MAC_EX_10G_TX_FIFO_OVFL: \
bitMask = IMASK_TX_FIFO_OVFL ; break; \
case e_FM_MAC_EX_10G_TX_ER: \
bitMask = IMASK_TX_ER ; break; \
case e_FM_MAC_EX_10G_RX_FIFO_OVFL: \
bitMask = IMASK_RX_FIFO_OVFL ; break; \
case e_FM_MAC_EX_10G_RX_ECC_ER: \
bitMask = IMASK_RX_ECC_ER ; break; \
case e_FM_MAC_EX_10G_RX_JAB_FRM: \
bitMask = IMASK_RX_JAB_FRM ; break; \
case e_FM_MAC_EX_10G_RX_OVRSZ_FRM: \
bitMask = IMASK_RX_OVRSZ_FRM ; break; \
case e_FM_MAC_EX_10G_RX_RUNT_FRM: \
bitMask = IMASK_RX_RUNT_FRM ; break; \
case e_FM_MAC_EX_10G_RX_FRAG_FRM: \
bitMask = IMASK_RX_FRAG_FRM ; break; \
case e_FM_MAC_EX_10G_RX_LEN_ER: \
bitMask = IMASK_RX_LEN_ER ; break; \
case e_FM_MAC_EX_10G_RX_CRC_ER: \
bitMask = IMASK_RX_CRC_ER ; break; \
case e_FM_MAC_EX_10G_RX_ALIGN_ER: \
bitMask = IMASK_RX_ALIGN_ER ; break; \
default: bitMask = 0;break;}
/* Default Config Params */
#define DEFAULT_wanModeEnable FALSE
#define DEFAULT_promiscuousModeEnable FALSE
#define DEFAULT_pauseForwardEnable FALSE
#define DEFAULT_pauseIgnore FALSE
#define DEFAULT_txAddrInsEnable FALSE
#define DEFAULT_loopbackEnable FALSE
#define DEFAULT_cmdFrameEnable FALSE
#define DEFAULT_rxErrorDiscard FALSE
#define DEFAULT_phyTxenaOn FALSE
#define DEFAULT_sendIdleEnable FALSE
#define DEFAULT_noLengthCheckEnable TRUE
#define DEFAULT_lgthCheckNostdr FALSE
#define DEFAULT_timeStampEnable FALSE
#define DEFAULT_rxSfdAny FALSE
#define DEFAULT_rxPblFwd FALSE
#define DEFAULT_txPblFwd FALSE
#define DEFAULT_txIpgLength 12
#define DEFAULT_maxFrameLength 0x600
#define DEFAULT_debugMode FALSE
#define DEFAULT_pauseTime 0xf000
#define DEFAULT_imask 0xf000
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
#define DEFAULT_skipFman11Workaround FALSE
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
#define DEFAULT_exceptions ((uint32_t)(IMASK_MDIO_SCAN_EVENTMDIO | \
IMASK_REM_FAULT | \
IMASK_LOC_FAULT | \
IMASK_1TX_ECC_ER | \
IMASK_TX_FIFO_UNFL | \
IMASK_TX_FIFO_OVFL | \
IMASK_TX_ER | \
IMASK_RX_FIFO_OVFL | \
IMASK_RX_ECC_ER | \
IMASK_RX_JAB_FRM | \
IMASK_RX_OVRSZ_FRM | \
IMASK_RX_RUNT_FRM | \
IMASK_RX_FRAG_FRM | \
IMASK_RX_CRC_ER | \
IMASK_RX_ALIGN_ER))
#define MAX_PACKET_ALIGNMENT 31
#define MAX_INTER_PACKET_GAP 0x7f
#define MAX_INTER_PALTERNATE_BEB 0x0f
#define MAX_RETRANSMISSION 0x0f
#define MAX_COLLISION_WINDOW 0x03ff
#define TGEC_NUM_OF_PADDRS 1 /* number of pattern match registers (entries) */
#define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */
#define HASH_TABLE_SIZE 512 /* Hash table size (= 32 bits * 8 regs) */
#define TGEC_TO_MII_OFFSET 0x1030 /* Offset from the MEM map to the MDIO mem map */
/* 10-gigabit Ethernet MAC Controller ID (10GEC_ID) */
#define TGEC_ID_ID 0xffff0000
#define TGEC_ID_MAC_VERSION 0x0000FF00
#define TGEC_ID_MAC_REV 0x000000ff
/* Command and Configuration Register (COMMAND_CONFIG) */
#define CMD_CFG_TX_PBL_FWD 0x00800000 /* 08 Transmit Preamble Forwarding (custom preamble).
*/
#define CMD_CFG_RX_PBL_FWD 0x00400000 /* 09 Receive Preamble Forwarding (custom preamble).
*/
#define RX_SFD_ANY 0x00200000 /* 10 Enables, when set, that any character is allowed at the SFD position of the preamble and the frame will be accepted.
*/
#define CMD_CFG_EN_TIMESTAMP 0x00100000 /* 11 EN_TIMESTAMP IEEE 1588 timeStamp functionality control.
* 0 disabled
* 1 enabled
*/
#define CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* 12 TX_ADDR_INS_SEL Transmit MAC address select
* 0 insert using first MAC address
* 1 insert using second MAC address
*/
#define CMD_CFG_LEN_CHK_NOSTDR 0x00040000 /* 13 LEN_CHK_NOSTDR
*/
#define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 NO_LEN_CHK Payload length check disable
* 0 MAC compares the frame payload length with the frame length/type field.
* 1 Payload length check is disabled.
*/
#define CMD_CFG_SEND_IDLE 0x00010000 /* 15 SEND_IDLE Force idle generation
* 0 Normal operation.
* 1 MAC permanently sends XGMII idle sequences even when faults are received.
*/
#define CMD_CFG_PHY_TX_EN 0x00008000 /* 16 PHY_TX_EN PHY transmit enable
* 0 PHY transmit is disabled.
* 1 PHY transmit is enabled.
*/
#define CMD_CFG_RX_ER_DISC 0x00004000 /* 17 RX_ER_DISC Receive error frame discard enable
* 0 Received error frames are processed.
* 1 Any frame received with an error is discarded.
*/
#define CMD_CFG_CMD_FRM_EN 0x00002000 /* 18 CMD_FRM_EN Command frame reception enable
* 0 Only Pause frames are accepted (all other command frames are rejected).
* 1 All command frames are accepted.
*/
#define CMD_CFG_STAT_CLR 0x00001000 /* 19 STAT_CLR Clear statistics
* 0 Normal operations.
* 1 All statistics counters are cleared.
*/
#define CMD_CFG_LOOPBACK_EN 0x00000400 /* 21 LOOPBAC_EN PHY interface loopback enable
* 0 Configure PHY for normal operation.
* 1 Configure PHY for loopback mode.
*/
#define CMD_CFG_TX_ADDR_INS 0x00000200 /* 22 TX_ADDR_INS Transmit source MAC address insertion
* 0 MAC transmits the source MAC address unmodified.
* 1 MAC overwrites the source MAC address with address specified by COMMAND_CONFIG[TX_ADDR_INS_SEL].
*/
#define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 PAUSE_IGNORE Ignore Pause frame quanta
* 0 MAC stops transmit process for the duration specified in the Pause frame quanta of a received Pause frame.
* 1 MAC ignores received Pause frames.
*/
#define CMD_CFG_PAUSE_FWD 0x00000080 /* 24 PAUSE_FWD Terminate/forward received Pause frames
* 0 MAC terminates and discards received Pause frames.
* 1 MAC forwards Pause frames to the user application.
*/
#define CMD_CFG_PROMIS_EN 0x00000010 /* 27 PROMIS_EN Promiscuous operation enable
* 0 Unicast frames with a destination address not matching the core MAC address (defined by registers, MAC_ADDR_0 and MAC_ADDR_1) are rejected.
* 1 All frames are received without any MAC address filtering.
*/
#define CMD_CFG_WAN_MODE 0x00000008 /* 28 WAN_MODE WAN mode enable
* 0 Configure MAC for LAN mode.
* 1 Configure MAC for WAN mode.
*/
#define CMD_CFG_RX_EN 0x00000002 /* 30 RX_EN MAC receive path enable
* 0 MAC receive path is disabled
* 1 MAC receive path is enabled.
*/
#define CMD_CFG_TX_EN 0x00000001 /* 31 TX_EN MAC transmit path enable
* 0 MAC transmit path is disabled
* 1 MAC transmit path is enabled.
*/
/* Hashtable Control Register (HASHTABLE_CTRL) */
#define HASH_CTRL_MCAST_SHIFT 23
#define HASH_CTRL_MCAST_RD 0x00000400 /* 22 MCAST_READ Entry Multicast frame reception for the hash entry.
* 0 disabled
* 1 enabled
*/
#define HASH_CTRL_MCAST_EN 0x00000200 /* 22 MCAST_EN Multicast frame reception for the hash entry.
* 0 disabled
* 1 enabled
*/
#define HASH_ADDR_MASK 0x000001ff /* 23-31 HASH_ADDR Hash table address code.
*/
/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
#define TX_IPG_LENGTH_MASK 0x000003ff
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/*
* 10G memory map
*/
typedef _Packed struct {
/* 10Ge General Control and Status */
volatile uint32_t tgec_id; /* 0x000 10GEC_ID - Controller ID register */
volatile uint32_t scratch; /* 0x004 */
volatile uint32_t cmd_conf_ctrl; /* 0x008 COMMAND_CONFIG - Control and configuration register */
volatile uint32_t mac_addr_0; /* 0x00C MAC_ADDR_0 - Lower 32 bits of the first 48-bit MAC address */
volatile uint32_t mac_addr_1; /* 0x010 MAC_ADDR_1 - Upper 16 bits of the first 48-bit MAC address */
volatile uint32_t maxfrm; /* 0x014 MAXFRM - Maximum frame length register */
volatile uint32_t pause_quant; /* 0x018 PAUSE_QUANT - Pause quanta register */
volatile uint32_t rx_fifo_sections; /* 0x01c */
volatile uint32_t tx_fifo_sections; /* 0x020 */
volatile uint32_t rx_fifo_almost_f_e; /* 0x024 */
volatile uint32_t tx_fifo_almost_f_e; /* 0x028 */
volatile uint32_t hashtable_ctrl; /* 0x02C HASHTABLE_CTRL - Hash table control register */
volatile uint32_t mdio_cfg_status; /* 0x030 */
volatile uint32_t mdio_command; /* 0x034 */
volatile uint32_t mdio_data; /* 0x038 */
volatile uint32_t mdio_regaddr; /* 0x03c */
volatile uint32_t status; /* 0x040 */
volatile uint32_t tx_ipg_len; /* 0x044 TX_IPG_LENGTH - Transmitter inter-packet-gap register */
volatile uint32_t mac_addr_2; /* 0x048 MAC_ADDR_2 - Lower 32 bits of the second 48-bit MAC address */
volatile uint32_t mac_addr_3; /* 0x04C MAC_ADDR_3 - Upper 16 bits of the second 48-bit MAC address */
volatile uint32_t rx_fifo_ptr_rd; /* 0x050 */
volatile uint32_t rx_fifo_ptr_wr; /* 0x054 */
volatile uint32_t tx_fifo_ptr_rd; /* 0x058 */
volatile uint32_t tx_fifo_ptr_wr; /* 0x05c */
volatile uint32_t imask; /* 0x060 IMASK - Interrupt mask register */
volatile uint32_t ievent; /* 0x064 IEVENT - Interrupt event register */
volatile uint32_t udp_port; /* 0x068 Defines a UDP Port number. When an UDP/IP frame is received with a matching UDP destination port, the receive status indication pin ff_rx_ts_frm will be asserted.*/
volatile uint32_t type_1588v2; /* 0x06c Type field for 1588v2 layer 2 frames. IEEE1588 defines the type 0x88f7 for 1588 frames. */
volatile uint32_t TENGEC_RESERVED4[4];
/*10Ge Statistics Counter */
volatile uint64_t TFRM; /* 80 aFramesTransmittedOK */
volatile uint64_t RFRM; /* 88 aFramesReceivedOK */
volatile uint64_t RFCS; /* 90 aFrameCheckSequenceErrors */
volatile uint64_t RALN; /* 98 aAlignmentErrors */
volatile uint64_t TXPF; /* A0 aPAUSEMACCtrlFramesTransmitted */
volatile uint64_t RXPF; /* A8 aPAUSEMACCtrlFramesReceived */
volatile uint64_t RLONG; /* B0 aFrameTooLongErrors */
volatile uint64_t RFLR; /* B8 aInRangeLengthErrors */
volatile uint64_t TVLAN; /* C0 VLANTransmittedOK */
volatile uint64_t RVLAN; /* C8 VLANReceivedOK */
volatile uint64_t TOCT; /* D0 ifOutOctets */
volatile uint64_t ROCT; /* D8 ifInOctets */
volatile uint64_t RUCA; /* E0 ifInUcastPkts */
volatile uint64_t RMCA; /* E8 ifInMulticastPkts */
volatile uint64_t RBCA; /* F0 ifInBroadcastPkts */
volatile uint64_t TERR; /* F8 ifOutErrors */
volatile uint32_t TENGEC_RESERVED6[2];
volatile uint64_t TUCA; /* 108 ifOutUcastPkts */
volatile uint64_t TMCA; /* 110 ifOutMulticastPkts */
volatile uint64_t TBCA; /* 118 ifOutBroadcastPkts */
volatile uint64_t RDRP; /* 120 etherStatsDropEvents */
volatile uint64_t REOCT; /* 128 etherStatsOctets */
volatile uint64_t RPKT; /* 130 etherStatsPkts */
volatile uint64_t TRUND; /* 138 etherStatsUndersizePkts */
volatile uint64_t R64; /* 140 etherStatsPkts64Octets */
volatile uint64_t R127; /* 148 etherStatsPkts65to127Octets */
volatile uint64_t R255; /* 150 etherStatsPkts128to255Octets */
volatile uint64_t R511; /* 158 etherStatsPkts256to511Octets */
volatile uint64_t R1023; /* 160 etherStatsPkts512to1023Octets */
volatile uint64_t R1518; /* 168 etherStatsPkts1024to1518Octets */
volatile uint64_t R1519X; /* 170 etherStatsPkts1519toX */
volatile uint64_t TROVR; /* 178 etherStatsOversizePkts */
volatile uint64_t TRJBR; /* 180 etherStatsJabbers */
volatile uint64_t TRFRG; /* 188 etherStatsFragments */
volatile uint64_t RERR; /* 190 ifInErrors */
} _PackedType t_TgecMemMap;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
typedef struct {
bool wanModeEnable; /* WAN Mode Enable. Sets WAN mode (1) or LAN mode (0, default) of operation. */
bool promiscuousModeEnable; /* Enables MAC promiscuous operation. When set to '1', all frames are received without any MAC address filtering, when set to '0' (Reset value) Unicast Frames with a destination address not matching the Core MAC Address (MAC Address programmed in Registers MAC_ADDR_0 and MAC_ADDR_1 or the MAC address programmed in Registers MAC_ADDR_2 and MAC_ADDR_3 ) are rejected. */
bool pauseForwardEnable; /* Terminate / Forward Pause Frames. If set to '1' pause frames are forwarded to the user application. When set to '0' (Reset value) pause frames are terminated and discarded within the MAC. */
bool pauseIgnore; /* Ignore Pause Frame Quanta. If set to '1' received pause frames are ignored by the MAC. When set to '0' (Reset value) the transmit process is stopped for the amount of time specified in the pause quanta received within a pause frame. */
bool txAddrInsEnable; /* Set Source MAC Address on Transmit.
If set to '1' the MAC overwrites the source MAC address received from the Client Interface with one of the MAC addresses (Refer to section 10.4)
If set to '0' (Reset value), the source MAC address from the Client Interface is transmitted unmodified to the line. */
bool loopbackEnable; /* PHY Interface Loopback. When set to '1', the signal loop_ena is set to '1', when set to '0' (Reset value) the signal loop_ena is set to '0'. */
bool cmdFrameEnable; /* Enables reception of all command frames. When set to '1' all Command Frames are accepted, when set to '0' (Reset Value) only Pause Frames are accepted and all other Command Frames are rejected. */
bool rxErrorDiscard; /* Receive Errored Frame Discard Enable. When set to ‘1’, any frame received with an error is discarded in the Core and not forwarded to the Client interface. When set to ‘0’ (Reset value), errored Frames are forwarded to the Client interface with ff_rx_err asserted. */
bool phyTxenaOn; /* PHY Transmit Enable. When set to '1', the signal phy_txena is set to '1', when set to '0' (Reset value) the signal phy_txena is set to '0' */
bool sendIdleEnable; /* Force Idle Generation. When set to '1', the MAC permanently sends XGMII Idle sequences even when faults are received. */
bool noLengthCheckEnable; /* Payload Length Check Disable. When set to ‘0’ (Reset value), the Core checks the frame's payload length with the Frame Length/Type field, when set to ‘1’, the payload length check is disabled. */
bool lgthCheckNostdr; /* The Core interprets the Length/Type field differently depending on the value of this Bit */
bool timeStampEnable; /* This bit selects between enabling and disabling the IEEE 1588 functionality.
1: IEEE 1588 is enabled.
0: IEEE 1588 is disabled. */
bool rxSfdAny; /* Enables, when set, that any character is allowed at the SFD position of the preamble and the frame will be accepted.
If cleared (default) the frame is accepted only if the 8th byte of the preamble contains the SFD value 0xd5. If another value is received, the frame is discarded and the alignment error counter increments. */
bool rxPblFwd; /* Receive Preamble Forwarding (custom preamble).
If set, the first word (ff_rx_sop) of every received frame contains the preamble of the frame. The frame data starts with the 2nd word from the FIFO.
If the bit is cleared (default) the preamble is removed from the frame before it is written into the receive FIFO. */
bool txPblFwd; /* Transmit Preamble Forwarding (custom preamble).
If set, the first word written into the TX FIFO is considered as frame preamble. The MAC will not add a preamble in front of the frame. Note that bits 7:0 of the preamble word will still be overwritten with the XGMII start character upon transmission.
If cleared (default) the MAC */
uint32_t txIpgLength; /*Transmit Inter-Packet-Gap (IPG) value.
A 6-bit value: Depending on LAN or WAN mode of operation (see COMMAND_CONFIG, 19.2.1 page 91) the value has the following meaning:
- LAN Mode: Number of octets in steps of 4. Valid values are 8, 12, 16, ... 100. DIC is fully supported (see 10.6.1 page 49) for any setting. A default of 12 (reset value) must be set to conform to IEEE802.3ae. Warning: When set to 8, PCS layers may not be able to perform clock rate compensation.
- WAN Mode: Stretch factor. Valid values are 4..15. The stretch factor is calculated as (value+1)*8. A default of 12 (reset value) must be set to conform to IEEE 802.3ae (i.e. 13*8=104). A larger value shrinks the IPG (increasing bandwidth). */
/*.. */
uint16_t maxFrameLength;
bool debugMode;
uint16_t pauseTime;
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
bool skipFman11Workaround;
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
} t_TgecDriverParam;
typedef struct {
t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */
t_Handle h_App; /**< Handle to the upper layer application */
t_TgecMemMap *p_MemMap; /**< pointer to 10G memory mapped registers. */
t_TgecMiiAccessMemMap *p_MiiMemMap; /**< pointer to MII memory mapped registers. */
uint64_t addr; /**< MAC address of device; */
e_EnetMode enetMode; /**< Ethernet physical interface */
t_FmMacExceptionCallback *f_Exception;
int mdioIrq;
t_FmMacExceptionCallback *f_Event;
bool indAddrRegUsed[TGEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
uint64_t paddr[TGEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
t_EthHash *p_MulticastAddrHash; /**< pointer to driver's global address hash table */
t_EthHash *p_UnicastAddrHash; /**< pointer to driver's individual address hash table */
bool debugMode;
uint8_t macId;
uint32_t exceptions;
t_TgecDriverParam *p_TgecDriverParam;
} t_Tgec;
t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t data);
t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#endif /* __TGEC_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "error_ext.h"
#include "std_ext.h"
#include "fm_mac.h"
#include "tgec.h"
#include "xx_ext.h"
/*****************************************************************************/
t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec,
uint8_t phyAddr,
uint8_t reg,
uint16_t data)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
t_TgecMiiAccessMemMap *p_MiiAccess;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Tgec->p_MiiMemMap;
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
CORE_MemoryBarrier();
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
WRITE_UINT32(p_MiiAccess->mdio_data, data);
CORE_MemoryBarrier();
while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
XX_UDelay (1);
return E_OK;
}
/*****************************************************************************/
t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,
uint8_t phyAddr,
uint8_t reg,
uint16_t *p_Data)
{
t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
t_TgecMiiAccessMemMap *p_MiiAccess;
uint32_t cfg_status;
SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
p_MiiAccess = p_Tgec->p_MiiMemMap;
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
CORE_MemoryBarrier();
while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
XX_UDelay (1);
WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE));
CORE_MemoryBarrier();
while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
XX_UDelay (1);
*p_Data = (uint16_t)GET_UINT32(p_MiiAccess->mdio_data);
cfg_status = GET_UINT32(p_MiiAccess->mdio_cfg_status);
if (cfg_status & MIIMIND_READ_ERROR)
RETURN_ERROR(MINOR, E_INVALID_VALUE,
("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfg_status 0x%x",
((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfg_status));
return E_OK;
}

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __TGEC_MII_ACC_H
#define __TGEC_MII_ACC_H
#include "std_ext.h"
/* MII Management Command Register */
#define MIIMCOM_READ_POST_INCREMENT 0x00004000
#define MIIMCOM_READ_CYCLE 0x00008000
#define MIIMCOM_SCAN_CYCLE 0x00000800
#define MIIMCOM_PREAMBLE_DISABLE 0x00000400
#define MIIMCOM_MDIO_HOLD_1_REG_CLK 0
#define MIIMCOM_MDIO_HOLD_2_REG_CLK 1
#define MIIMCOM_MDIO_HOLD_3_REG_CLK 2
#define MIIMCOM_MDIO_HOLD_4_REG_CLK 3
#define MIIMCOM_DIV_MASK 0x0000ff00
#define MIIMCOM_DIV_SHIFT 8
/* MII Management Indicator Register */
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_READ_ERROR 0x00000002
#define MIIDATA_BUSY 0x80000000
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/*----------------------------------------------------*/
/* MII Configuration Control Memory Map Registers */
/*----------------------------------------------------*/
typedef _Packed struct t_TgecMiiAccessMemMap
{
volatile uint32_t mdio_cfg_status; /* 0x030 */
volatile uint32_t mdio_command; /* 0x034 */
volatile uint32_t mdio_data; /* 0x038 */
volatile uint32_t mdio_regaddr; /* 0x03c */
} _PackedType t_TgecMiiAccessMemMap ;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
#endif /* __TGEC_MII_ACC_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_cc.h
@Description FM PCD CC ...
*//***************************************************************************/
#ifndef __FM_CC_H
#define __FM_CC_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_pcd.h"
/***********************************************************************/
/* Coarse classification defines */
/***********************************************************************/
#define CC_PC_FF_MACDST 0x00
#define CC_PC_FF_MACSRC 0x01
#define CC_PC_FF_ETYPE 0x02
#define CC_PC_FF_TCI1 0x03
#define CC_PC_FF_TCI2 0x04
#define CC_PC_FF_MPLS1 0x06
#define CC_PC_FF_MPLS_LAST 0x07
#define CC_PC_FF_IPV4DST1 0x08
#define CC_PC_FF_IPV4DST2 0x16
#define CC_PC_FF_IPV4IPTOS_TC1 0x09
#define CC_PC_FF_IPV4IPTOS_TC2 0x17
#define CC_PC_FF_IPV4PTYPE1 0x0A
#define CC_PC_FF_IPV4PTYPE2 0x18
#define CC_PC_FF_IPV4SRC1 0x0b
#define CC_PC_FF_IPV4SRC2 0x19
#define CC_PC_FF_IPV4SRC1_IPV4DST1 0x0c
#define CC_PC_FF_IPV4SRC2_IPV4DST2 0x1a
#define CC_PC_FF_IPV4TTL 0x29
#define CC_PC_FF_IPTOS_IPV6TC1_IPV6FLOW1 0x0d /*TODO - CLASS - what is it? TOS*/
#define CC_PC_FF_IPTOS_IPV6TC2_IPV6FLOW2 0x1b
#define CC_PC_FF_IPV6PTYPE1 0x0e
#define CC_PC_FF_IPV6PTYPE2 0x1c
#define CC_PC_FF_IPV6DST1 0x0f
#define CC_PC_FF_IPV6DST2 0x1d
#define CC_PC_FF_IPV6SRC1 0x10
#define CC_PC_FF_IPV6SRC2 0x1e
#define CC_PC_FF_IPV6HOP_LIMIT 0x2a
#define CC_PC_FF_GREPTYPE 0x11
#define CC_PC_FF_MINENCAP_PTYPE 0x12
#define CC_PC_FF_MINENCAP_IPDST 0x13
#define CC_PC_FF_MINENCAP_IPSRC 0x14
#define CC_PC_FF_MINENCAP_IPSRC_IPDST 0x15
#define CC_PC_FF_L4PSRC 0x1f
#define CC_PC_FF_L4PDST 0x20
#define CC_PC_FF_L4PSRC_L4PDST 0x21
#define CC_PC_FF_PPPPID 0x05
#define CC_PC_PR_SHIM1 0x22
#define CC_PC_PR_SHIM2 0x23
#define CC_PC_GENERIC_WITHOUT_MASK 0x27
#define CC_PC_GENERIC_WITH_MASK 0x28
#define CC_PC_GENERIC_IC_GMASK 0x2B
#define CC_PC_GENERIC_IC_HASH_INDEXED 0x2C
#define CC_PR_OFFSET 0x25
#define CC_PR_WITHOUT_OFFSET 0x26
#define CC_PC_PR_ETH_OFFSET 19
#define CC_PC_PR_USER_DEFINED_SHIM1_OFFSET 16
#define CC_PC_PR_USER_DEFINED_SHIM2_OFFSET 17
#define CC_PC_PR_USER_LLC_SNAP_OFFSET 20
#define CC_PC_PR_VLAN1_OFFSET 21
#define CC_PC_PR_VLAN2_OFFSET 22
#define CC_PC_PR_PPPOE_OFFSET 24
#define CC_PC_PR_MPLS1_OFFSET 25
#define CC_PC_PR_MPLS_LAST_OFFSET 26
#define CC_PC_PR_IP1_OFFSET 27
#define CC_PC_PR_IP_LAST_OFFSET 28
#define CC_PC_PR_MINENC_OFFSET 28
#define CC_PC_PR_L4_OFFSET 30
#define CC_PC_PR_GRE_OFFSET 29
#define CC_PC_PR_ETYPE_LAST_OFFSET 23
#define CC_PC_PR_NEXT_HEADER_OFFSET 31
#define CC_PC_ILLEGAL 0xff
#define CC_SIZE_ILLEGAL 0
#define FM_PCD_CC_KEYS_MATCH_TABLE_ALIGN 16
#define FM_PCD_CC_AD_TABLE_ALIGN 256
#define FM_PCD_CC_AD_ENTRY_SIZE 16
#define FM_PCD_CC_NUM_OF_KEYS 255
#define FM_PCD_AD_RESULT_CONTRL_FLOW_TYPE 0x00000000
#define FM_PCD_AD_RESULT_DATA_FLOW_TYPE 0x80000000
#define FM_PCD_AD_RESULT_PLCR_DIS 0x20000000
#define FM_PCD_AD_RESULT_EXTENDED_MODE 0x80000000
#define FM_PCD_AD_RESULT_NADEN 0x20000000
#define FM_PCD_AD_RESULT_STATISTICS_EN 0x40000000
#define FM_PCD_AD_CONT_LOOKUP_TYPE 0x40000000
#define FM_PCD_AD_CONT_LOOKUP_LCL_MASK 0x00800000
#define FM_PCD_AD_TYPE_MASK 0xc0000000
#define FM_PCD_AD_OPCODE_MASK 0x0000000f
#define FM_PCD_AD_PROFILEID_FOR_CNTRL_SHIFT 16
#define GLBL_MASK_FOR_HASH_INDEXED 0xfff00000
#define CC_GLBL_MASK_SIZE 4
typedef uint32_t ccPrivateInfo_t; /**< private info of CC: */
#define CC_PRIVATE_INFO_NONE 0
#define CC_PRIVATE_INFO_IC_HASH_INDEX_LOOKUP 0x80000000
#define CC_PRIVATE_INFO_IC_HASH_EXACT_MATCH 0x40000000
#define CC_PRIVATE_INFO_IC_KEY_EXACT_MATCH 0x20000000
#define CC_PRIVATE_INFO_IC_DEQ_FQID_INDEX_LOOKUP 0x10000000
/***********************************************************************/
/* Memory map */
/***********************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct {
volatile uint32_t fqid;
volatile uint32_t plcrProfile;
volatile uint32_t nia;
volatile uint32_t res;
} _PackedType t_AdOfTypeResult;
typedef _Packed struct {
volatile uint32_t ccAdBase;
volatile uint32_t matchTblPtr;
volatile uint32_t pcAndOffsets;
volatile uint32_t gmask;
} _PackedType t_AdOfTypeContLookup;
typedef _Packed union {
volatile t_AdOfTypeResult adResult;
volatile t_AdOfTypeContLookup adContLookup;
} _PackedType t_Ad;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/***********************************************************************/
/* Driver's internal structures */
/***********************************************************************/
typedef enum e_ModifyState {
e_MODIFY_STATE_ADD = 0,
e_MODIFY_STATE_REMOVE,
e_MODIFY_STATE_CHANGE
} e_ModifyState;
typedef struct {
t_FmPcdCcNextEngineParams nextEngineParams;
uint32_t requiredAction;
uint32_t shadowAction;
} t_FmPcdCcNextEngineAndRequiredActionParams;
typedef struct {
t_Handle p_Ad;
e_FmPcdEngine fmPcdEngine;
bool adAllocated;
bool isTree;
uint32_t myInfo;
t_List *h_CcNextNodesLst;
t_Handle h_AdditionalInfo;
t_Handle h_Node;
} t_FmPcdModifyCcAdditionalParams;
typedef struct {
t_Handle p_AdTableNew;
t_Handle p_KeysMatchTableNew;
t_Handle p_AdTableOld;
t_Handle p_KeysMatchTableOld;
uint16_t numOfKeys;
t_Handle h_CurrentNode;
uint16_t keyIndex;
t_Handle h_NodeForAdd;
t_Handle h_NodeForRmv;
t_Handle h_ManipForRmv;
bool tree;
t_FmPcdCcNextEngineAndRequiredActionParams nextEngineAndRequiredAction[256];
} t_FmPcdModifyCcKeyAdditionalParams;
typedef struct {
t_Handle h_Manip;
t_Handle h_CcNode;
} t_CcNextEngineInfo;
typedef struct {
uint16_t numOfKeys;
bool glblMaskUpdated;
t_Handle p_GlblMask;
bool lclMask;
uint8_t parseCode;
uint8_t offset;
uint8_t prsArrayOffset;
bool ctrlFlow;
uint8_t owners;
uint8_t ccKeySizeAccExtraction;
uint8_t sizeOfExtraction;
uint8_t glblMaskSize;
t_Handle h_KeysMatchTable;
t_Handle h_AdTable;
t_List ccPrevNodesLst;
t_List ccTreeIdLst;
t_List ccTreesLst;
t_Handle h_FmPcd;
uint32_t shadowAction;
bool modifiedState;
uint8_t userSizeOfExtraction;
t_FmPcdCcNextEngineAndRequiredActionParams nextEngineAndRequiredAction[256];
} t_FmPcdCcNode;
typedef struct {
t_FmPcdCcNode *p_FmPcdCcNode;
bool occupied;
uint8_t owners;
volatile bool lock;
} t_FmPcdCcNodeArray;
typedef struct {
uint8_t numOfEntriesInGroup;
uint32_t totalBitsMask;
uint8_t baseGroupEntry;
} t_FmPcdCcGroupParam;
typedef struct {
uint8_t netEnvId;
uintptr_t ccTreeBaseAddr;
uint8_t numOfGrps;
t_FmPcdCcGroupParam fmPcdGroupParam[FM_PCD_MAX_NUM_OF_CC_GROUPS];
t_List fmPortsLst;
volatile bool lock;
uint8_t numOfEntries;
uint8_t owners;
t_Handle *fmPcdCcSavedManipParams[256];
bool modifiedState;
uint32_t requiredAction;
t_FmPcdCcNextEngineAndRequiredActionParams nextEngineAndRequiredAction[FM_PCD_MAX_NUM_OF_KEYS];
} t_FmPcdCcTree;
typedef struct {
t_FmPcdCcTree *p_FmPcdCcTree;
bool occupied;
uint8_t owners;
volatile bool lock;
} t_FmPcdCcTreeArray;
bool FmPcdManipIsManipNode(t_Handle h_Ad);
#endif /* __FM_CC_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_manip.h
@Description FM PCD manip...
*//***************************************************************************/
#ifndef __FM_MANIP_H
#define __FM_MANIP_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_cc.h"
/***********************************************************************/
/* Header manipulations defines */
/***********************************************************************/
#define HMAN_OC_RMV_N_OR_INSRT_INT_FRM_HDR 0x2e
#define HMAN_OC_INSRT_HDR_BY_TEMPL_N_OR_FRAG_AFTER 0x31
#define HMAN_OC_CAPWAP_FRAGMENTATION 0x33
#define HMAN_OC_IPSEC 0x34
#define HMAN_OC_IP_FRAGMENTATION 0x74
#define HMAN_OC_IP_REASSEMBLY 0xB4
#define HMAN_OC_MV_INT_FRAME_HDR_FROM_FRM_TO_BUFFER_PREFFIX 0x2f
#define HMAN_OC_CAPWAP_RMV_DTLS_IF_EXIST 0x30
#define HMAN_OC_CAPWAP_REASSEMBLY 0x11 /* dummy */
#define HMAN_OC_CAPWAP_INDEXED_STATS 0x32 /* dummy */
#define HMAN_RMV_HDR 0x80000000
#define HMAN_INSRT_INT_FRM_HDR 0x40000000
#define UDP_UDPHECKSUM_FIELD_OFFSET_FROM_UDP 6
#define UDP_UDPCHECKSUM_FIELD_SIZE 2
#define IP_DSCECN_FIELD_OFFSET_FROM_IP 1
#define IP_TOTALLENGTH_FIELD_OFFSET_FROM_IP 2
#define IP_HDRCHECKSUM_FIELD_OFFSET_FROM_IP 10
#define VLAN_TAG_FIELD_OFFSET_FROM_ETH 12
#define IP_ID_FIELD_OFFSET_FROM_IP 4
#define FM_PCD_MANIP_CAPWAP_REASM_TABLE_SIZE 80
#define FM_PCD_MANIP_CAPWAP_REASM_TABLE_ALIGN 8
#define FM_PCD_MANIP_CAPWAP_REASM_RFD_SIZE 32
#define FM_PCD_MANIP_CAPWAP_REASM_AUTO_LEARNING_HASH_ENTRY_SIZE 4
#define FM_PCD_MANIP_CAPWAP_REASM_TIME_OUT_ENTRY_SIZE 8
#define FM_PCD_MANIP_CAPWAP_REASM_TIME_OUT_BETWEEN_FRAMES 0x40000000
#define FM_PCD_MANIP_CAPWAP_REASM_HALT_ON_DUPLICATE_FRAG 0x10000000
#define FM_PCD_MANIP_CAPWAP_REASM_AUTOMATIC_LEARNIN_HASH_8_WAYS 0x08000000
#define FM_PCD_MANIP_CAPWAP_REASM_PR_COPY 0x00800000
#define FM_PCD_MANIP_CAPWAP_FRAG_COMPR_OPTION_FIELD_EN 0x80000000
#define FM_PCD_MANIP_INDEXED_STATS_ENTRY_SIZE 4
#define FM_PCD_MANIP_INDEXED_STATS_CNIA 0x20000000
#define FM_PCD_MANIP_INDEXED_STATS_DPD 0x10000000
#define FM_PCD_MANIP_IPSEC_CALC_UDP_LENGTH 0x01000000
#define FM_PCD_MANIP_IPSEC_CNIA 0x20000000
#define e_FM_MANIP_CAPWAP_INDX 0
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
#define FM_PCD_MANIP_IP_REASM_TABLE_SIZE 0x40
#define FM_PCD_MANIP_IP_REASM_TABLE_ALIGN 8
#define FM_PCD_MANIP_IP_REASM_COMMON_PARAM_TABLE_SIZE 64
#define FM_PCD_MANIP_IP_REASM_COMMON_PARAM_TABLE_ALIGN 8
#define FM_PCD_MANIP_IP_REASM_TIME_OUT_BETWEEN_FRAMES 0x80000000
#define e_FM_MANIP_IP_INDX 1
#define FM_PCD_MANIP_IP_REASM_LIODN_MASK 0x000003F0
#define FM_PCD_MANIP_IP_REASM_LIODN_SHIFT 56
#define FM_PCD_MANIP_IP_REASM_ELIODN_MASK 0x0000000F
#define FM_PCD_MANIP_IP_REASM_ELIODN_SHIFT 44
#endif /* UNDER_CONSTRUCTION_FRAG_REASSEMBLY */
/***********************************************************************/
/* Memory map */
/***********************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
typedef _Packed struct {
volatile uint32_t mode;
volatile uint32_t autoLearnHashTblPtr;
volatile uint32_t intStatsTblPtr;
volatile uint32_t reasmFrmDescPoolTblPtr;
volatile uint32_t reasmFrmDescIndexPoolTblPtr;
volatile uint32_t timeOutTblPtr;
volatile uint32_t bufferPoolIdAndRisc1SetIndexes;
volatile uint32_t risc23SetIndexes;
volatile uint32_t risc4SetIndexesAndExtendedStatsTblPtr;
volatile uint32_t extendedStatsTblPtr;
volatile uint32_t expirationDelay;
volatile uint32_t totalProcessedFragCounter;
volatile uint32_t totalUnsuccessfulReasmFramesCounter;
volatile uint32_t totalDuplicatedFragCounter;
volatile uint32_t totalMalformdFragCounter;
volatile uint32_t totalTimeOutCounter;
volatile uint32_t totalSetBusyCounter;
volatile uint32_t totalRfdPoolBusyCounter;
volatile uint32_t totalDiscardedFragsCounter;
volatile uint32_t totalMoreThan16FramesCounter;
volatile uint32_t internalBufferBusy;
volatile uint32_t externalBufferBusy;
volatile uint8_t res[16];
} _PackedType t_CapwapReasmPram;
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
typedef _Packed struct t_IpReasmPram{
volatile uint16_t waysNumAndSetSize;
volatile uint16_t autoLearnHashKeyMask;
volatile uint32_t ipReassCommonPrmTblPtr;
volatile uint32_t liodnAlAndAutoLearnHashTblPtrHi;
volatile uint32_t autoLearnHashTblPtrLow;
volatile uint32_t liodnSlAndAutoLearnSetLockTblPtrHi;
volatile uint32_t autoLearnSetLockTblPtrLow;
volatile uint16_t minFragSize;
volatile uint16_t reserved1;
volatile uint32_t totalSuccessfullyReasmFramesCounter;
volatile uint32_t totalValidFragmentCounter;
volatile uint32_t totalProcessedFragCounter;
volatile uint32_t totalMalformdFragCounter;
volatile uint32_t totalSetBusyCounter;
volatile uint32_t totalDiscardedFragsCounter;
volatile uint32_t totalMoreThan16FramesCounter;
volatile uint32_t reserved2[2];
} _PackedType t_IpReasmPram;
typedef _Packed struct t_IpReasmCommonTbl{
volatile uint32_t timeoutModeAndFqid;
volatile uint32_t reassFrmDescIndexPoolTblPtr;
volatile uint32_t liodnAndReassFrmDescPoolPtrHi;
volatile uint32_t reassFrmDescPoolPtrLow;
volatile uint32_t timeOutTblPtr;
volatile uint32_t expirationDelay;
volatile uint32_t reseervd1;
volatile uint32_t reseervd2;
volatile uint32_t totalTimeOutCounter;
volatile uint32_t totalRfdPoolBusyCounter;
volatile uint32_t totalInternalBufferBusy;
volatile uint32_t totalExternalBufferBusy;
volatile uint32_t reserved3[4];
} _PackedType t_IpReasmCommonTbl;
#endif /*UNDER_CONSTRUCTION_FRAG_REASSEMBLY*/
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/***********************************************************************/
/* Driver's internal structures */
/***********************************************************************/
typedef struct
{
t_Handle p_AutoLearnHashTbl;
t_Handle p_ReassmFrmDescrPoolTbl;
t_Handle p_ReassmFrmDescrIndxPoolTbl;
t_Handle p_TimeOutTbl;
uint8_t maxNumFramesInProcess;
uint8_t numOfTasks;
uint8_t poolId;
uint8_t prOffset;
uint16_t dataOffset;
uint8_t poolIndx;
uint8_t hwPortId;
uint32_t fqidForTimeOutFrames;
uint32_t timeoutRoutineRequestTime;
uint32_t bitFor1Micro;
} t_FragParams;
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
typedef struct
{
t_Handle h_Frag;
t_Handle h_FragId;
uint8_t poolId;
uint16_t dataOffset;
uint8_t poolIndx;
}t_IpFragParams;
typedef struct t_IpReassmParams
{
t_Handle h_Ipv4Ad;
t_Handle h_Ipv6Ad;
e_NetHeaderType hdr; /**< Header selection */
uint32_t fqidForTimeOutFrames;
uint16_t dataOffset;
t_Handle h_IpReassCommonParamsTbl;
t_Handle h_Ipv4ReassParamsTblPtr;
t_Handle h_Ipv6ReassParamsTblPtr;
t_Handle h_Ipv4AutoLearnHashTbl;
t_Handle h_Ipv6AutoLearnHashTbl;
t_Handle h_Ipv4AutoLearnSetLockTblPtr;
t_Handle h_Ipv6AutoLearnSetLockTblPtr;
t_Handle h_ReassmFrmDescrIndxPoolTbl;
t_Handle h_ReassmFrmDescrPoolTbl;
t_Handle h_TimeOutTbl;
uint32_t maxNumFramesInProcess;
uint32_t liodnOffset;
uint32_t minFragSize;
uint8_t dataMemId; /**< Memory partition ID for data buffers */
uint32_t bpid;
e_FmPcdManipReassemTimeOutMode timeOutMode;
e_FmPcdManipReassemWaysNumber numOfFramesPerHashEntry;
uint32_t timeoutThresholdForReassmProcess;
}t_IpReassmParams;
typedef struct t_IpCommonReassmParams
{
uint8_t numOfTasks;
uint32_t bitFor1Micro;
t_Handle h_ReassmFrmDescrPoolTbl;
t_Handle h_ReassmFrmDescrIndxPoolTbl;
t_Handle h_TimeOutTbl;
}t_IpCommonReassmParams;
#endif /*UNDER_CONSTRUCTION_FRAG_REASSEMBLY*/
typedef struct{
bool muramAllocate;
t_Handle h_Ad;
uint32_t type;
bool rmv;
bool insrt;
uint8_t *p_Template;
t_Handle h_Frag;
bool frag;
bool reassm;
uint16_t sizeForFragmentation;
uint8_t owner;
uint32_t updateParams;
uint32_t shadowUpdateParams;
t_FragParams fragParams;
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
t_IpReassmParams ipReassmParams;
t_IpFragParams ipFragParams;
#endif /* UNDER_CONSTRUCTION_FRAG_REASSEMBLY */
uint8_t icOffset;
uint16_t ownerTmp;
bool cnia;
t_Handle p_StatsTbl;
t_Handle h_FmPcd;
} t_FmPcdManip;
typedef struct t_FmPcdCcSavedManipParams
{
union
{
struct
{
uint16_t dataOffset;
uint8_t poolId;
}capwapParams;
#ifdef UNDER_CONSTRUCTION_FRAG_REASSEMBLY
struct
{
uint16_t dataOffset;
uint8_t poolId;
}ipParams;
#endif /*UNDER_CONSTRUCTION_FRAG_REASSEMBLY*/
};
} t_FmPcdCcSavedManipParams;
#endif /* __FM_MANIP_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_pcd.h
@Description FM PCD ...
*//***************************************************************************/
#ifndef __FM_PCD_H
#define __FM_PCD_H
#include "std_ext.h"
#include "error_ext.h"
#include "list_ext.h"
#include "fm_pcd_ext.h"
#define __ERR_MODULE__ MODULE_FM_PCD
/**************************************************************************//**
@Group FM_PCD_Runtime_grp FM PCD Runtime Unit
@{
*//***************************************************************************/
/****************************/
/* Network defines */
/****************************/
#define UDP_HEADER_SIZE 8
#define ESP_SPI_OFFSET 0
#define ESP_SPI_SIZE 4
#define ESP_SEQ_NUM_OFFSET ESP_SPI_SIZE
#define ESP_SEQ_NUM_SIZE 4
/****************************/
/* General defines */
/****************************/
#define ILLEGAL_CLS_PLAN 0xff
#define ILLEGAL_NETENV 0xff
/****************************/
/* Error defines */
/****************************/
#define FM_PCD_EX_KG_DOUBLE_ECC 0x80000000
#define FM_PCD_EX_KG_KEYSIZE_OVERFLOW 0x40000000
#define FM_PCD_EX_PLCR_DOUBLE_ECC 0x20000000
#define FM_PCD_EX_PLCR_INIT_ENTRY_ERROR 0x10000000
#define FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE 0x08000000
#define FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE 0x04000000
#define FM_PCD_EX_PRS_DOUBLE_ECC 0x02000000
#define FM_PCD_EX_PRS_SINGLE_ECC 0x01000000
#define GET_FM_PCD_EXCEPTION_FLAG(bitMask, exception) \
switch(exception){ \
case e_FM_PCD_KG_EXCEPTION_DOUBLE_ECC: \
bitMask = FM_PCD_EX_KG_DOUBLE_ECC; break; \
case e_FM_PCD_PLCR_EXCEPTION_DOUBLE_ECC: \
bitMask = FM_PCD_EX_PLCR_DOUBLE_ECC; break; \
case e_FM_PCD_KG_EXCEPTION_KEYSIZE_OVERFLOW: \
bitMask = FM_PCD_EX_KG_KEYSIZE_OVERFLOW; break; \
case e_FM_PCD_PLCR_EXCEPTION_INIT_ENTRY_ERROR: \
bitMask = FM_PCD_EX_PLCR_INIT_ENTRY_ERROR; break; \
case e_FM_PCD_PLCR_EXCEPTION_PRAM_SELF_INIT_COMPLETE: \
bitMask = FM_PCD_EX_PLCR_PRAM_SELF_INIT_COMPLETE; break; \
case e_FM_PCD_PLCR_EXCEPTION_ATOMIC_ACTION_COMPLETE: \
bitMask = FM_PCD_EX_PLCR_ATOMIC_ACTION_COMPLETE; break; \
case e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC: \
bitMask = FM_PCD_EX_PRS_DOUBLE_ECC; break; \
case e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC: \
bitMask = FM_PCD_EX_PRS_SINGLE_ECC; break; \
default: bitMask = 0;break;}
/***********************************************************************/
/* SW parser L4 shells patch */
/***********************************************************************/
#ifdef FM_PRS_L4_SHELL_ERRATA_FMANb
#define SW_PRS_L4_PATCH \
{ 0x31,0x92,0x02,0x1f,0x00,0x32,0x00,0x78, \
0x00,0x34,0x32,0xf0,0x00,0x50,0x00,0x0c, \
0x28,0x5e,0x83,0x8e,0x29,0x32,0xaf,0x8e, \
0x31,0xb2,0x9f,0xff,0x00,0x06,0xaf,0xbf, \
0x00,0x06,0x29,0x36,0x00,0x01,0x1b,0xff, \
0x32,0xf0,0x00,0x50,0x00,0x08,0x28,0x5e, \
0x08,0x99,0x00,0x00,0x9f,0x8e,0x31,0xb2, \
0x9f,0xff,0x00,0x06,0x29,0x36,0x00,0x01, \
0x1b,0xff,0x32,0xf0,0x00,0x50,0x00,0x04, \
0x28,0x5e,0x8f,0x9e,0x29,0x32,0x31,0xb2, \
0x8f,0xbf,0x00,0x06,0x29,0x36,0x00,0x01, \
0x1b,0xff,0x32,0xf0,0x00,0x50,0x00,0x04, \
0x28,0x5e,0x8f,0x9e,0x29,0x32,0x31,0xb2, \
0x8f,0xbf,0x00,0x06,0x29,0x36,0x00,0x01, \
0x1b,0xff,0x00,0x00,0x00,0x00,0x00,0x00};
#define SW_PRS_L4_PATCH_SIZE 120
#endif /* FM_PRS_L4_SHELL_ERRATA_FMANb */
/****************************/
/* Parser defines */
/****************************/
/* masks */
#define PRS_ERR_CAP 0x80000000
#define PRS_ERR_TYPE_DOUBLE 0x40000000
#define PRS_ERR_SINGLE_ECC_CNT_MASK 0x00FF0000
#define PRS_ERR_ADDR_MASK 0x000001FF
#define FM_PCD_PRS_RPIMAC_EN 0x00000001
#define FM_PCD_PRS_SINGLE_ECC 0x00004000
#define FM_PCD_PRS_PORT_IDLE_STS 0xffff0000
#define FM_PCD_PRS_DOUBLE_ECC 0x00004000
#define FM_PCD_PRS_PPSC_ALL_PORTS 0xffff0000
/* others */
#define PRS_MAX_CYCLE_LIMIT 8191
#define PRS_SW_DATA 0x00000800
#define PRS_REGS_OFFSET 0x00000840
#define GET_FM_PCD_PRS_PORT_ID(prsPortId,hardwarePortId) \
prsPortId = (uint8_t)(hardwarePortId & 0x0f)
#define GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId) \
bitMask = 0x80000000>>prsPortId
/***********************************************************************/
/* Keygen defines */
/***********************************************************************/
/* Masks */
#define FM_PCD_KG_KGGCR_EN 0x80000000
#define KG_SCH_GEN_VALID 0x80000000
#define KG_SCH_GEN_EXTRACT_TYPE 0x00008000
#define KG_ERR_CAP 0x80000000
#define KG_ERR_TYPE_DOUBLE 0x40000000
#define KG_ERR_ADDR_MASK 0x00000FFF
#define FM_PCD_KG_DOUBLE_ECC 0x80000000
#define FM_PCD_KG_KEYSIZE_OVERFLOW 0x40000000
#define KG_SCH_MODE_EN 0x80000000
/* shifts */
#define FM_PCD_KG_PE_CPP_MASK_SHIFT 16
#define FM_PCD_KG_KGAR_WSEL_SHIFT 8
/* others */
#define KG_DOUBLE_MEANING_REGS_OFFSET 0x100
#define NO_VALIDATION 0x70
#define KG_ACTION_REG_TO 1024
#define KG_MAX_PROFILE 255
#define SCHEME_ALWAYS_DIRECT 0xFFFFFFFF
typedef struct {
bool known;
uint8_t id;
} t_FmPcdKgSchemesExtractsEntry;
typedef struct {
t_FmPcdKgSchemesExtractsEntry extractsArray[FM_PCD_KG_MAX_NUM_OF_EXTRACTS_PER_KEY];
} t_FmPcdKgSchemesExtracts;
/***********************************************************************/
/* Policer defines */
/***********************************************************************/
/* masks */
#define FM_PCD_PLCR_PEMODE_PI 0x80000000
#define FM_PCD_PLCR_PEMODE_CBLND 0x40000000
#define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000
#define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000
#define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000
#define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000
#define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000
#define FM_PCD_PLCR_PEMODE_DEFC_R 0x08000000
#define FM_PCD_PLCR_PEMODE_DEFC_OVERRIDE 0x0C000000
#define FM_PCD_PLCR_PEMODE_OVCLR_MASK 0x03000000
#define FM_PCD_PLCR_PEMODE_OVCLR_Y 0x01000000
#define FM_PCD_PLCR_PEMODE_OVCLR_R 0x02000000
#define FM_PCD_PLCR_PEMODE_OVCLR_G_NC 0x03000000
#define FM_PCD_PLCR_PEMODE_PKT 0x00800000
#define FM_PCD_PLCR_PEMODE_FPP_MASK 0x001F0000
#define FM_PCD_PLCR_PEMODE_FPP_SHIFT 16
#define FM_PCD_PLCR_PEMODE_FLS_MASK 0x0000F000
#define FM_PCD_PLCR_PEMODE_FLS_L2 0x00003000
#define FM_PCD_PLCR_PEMODE_FLS_L3 0x0000B000
#define FM_PCD_PLCR_PEMODE_FLS_L4 0x0000E000
#define FM_PCD_PLCR_PEMODE_FLS_FULL 0x0000F000
#define FM_PCD_PLCR_PEMODE_RBFLS 0x00000800
#define FM_PCD_PLCR_PEMODE_TRA 0x00000004
#define FM_PCD_PLCR_PEMODE_TRB 0x00000002
#define FM_PCD_PLCR_PEMODE_TRC 0x00000001
#define FM_PCD_PLCR_DOUBLE_ECC 0x80000000
#define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000
#define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000
#define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000
#define FM_PCD_PLCR_NIA_VALID 0x80000000
#define FM_PCD_PLCR_GCR_EN 0x80000000
#define FM_PCD_PLCR_GCR_STEN 0x40000000
#define FM_PCD_PLCR_GCR_DAR 0x20000000
#define FM_PCD_PLCR_GCR_DEFNIA 0x00FFFFFF
#define FM_PCD_PLCR_NIA_ABS 0x00000100
#define FM_PCD_PLCR_GSR_BSY 0x80000000
#define FM_PCD_PLCR_GSR_DQS 0x60000000
#define FM_PCD_PLCR_GSR_RPB 0x20000000
#define FM_PCD_PLCR_GSR_FQS 0x0C000000
#define FM_PCD_PLCR_GSR_LPALG 0x0000C000
#define FM_PCD_PLCR_GSR_LPCA 0x00003000
#define FM_PCD_PLCR_GSR_LPNUM 0x000000FF
#define FM_PCD_PLCR_EVR_PSIC 0x80000000
#define FM_PCD_PLCR_EVR_AAC 0x40000000
#define FM_PCD_PLCR_PAR_PSI 0x20000000
#define FM_PCD_PLCR_PAR_PNUM 0x00FF0000
/* PWSEL Selctive select options */
#define FM_PCD_PLCR_PAR_PWSEL_PEMODE 0x00008000 /* 0 */
#define FM_PCD_PLCR_PAR_PWSEL_PEGNIA 0x00004000 /* 1 */
#define FM_PCD_PLCR_PAR_PWSEL_PEYNIA 0x00002000 /* 2 */
#define FM_PCD_PLCR_PAR_PWSEL_PERNIA 0x00001000 /* 3 */
#define FM_PCD_PLCR_PAR_PWSEL_PECIR 0x00000800 /* 4 */
#define FM_PCD_PLCR_PAR_PWSEL_PECBS 0x00000400 /* 5 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPIR_EIR 0x00000200 /* 6 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPBS_EBS 0x00000100 /* 7 */
#define FM_PCD_PLCR_PAR_PWSEL_PELTS 0x00000080 /* 8 */
#define FM_PCD_PLCR_PAR_PWSEL_PECTS 0x00000040 /* 9 */
#define FM_PCD_PLCR_PAR_PWSEL_PEPTS_ETS 0x00000020 /* 10 */
#define FM_PCD_PLCR_PAR_PWSEL_PEGPC 0x00000010 /* 11 */
#define FM_PCD_PLCR_PAR_PWSEL_PEYPC 0x00000008 /* 12 */
#define FM_PCD_PLCR_PAR_PWSEL_PERPC 0x00000004 /* 13 */
#define FM_PCD_PLCR_PAR_PWSEL_PERYPC 0x00000002 /* 14 */
#define FM_PCD_PLCR_PAR_PWSEL_PERRPC 0x00000001 /* 15 */
#define FM_PCD_PLCR_PAR_PMR_BRN_1TO1 0x0000 /* - Full bit replacement. {PBNUM[0:N-1]
1-> 2^N specific locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_2TO2 0x1 /* - {PBNUM[0:N-2],PNUM[N-1]}.
2-> 2^(N-1) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_4TO4 0x2 /* - {PBNUM[0:N-3],PNUM[N-2:N-1]}.
4-> 2^(N-2) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_8TO8 0x3 /* - {PBNUM[0:N-4],PNUM[N-3:N-1]}.
8->2^(N-3) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_16TO16 0x4 /* - {PBNUM[0:N-5],PNUM[N-4:N-1]}.
16-> 2^(N-4) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_32TO32 0x5 /* {PBNUM[0:N-6],PNUM[N-5:N-1]}.
32-> 2^(N-5) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_64TO64 0x6 /* {PBNUM[0:N-7],PNUM[N-6:N-1]}.
64-> 2^(N-6) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_128TO128 0x7 /* {PBNUM[0:N-8],PNUM[N-7:N-1]}.
128-> 2^(N-7) base locations. */
#define FM_PCD_PLCR_PAR_PMR_BRN_256TO256 0x8 /* - No bit replacement for N=8. {PNUM[N-8:N-1]}.
When N=8 this option maps all 256 profiles by the DISPATCH bus into one group. */
#define FM_PCD_PLCR_PMR_V 0x80000000
#define PLCR_ERR_ECC_CAP 0x80000000
#define PLCR_ERR_ECC_TYPE_DOUBLE 0x40000000
#define PLCR_ERR_ECC_PNUM_MASK 0x00000FF0
#define PLCR_ERR_ECC_OFFSET_MASK 0x0000000F
#define PLCR_ERR_UNINIT_CAP 0x80000000
#define PLCR_ERR_UNINIT_NUM_MASK 0x000000FF
#define PLCR_ERR_UNINIT_PID_MASK 0x003f0000
#define PLCR_ERR_UNINIT_ABSOLUTE_MASK 0x00008000
/* shifts */
#define PLCR_ERR_ECC_PNUM_SHIFT 4
#define PLCR_ERR_UNINIT_PID_SHIFT 16
#define FM_PCD_PLCR_PMR_BRN_SHIFT 16
/* others */
#define WAIT_FOR_PLCR_EVR_AAC \
{\
uint32_t count = 0; \
uint32_t tmpReg32; \
while (count < FM_PCD_PLCR_POLL) \
{ \
tmpReg32 = GET_UINT32(p_FmPcdPlcrRegs->fmpl_evr);\
if (!( tmpReg32 & FM_PCD_PLCR_EVR_AAC)) break;\
count++;\
}\
}
#define WAIT_FOR_PLCR_PAR_GO \
{\
uint32_t count = 0; \
uint32_t tmpReg32; \
while (count < FM_PCD_PLCR_POLL) \
{ \
tmpReg32 = GET_UINT32(p_FmPcdPlcrRegs->fmpl_par);\
if (!( tmpReg32 & FM_PCD_PLCR_PAR_GO)) break;\
count++; \
}\
}
#define PLCR_PORT_WINDOW_SIZE(hardwarePortId)
/****************************/
/* Defaults */
/****************************/
#define DEFAULT_plcrAutoRefresh FALSE
#define DEFAULT_prsMaxParseCycleLimit 0
#define DEFAULT_fmPcdKgErrorExceptions (FM_PCD_EX_KG_DOUBLE_ECC | FM_PCD_EX_KG_KEYSIZE_OVERFLOW)
#define DEFAULT_fmPcdPlcrErrorExceptions (FM_PCD_EX_PLCR_DOUBLE_ECC | FM_PCD_EX_PLCR_INIT_ENTRY_ERROR)
#define DEFAULT_fmPcdPlcrExceptions 0
#define DEFAULT_fmPcdPrsErrorExceptions (FM_PCD_EX_PRS_DOUBLE_ECC)
#define DEFAULT_fmPcdPrsExceptions FM_PCD_EX_PRS_SINGLE_ECC
#define DEFAULT_numOfUsedProfilesPerWindow 16
#define DEFAULT_numOfSharedPlcrProfiles 4
/***********************************************************************/
/* Memory map */
/***********************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct {
volatile uint32_t kgoe_sp;
volatile uint32_t kgoe_cpp;
} _PackedType t_FmPcdKgPortConfigRegs;
typedef _Packed struct {
volatile uint32_t kgcpe[8];
} _PackedType t_FmPcdKgClsPlanRegs;
typedef _Packed union {
t_FmPcdKgInterModuleSchemeRegs schemeRegs;
t_FmPcdKgPortConfigRegs portRegs;
t_FmPcdKgClsPlanRegs clsPlanRegs;
} _PackedType u_FmPcdKgIndirectAccessRegs;
typedef _Packed struct {
volatile uint32_t kggcr;
volatile uint32_t res0;
volatile uint32_t res1;
volatile uint32_t kgeer;
volatile uint32_t kgeeer;
volatile uint32_t res2;
volatile uint32_t res3;
volatile uint32_t kgseer;
volatile uint32_t kgseeer;
volatile uint32_t kggsr;
volatile uint32_t kgtpc;
volatile uint32_t kgserc;
volatile uint32_t res4[4];
volatile uint32_t kgfdor;
volatile uint32_t kggdv0r;
volatile uint32_t kggdv1r;
volatile uint32_t res5[5];
volatile uint32_t kgfer;
volatile uint32_t kgfeer;
volatile uint32_t res6[38];
u_FmPcdKgIndirectAccessRegs indirectAccessRegs;
volatile uint32_t res[42]; /*(0xfc-sizeof(u_FmPcdKgIndirectAccessRegs))/4 */
volatile uint32_t kgar;
} _PackedType t_FmPcdKgRegs;
typedef _Packed struct {
/* General Configuration and Status Registers */
volatile uint32_t fmpl_gcr; /* 0x000 FMPL_GCR - FM Policer General Configuration */
volatile uint32_t fmpl_gsr; /* 0x004 FMPL_GSR - FM Policer Global Status Register */
volatile uint32_t fmpl_evr; /* 0x008 FMPL_EVR - FM Policer Event Register */
volatile uint32_t fmpl_ier; /* 0x00C FMPL_IER - FM Policer Interrupt Enable Register */
volatile uint32_t fmpl_ifr; /* 0x010 FMPL_IFR - FM Policer Interrupt Force Register */
volatile uint32_t fmpl_eevr; /* 0x014 FMPL_EEVR - FM Policer Error Event Register */
volatile uint32_t fmpl_eier; /* 0x018 FMPL_EIER - FM Policer Error Interrupt Enable Register */
volatile uint32_t fmpl_eifr; /* 0x01C FMPL_EIFR - FM Policer Error Interrupt Force Register */
/* Global Statistic Counters */
volatile uint32_t fmpl_rpcnt; /* 0x020 FMPL_RPC - FM Policer RED Packets Counter */
volatile uint32_t fmpl_ypcnt; /* 0x024 FMPL_YPC - FM Policer YELLOW Packets Counter */
volatile uint32_t fmpl_rrpcnt; /* 0x028 FMPL_RRPC - FM Policer Recolored RED Packet Counter */
volatile uint32_t fmpl_rypcnt; /* 0x02C FMPL_RYPC - FM Policer Recolored YELLOW Packet Counter */
volatile uint32_t fmpl_tpcnt; /* 0x030 FMPL_TPC - FM Policer Total Packet Counter */
volatile uint32_t fmpl_flmcnt; /* 0x034 FMPL_FLMC - FM Policer Frame Length Mismatch Counter */
volatile uint32_t fmpl_res0[21]; /* 0x038 - 0x08B Reserved */
/* Profile RAM Access Registers */
volatile uint32_t fmpl_par; /* 0x08C FMPL_PAR - FM Policer Profile Action Register*/
t_FmPcdPlcrInterModuleProfileRegs profileRegs;
/* Error Capture Registers */
volatile uint32_t fmpl_serc; /* 0x100 FMPL_SERC - FM Policer Soft Error Capture */
volatile uint32_t fmpl_upcr; /* 0x104 FMPL_UPCR - FM Policer Uninitialized Profile Capture Register */
volatile uint32_t fmpl_res2; /* 0x108 Reserved */
/* Debug Registers */
volatile uint32_t fmpl_res3[61]; /* 0x10C-0x200 Reserved Debug*/
/* Profile Selection Mapping Registers Per Port-ID (n=1-11, 16) */
volatile uint32_t fmpl_dpmr; /* 0x200 FMPL_DPMR - FM Policer Default Mapping Register */
volatile uint32_t fmpl_pmr[63]; /*+default 0x204-0x2FF FMPL_PMR1 - FMPL_PMR63, - FM Policer Profile Mapping Registers.
(for port-ID 1-11, only for supported Port-ID registers) */
} _PackedType t_FmPcdPlcrRegs;
typedef _Packed struct {
volatile uint32_t rpclim;
volatile uint32_t rpimac;
volatile uint32_t pmeec;
volatile uint32_t res1[5];
volatile uint32_t pevr;
volatile uint32_t pever;
volatile uint32_t pevfr;
volatile uint32_t perr;
volatile uint32_t perer;
volatile uint32_t perfr;
volatile uint32_t res2[0xA];
volatile uint32_t ppsc;
volatile uint32_t res3;
volatile uint32_t pds;
volatile uint32_t l2rrs;
volatile uint32_t l3rrs;
volatile uint32_t l4rrs;
volatile uint32_t srrs;
volatile uint32_t l2rres;
volatile uint32_t l3rres;
volatile uint32_t l4rres;
volatile uint32_t srres;
volatile uint32_t spcs;
volatile uint32_t spscs;
volatile uint32_t hxscs;
volatile uint32_t mrcs;
volatile uint32_t mwcs;
volatile uint32_t mrscs;
volatile uint32_t mwscs;
volatile uint32_t fcscs;
} _PackedType t_FmPcdPrsRegs;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/***********************************************************************/
/* Driver's internal structures */
/***********************************************************************/
typedef struct {
t_Handle h_Manip;
bool keepRes;
e_FmPcdEngine nextEngine;
uint8_t parseCode;
} t_FmPcdInfoForManip;
/**************************************************************************//**
@Description A structure of parameters to communicate
between the port and PCD regarding the KG scheme.
*//***************************************************************************/
typedef struct {
uint8_t netEnvId; /* in */
uint8_t numOfDistinctionUnits; /* in */
uint8_t unitIds[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS]; /* in */
uint32_t vector; /* out */
} t_NetEnvParams;
typedef struct {
volatile bool lock;
bool used;
uint8_t owners;
uint8_t netEnvId;
uint8_t guestId;
uint8_t baseEntry;
uint16_t sizeOfGrp;
protocolOpt_t optArray[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)];
} t_FmPcdKgClsPlanGrp;
typedef struct {
volatile bool lock;
bool valid;
uint8_t netEnvId;
uint8_t owners;
uint32_t matchVector;
uint32_t ccUnits;
bool nextRelativePlcrProfile;
uint16_t relativeProfileId;
uint16_t numOfProfiles;
t_FmPcdKgKeyOrder orderedArray;
e_FmPcdEngine nextEngine;
e_FmPcdDoneAction doneAction;
uint8_t pointedOwners;
uint32_t requiredAction;
bool extractedOrs;
uint8_t bitOffsetInPlcrProfile;
bool directPlcr;
} t_FmPcdKgScheme;
typedef struct {
bool allocated;
uint8_t ownerId; /* guestId for KG in multi-partition only,
portId for PLCR in any environment */
} t_FmPcdAllocMng;
typedef struct {
t_FmPcdKgRegs *p_FmPcdKgRegs;
uint32_t schemeExceptionsBitMask;
uint8_t numOfSchemes;
uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES];
t_FmPcdKgScheme schemes[FM_PCD_KG_NUM_OF_SCHEMES];
t_FmPcdKgClsPlanGrp clsPlanGrps[FM_MAX_NUM_OF_PORTS];
uint8_t emptyClsPlanGrpId;
t_FmPcdAllocMng schemesMng[FM_PCD_KG_NUM_OF_SCHEMES]; /* only for MASTER ! */
t_FmPcdAllocMng clsPlanBlocksMng[FM_PCD_MAX_NUM_OF_CLS_PLANS/CLS_PLAN_NUM_PER_GRP];
} t_FmPcdKg;
typedef struct {
uint16_t profilesBase;
uint16_t numOfProfiles;
t_Handle h_FmPort;
} t_FmPcdPlcrMapParam;
typedef struct {
bool valid;
volatile bool lock;
t_FmPcdAllocMng profilesMng;
uint8_t pointedOwners;
uint32_t requiredAction;
e_FmPcdEngine nextEngineOnGreen; /**< Green next engine type */
u_FmPcdPlcrNextEngineParams paramsOnGreen; /**< Green next engine params */
e_FmPcdEngine nextEngineOnYellow; /**< Yellow next engine type */
u_FmPcdPlcrNextEngineParams paramsOnYellow; /**< Yellow next engine params */
e_FmPcdEngine nextEngineOnRed; /**< Red next engine type */
u_FmPcdPlcrNextEngineParams paramsOnRed; /**< Red next engine params */
} t_FmPcdPlcrProfile;
typedef struct {
t_FmPcdPlcrRegs *p_FmPcdPlcrRegs;
t_FmPcdPlcrProfile profiles[FM_PCD_PLCR_NUM_ENTRIES];
uint16_t numOfSharedProfiles;
uint16_t sharedProfilesIds[FM_PCD_PLCR_NUM_ENTRIES];
t_FmPcdPlcrMapParam portsMapping[FM_MAX_NUM_OF_PORTS];
} t_FmPcdPlcr;
typedef struct {
uint32_t *p_SwPrsCode;
uint32_t *p_CurrSwPrs;
uint8_t currLabel;
t_FmPcdPrsRegs *p_FmPcdPrsRegs;
t_FmPcdPrsLabelParams labelsTable[FM_PCD_PRS_NUM_OF_LABELS];
uint32_t fmPcdPrsPortIdStatistics;
} t_FmPcdPrs;
typedef struct {
struct {
e_NetHeaderType hdr;
protocolOpt_t opt; /* only one option !! */
} hdrs[FM_PCD_MAX_NUM_OF_INTERCHANGEABLE_HDRS];
} t_FmPcdIntDistinctionUnit;
typedef struct {
e_NetHeaderType hdr;
e_NetHeaderType aliasHdr;
} t_FmPcdNetEnvAliases;
typedef struct {
volatile bool lock;
bool used;
uint8_t owners;
uint8_t clsPlanGrpId;
t_FmPcdIntDistinctionUnit units[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS];
uint32_t unitsVectors[FM_PCD_MAX_NUM_OF_DISTINCTION_UNITS];
uint32_t lcvs[FM_PCD_PRS_NUM_OF_HDRS];
uint32_t macsecVector;
t_FmPcdNetEnvAliases aliasHdrs[FM_PCD_MAX_NUM_OF_PRIVATE_HDRS];
} t_FmPcdNetEnv;
typedef struct {
bool plcrAutoRefresh;
uint16_t prsMaxParseCycleLimit;
} t_FmPcdDriverParam;
typedef struct {
t_Handle h_Fm;
t_Handle h_FmMuram;
uint64_t physicalMuramBase;
volatile bool lock;
t_Handle h_Spinlock;
t_Handle h_IpcSession; /* relevant for guest only */
bool enabled;
uint8_t guestId; /**< Guest Partition Id */
uint8_t numOfEnabledGuestPartitionsPcds;
char fmPcdModuleName[MODULE_NAME_SIZE];
char fmPcdIpcHandlerModuleName[MODULE_NAME_SIZE]; /* relevant for guest only - this is the master's name */
t_FmPcdNetEnv netEnvs[FM_MAX_NUM_OF_PORTS];
t_FmPcdKg *p_FmPcdKg;
t_FmPcdPlcr *p_FmPcdPlcr;
t_FmPcdPrs *p_FmPcdPrs;
t_Handle h_Hc;
uint32_t exceptions;
t_FmPcdExceptionCallback *f_Exception;
t_FmPcdIdExceptionCallback *f_FmPcdIndexedException;
t_Handle h_App;
t_FmPcdDriverParam *p_FmPcdDriverParam;
} t_FmPcd;
/***********************************************************************/
/* PCD internal routines */
/***********************************************************************/
/**************************************************************************//**
@Group FM_PCD_InterModule_grp FM PCD Inter-Module Unit
@Description FM PCD Inter Module functions -
These are not User API routines but routines that may be called
from other modules. This will be the case in a single core environment,
where instead of useing the XX messeging mechanism, the routines may be
called from other modules. In a multicore environment, the other modules may
be run by other cores and therefor these routines may not be called directly.
@{
*//***************************************************************************/
t_Error PcdGetVectorForOpt(t_FmPcd *p_FmPcd, uint8_t netEnvId, protocolOpt_t opt, uint32_t *p_Vector);
t_Error PcdGetUnitsVector(t_FmPcd *p_FmPcd, t_NetEnvParams *p_Params);
bool PcdNetEnvIsUnitWithoutOpts(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint32_t unitVector);
t_Error PcdGetClsPlanGrpParams(t_FmPcd *p_FmPcd, t_FmPcdKgInterModuleClsPlanGrpParams *p_GrpParams);
void FmPcdSetClsPlanGrpId(t_FmPcd *p_FmPcd, uint8_t netEnvId, uint8_t clsPlanGrpId);
e_NetHeaderType FmPcdGetAliasHdr(t_FmPcd *p_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr);
uint8_t FmPcdNetEnvGetUnitIdForSingleHdr(t_Handle h_FmPcd, uint8_t netEnvId, e_NetHeaderType hdr);
t_Handle KgConfig( t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams);
t_Error KgInit(t_FmPcd *p_FmPcd);
t_Error KgFree(t_FmPcd *p_FmPcd);
void KgSetClsPlan(t_Handle h_FmPcd, t_FmPcdKgInterModuleClsPlanSet *p_Set);
bool KgIsSchemeAlwaysDirect(t_Handle h_FmPcd, uint8_t schemeId);
void KgEnable(t_FmPcd *p_FmPcd);
void KgDisable(t_FmPcd *p_FmPcd);
t_Error KgAllocClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t *p_First);
void KgFreeClsPlanEntries(t_Handle h_FmPcd, uint16_t numOfClsPlanEntries, uint8_t guestId, uint8_t base);
/* only for MULTI partittion */
t_Error FmPcdKgAllocSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds);
t_Error FmPcdKgFreeSchemes(t_Handle h_FmPcd, uint8_t numOfSchemes, uint8_t guestId, uint8_t *p_SchemesIds);
/* only for SINGLE partittion */
t_Error KgBindPortToSchemes(t_Handle h_FmPcd , uint8_t hardwarePortId, uint32_t spReg);
t_Handle PlcrConfig(t_FmPcd *p_FmPcd, t_FmPcdParams *p_FmPcdParams);
t_Error PlcrInit(t_FmPcd *p_FmPcd);
t_Error PlcrFree(t_FmPcd *p_FmPcd);
void PlcrEnable(t_FmPcd *p_FmPcd);
void PlcrDisable(t_FmPcd *p_FmPcd);
t_Error PlcrFreeProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, uint16_t num, uint16_t base);
t_Error PlcrAllocProfiles(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, uint16_t numOfProfiles, uint16_t *p_Base);
t_Error PlcrAllocSharedProfiles(t_FmPcd *p_FmPcd, uint16_t numOfProfiles, uint16_t *profilesIds);
void PlcrFreeSharedProfiles(t_FmPcd *p_FmPcd, uint16_t numOfProfiles, uint16_t *profilesIds);
t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams);
t_Error PrsInit(t_FmPcd *p_FmPcd);
void PrsEnable(t_FmPcd *p_FmPcd);
void PrsDisable(t_FmPcd *p_FmPcd);
void PrsFree(t_FmPcd *p_FmPcd );
t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include);
t_Handle FmPcdCcConfig(t_Handle h_FmPcd, t_FmPcdParams *p_FmPcdParams);
t_Error FmPcdCcGetGrpParams(t_Handle treeId, uint8_t grpId, uint32_t *p_GrpBits, uint8_t *p_GrpBase);
uint8_t FmPcdCcGetOffset(t_Handle h_CcNode);
uint8_t FmPcdCcGetParseCode(t_Handle h_CcNode);
uint16_t FmPcdCcGetNumOfKeys(t_Handle h_CcNode);
void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add);
t_Error FmPcdManipCheckParamsForCcNextEgine(t_FmPcdCcNextEngineParams *p_InfoForManip, uint32_t *requiredAction);
void FmPcdManipUpdateAdResultForCc(t_Handle h_Manip, t_Handle p_Ad, t_Handle *p_AdNew);
void FmPcdManipUpdateAdContLookupForCc(t_Handle h_Manip, t_Handle p_Ad, t_Handle *p_AdNew, uint32_t adTableOffset);
uint32_t FmPcdManipCheckNia(t_Handle h_FmPcd, t_Handle h_Ad);
void FmPcdManipUpdateOwner(t_Handle h_Manip, bool add);
t_Error FmPcdManipCheckParamsWithCcNodeParams(t_Handle h_Manip, t_Handle h_FmPcdCcNode);
static __inline__ t_Handle FmPcdGetMuramHandle(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
ASSERT_COND(p_FmPcd);
return p_FmPcd->h_FmMuram;
}
static __inline__ uint64_t FmPcdGetMuramPhysBase(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
ASSERT_COND(p_FmPcd);
return p_FmPcd->physicalMuramBase;
}
#endif /* __FM_PCD_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_pcd_ipc.h
@Description FM PCD Inter-Partition prototypes, structures and definitions.
*//***************************************************************************/
#ifndef __FM_PCD_IPC_H
#define __FM_PCD_IPC_H
#include "std_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/**************************************************************************//**
@Description Structure for getting a sw parser address according to a label
Fields commented 'IN' are passed by the port module to be used
by the FM module.
Fields commented 'OUT' will be filled by FM before returning to port.
*//***************************************************************************/
typedef _Packed struct t_FmPcdIpcSwPrsLable
{
uint32_t enumHdr; /**< IN. The existance of this header will envoke
the sw parser code. */
uint8_t indexPerHdr; /**< IN. Normally 0, if more than one sw parser
attachments for the same header, use this
index to distinguish between them. */
} _PackedType t_FmPcdIpcSwPrsLable;
/**************************************************************************//**
@Description Structure for port-PCD communication.
Fields commented 'IN' are passed by the port module to be used
by the FM module.
Fields commented 'OUT' will be filled by FM before returning to port.
Some fields are optional (depending on configuration) and
will be analized by the port and FM modules accordingly.
*//***************************************************************************/
typedef struct t_FmPcdIpcKgSchemesParams
{
uint8_t guestId; /**< IN */
uint8_t numOfSchemes; /**< IN */
uint8_t schemesIds[FM_PCD_KG_NUM_OF_SCHEMES]; /**< OUT */
} _PackedType t_FmPcdIpcKgSchemesParams;
typedef struct t_FmPcdIpcKgClsPlanParams
{
uint8_t guestId; /**< IN */
uint16_t numOfClsPlanEntries; /**< IN */
uint8_t clsPlanBase; /**< IN in alloc only */
} _PackedType t_FmPcdIpcKgClsPlanParams;
typedef _Packed struct t_FmPcdIpcPlcrAllocParams
{
uint16_t num;
uint8_t hardwarePortId;
uint16_t plcrProfilesBase;
} _PackedType t_FmPcdIpcPlcrAllocParams;
typedef _Packed struct t_FmPcdIpcSharedPlcrAllocParams
{
uint16_t num; /**< IN */
//uint16_t profilesIds[FM_PCD_PLCR_NUM_ENTRIES]; /**< OUT */
uint32_t sharedProfilesMask[8];
} _PackedType t_FmPcdIpcSharedPlcrAllocParams;
typedef _Packed struct t_FmPcdIpcPrsIncludePort
{
uint8_t hardwarePortId; /* IN */
bool include; /* IN */
} _PackedType t_FmPcdIpcPrsIncludePort;
#define FM_PCD_MAX_REPLY_SIZE 16
#define FM_PCD_MAX_MSG_SIZE 36
#define FM_PCD_MAX_REPLY_BODY_SIZE 36
typedef _Packed struct
{
uint32_t msgId;
uint8_t msgBody[FM_PCD_MAX_MSG_SIZE];
} _PackedType t_FmPcdIpcMsg;
typedef _Packed struct t_FmPcdIpcReply
{
uint32_t error;
uint8_t replyBody[FM_PCD_MAX_REPLY_BODY_SIZE];
} _PackedType t_FmPcdIpcReply;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Function FM_PCD_ALLOC_KG_SCHEMES
@Description Used by FM PCD front-end in order to allocate KG resources
@Param[in/out] t_FmPcdIpcKgAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_KG_SCHEMES 3
/**************************************************************************//**
@Function FM_PCD_FREE_KG_SCHEMES
@Description Used by FM PCD front-end in order to Free KG resources
@Param[in/out] t_FmPcdIpcKgSchemesParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_KG_SCHEMES 4
/**************************************************************************//**
@Function FM_PCD_ALLOC_PROFILES
@Description Used by FM PCD front-end in order to allocate Policer profiles
@Param[in/out] t_FmPcdIpcKgSchemesParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_PROFILES 5
/**************************************************************************//**
@Function FM_PCD_FREE_PROFILES
@Description Used by FM PCD front-end in order to Free Policer profiles
@Param[in/out] t_FmPcdIpcPlcrAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_PROFILES 6
/**************************************************************************//**
@Function FM_PCD_GET_PHYS_MURAM_BASE
@Description Used by FM PCD front-end in order to get MURAM base address
@Param[in/out] t_FmPcdIcPhysAddr Pointer
*//***************************************************************************/
#define FM_PCD_GET_PHYS_MURAM_BASE 7
/**************************************************************************//**
@Function FM_PCD_GET_SW_PRS_OFFSET
@Description Used by FM front-end to get the SW parser offset of the start of
code relevant to a given label.
@Param[in/out] t_FmPcdIpcSwPrsLable Pointer
*//***************************************************************************/
#define FM_PCD_GET_SW_PRS_OFFSET 8
/**************************************************************************//**
@Function FM_PCD_ALLOC_SHARED_PROFILES
@Description Used by FM PCD front-end in order to allocate shared profiles
@Param[in/out] t_FmPcdIpcSharedPlcrAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_SHARED_PROFILES 9
/**************************************************************************//**
@Function FM_PCD_FREE_SHARED_PROFILES
@Description Used by FM PCD front-end in order to free shared profiles
@Param[in/out] t_FmPcdIpcSharedPlcrAllocParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_SHARED_PROFILES 10
/**************************************************************************//**
@Function FM_PCD_MASTER_IS_ENABLED
@Description Used by FM front-end in order to verify
PCD enablement.
@Param[in] bool Pointer
*//***************************************************************************/
#define FM_PCD_MASTER_IS_ENABLED 15
/**************************************************************************//**
@Function FM_PCD_GUEST_DISABLE
@Description Used by FM front-end to inform back-end when
front-end PCD is disabled
@Param[in] None
*//***************************************************************************/
#define FM_PCD_GUEST_DISABLE 16
/**************************************************************************//**
@Function FM_PCD_DUMP_REGS
@Description Used by FM front-end to dump all PCD registers
@Param[in] None
*//***************************************************************************/
#define FM_PCD_DUMP_REGS 17
/**************************************************************************//**
@Function FM_PCD_KG_DUMP_REGS
@Description Used by FM front-end to dump KG registers
@Param[in] None
*//***************************************************************************/
#define FM_PCD_KG_DUMP_REGS 18
/**************************************************************************//**
@Function FM_PCD_PLCR_DUMP_REGS
@Description Used by FM front-end to dump PLCR registers
@Param[in] None
*//***************************************************************************/
#define FM_PCD_PLCR_DUMP_REGS 19
/**************************************************************************//**
@Function FM_PCD_PLCR_PROFILE_DUMP_REGS
@Description Used by FM front-end to dump PLCR specified profile registers
@Param[in] t_Handle Pointer
*//***************************************************************************/
#define FM_PCD_PLCR_PROFILE_DUMP_REGS 20
/**************************************************************************//**
@Function FM_PCD_PRS_DUMP_REGS
@Description Used by FM front-end to dump PRS registers
@Param[in] None
*//***************************************************************************/
#define FM_PCD_PRS_DUMP_REGS 21
/**************************************************************************//**
@Function FM_PCD_FREE_KG_CLSPLAN
@Description Used by FM PCD front-end in order to Free KG classification plan entries
@Param[in/out] t_FmPcdIpcKgClsPlanParams Pointer
*//***************************************************************************/
#define FM_PCD_FREE_KG_CLSPLAN 22
/**************************************************************************//**
@Function FM_PCD_ALLOC_KG_CLSPLAN
@Description Used by FM PCD front-end in order to allocate KG classification plan entries
@Param[in/out] t_FmPcdIpcKgClsPlanParams Pointer
*//***************************************************************************/
#define FM_PCD_ALLOC_KG_CLSPLAN 23
/**************************************************************************//**
@Function FM_PCD_MASTER_IS_ALIVE
@Description Used by FM front-end to check that back-end exists
@Param[in] None
*//***************************************************************************/
#define FM_PCD_MASTER_IS_ALIVE 24
/**************************************************************************//**
@Function FM_PCD_GET_COUNTER
@Description Used by FM front-end to read PCD counters
@Param[in/out] t_FmPcdIpcGetCounter Pointer
*//***************************************************************************/
#define FM_PCD_GET_COUNTER 25
/**************************************************************************//**
@Function FM_PCD_PRS_INC_PORT_STATS
@Description Used by FM front-end to set/clear statistics for port
@Param[in/out] t_FmPcdIpcPrsIncludePort Pointer
*//***************************************************************************/
#define FM_PCD_PRS_INC_PORT_STATS 26
/** @} */ /* end of FM_PCD_IPC_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_PCD_IPC_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_pcd.c
@Description FM PCD ...
*//***************************************************************************/
#include "std_ext.h"
#include "error_ext.h"
#include "string_ext.h"
#include "debug_ext.h"
#include "net_ext.h"
#include "fm_common.h"
#include "fm_pcd.h"
#include "fm_pcd_ipc.h"
t_Handle PrsConfig(t_FmPcd *p_FmPcd,t_FmPcdParams *p_FmPcdParams)
{
t_FmPcdPrs *p_FmPcdPrs;
uintptr_t baseAddr;
UNUSED(p_FmPcd);
UNUSED(p_FmPcdParams);
p_FmPcdPrs = (t_FmPcdPrs *) XX_Malloc(sizeof(t_FmPcdPrs));
if (!p_FmPcdPrs)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM Parser structure allocation FAILED"));
return NULL;
}
memset(p_FmPcdPrs, 0, sizeof(t_FmPcdPrs));
if (p_FmPcd->guestId == NCSW_MASTER_ID)
{
baseAddr = FmGetPcdPrsBaseAddr(p_FmPcdParams->h_Fm);
p_FmPcdPrs->p_SwPrsCode = (uint32_t *)UINT_TO_PTR(baseAddr);
p_FmPcdPrs->p_FmPcdPrsRegs = (t_FmPcdPrsRegs *)UINT_TO_PTR(baseAddr + PRS_REGS_OFFSET);
}
p_FmPcdPrs->fmPcdPrsPortIdStatistics = 0;
p_FmPcd->p_FmPcdDriverParam->prsMaxParseCycleLimit = DEFAULT_prsMaxParseCycleLimit;
p_FmPcd->exceptions |= (DEFAULT_fmPcdPrsErrorExceptions | DEFAULT_fmPcdPrsExceptions);
return p_FmPcdPrs;
}
static void PcdPrsErrorException(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
uint32_t event, mask, force;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
event = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perr);
mask = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perer);
event &= mask;
/* clear the forced events */
force = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perfr);
if(force & event)
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perfr, force & ~event);
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->perr, event);
DBG(TRACE, ("parser error - 0x%08x\n",event));
if(event & FM_PCD_PRS_DOUBLE_ECC)
p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_DOUBLE_ECC);
}
static void PcdPrsException(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
uint32_t event, force;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
event = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pevr);
event &= GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pever);
ASSERT_COND(event & FM_PCD_PRS_SINGLE_ECC);
DBG(TRACE, ("parser event - 0x%08x\n",event));
/* clear the forced events */
force = GET_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pevfr);
if(force & event)
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pevfr, force & ~event);
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->pevr, event);
p_FmPcd->f_Exception(p_FmPcd->h_App,e_FM_PCD_PRS_EXCEPTION_SINGLE_ECC);
}
static uint32_t GetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t indexPerHdr)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
int i;
t_FmPcdPrsLabelParams *p_Label;
SANITY_CHECK_RETURN_VALUE(p_FmPcd, E_INVALID_HANDLE, 0);
SANITY_CHECK_RETURN_VALUE(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE, 0);
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
ASSERT_COND(p_FmPcd->p_FmPcdPrs->currLabel < FM_PCD_PRS_NUM_OF_LABELS);
for (i=0; i < p_FmPcd->p_FmPcdPrs->currLabel; i++)
{
p_Label = &p_FmPcd->p_FmPcdPrs->labelsTable[i];
if ((hdr == p_Label->hdr) && (indexPerHdr == p_Label->indexPerHdr))
return p_Label->instructionOffset;
}
REPORT_ERROR(MAJOR, E_NOT_FOUND, ("Sw Parser attachment Not found"));
return (uint32_t)ILLEGAL_BASE;
}
t_Error PrsInit(t_FmPcd *p_FmPcd)
{
t_FmPcdDriverParam *p_Param = p_FmPcd->p_FmPcdDriverParam;
t_FmPcdPrsRegs *p_Regs = p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
uint32_t tmpReg;
if(p_FmPcd->guestId != NCSW_MASTER_ID)
return E_OK;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
#ifdef FM_PRS_MEM_ERRATA_FMAN_SW003
{
uint32_t i;
uint32_t regsToGlobalOffset = 0x840;
uint32_t firstPortToGlobalOffset = 0x45800;
uint64_t globalAddr = PTR_TO_UINT(p_Regs) - regsToGlobalOffset;
uint32_t firstPortAddr = (uint32_t)(globalAddr - (uint64_t)firstPortToGlobalOffset);
uint32_t portSize = 0x1000;
t_FmRevisionInfo revInfo;
FM_GetRevision(p_FmPcd->h_Fm, &revInfo);
if ((revInfo.majorRev == 1) && (revInfo.minorRev == 0))
{
/* clear all parser memory */
IOMemSet32(UINT_TO_PTR(globalAddr), 0x00000000, 0x800);
for(i = 0;i<16;i++)
IOMemSet32(UINT_TO_PTR(firstPortAddr+i*portSize), (uint8_t)0x00000000, (uint32_t)0x80);
}
}
#endif /* FM_PRS_MEM_ERRATA_FMAN_SW003 */
/**********************RPCLIM******************/
WRITE_UINT32(p_Regs->rpclim, (uint32_t)p_Param->prsMaxParseCycleLimit);
/**********************FMPL_RPCLIM******************/
/* register even if no interrupts enabled, to allow future enablement */
FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR, PcdPrsErrorException, p_FmPcd);
/* register even if no interrupts enabled, to allow future enablement */
FmRegisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL, PcdPrsException, p_FmPcd);
/**********************PEVR******************/
WRITE_UINT32(p_Regs->pevr, (FM_PCD_PRS_SINGLE_ECC | FM_PCD_PRS_PORT_IDLE_STS) );
/**********************PEVR******************/
/**********************PEVER******************/
if(p_FmPcd->exceptions & FM_PCD_EX_PRS_SINGLE_ECC)
{
FmEnableRamsEcc(p_FmPcd->h_Fm);
WRITE_UINT32(p_Regs->pever, FM_PCD_PRS_SINGLE_ECC);
}
else
WRITE_UINT32(p_Regs->pever, 0);
/**********************PEVER******************/
/**********************PERR******************/
WRITE_UINT32(p_Regs->perr, FM_PCD_PRS_DOUBLE_ECC);
/**********************PERR******************/
/**********************PERER******************/
tmpReg = 0;
if(p_FmPcd->exceptions & FM_PCD_EX_PRS_DOUBLE_ECC)
{
FmEnableRamsEcc(p_FmPcd->h_Fm);
tmpReg |= FM_PCD_PRS_DOUBLE_ECC;
}
WRITE_UINT32(p_Regs->perer, tmpReg);
/**********************PERER******************/
/**********************PPCS******************/
WRITE_UINT32(p_Regs->ppsc, p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics);
/**********************PPCS******************/
#ifdef FM_PRS_L4_SHELL_ERRATA_FMANb
{
uint32_t i, j;
t_FmRevisionInfo revInfo;
uint8_t swPrsL4Patch[] = SW_PRS_L4_PATCH;
FM_GetRevision(p_FmPcd->h_Fm, &revInfo);
if ((revInfo.majorRev == 1) && (revInfo.minorRev == 0))
{
/* load sw parser L4 patch */
for(i=0;i<sizeof(swPrsL4Patch)/4;i++)
{
tmpReg = 0;
for(j =0;j<4;j++)
{
tmpReg <<= 8;
tmpReg |= swPrsL4Patch[i*4+j];
}
WRITE_UINT32(*(p_FmPcd->p_FmPcdPrs->p_SwPrsCode+ FM_PCD_PRS_SW_OFFSET/4 + i), tmpReg);
}
p_FmPcd->p_FmPcdPrs->p_CurrSwPrs = FM_PCD_PRS_SW_OFFSET/4 + p_FmPcd->p_FmPcdPrs->p_SwPrsCode+sizeof(swPrsL4Patch)/4;
}
}
#endif /* FM_PRS_L4_SHELL_ERRATA_FMANb */
return E_OK;
}
void PrsFree(t_FmPcd *p_FmPcd )
{
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_ERR);
/* register even if no interrupts enabled, to allow future enablement */
FmUnregisterIntr(p_FmPcd->h_Fm, e_FM_MOD_PRS, 0, e_FM_INTR_TYPE_NORMAL);
}
void PrsEnable(t_FmPcd *p_FmPcd )
{
t_FmPcdPrsRegs *p_Regs = p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
WRITE_UINT32(p_Regs->rpimac, GET_UINT32(p_Regs->rpimac) | FM_PCD_PRS_RPIMAC_EN);
}
void PrsDisable(t_FmPcd *p_FmPcd )
{
t_FmPcdPrsRegs *p_Regs = p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs;
ASSERT_COND(p_FmPcd->guestId == NCSW_MASTER_ID);
WRITE_UINT32(p_Regs->rpimac, GET_UINT32(p_Regs->rpimac) & ~FM_PCD_PRS_RPIMAC_EN);
}
t_Error PrsIncludePortInStatistics(t_FmPcd *p_FmPcd, uint8_t hardwarePortId, bool include)
{
uint32_t bitMask = 0;
uint8_t prsPortId;
SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
GET_FM_PCD_PRS_PORT_ID(prsPortId, hardwarePortId);
GET_FM_PCD_INDEX_FLAG(bitMask, prsPortId);
if(include)
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics |= bitMask;
else
p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics &= ~bitMask;
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->ppsc, p_FmPcd->p_FmPcdPrs->fmPcdPrsPortIdStatistics);
return E_OK;
}
t_Error FmPcdPrsIncludePortInStatistics(t_Handle h_FmPcd, uint8_t hardwarePortId, bool include)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
t_FmPcdIpcPrsIncludePort prsIncludePortParams;
t_FmPcdIpcMsg msg;
t_Error err;
SANITY_CHECK_RETURN_ERROR((hardwarePortId >=1 && hardwarePortId <= 16), E_INVALID_VALUE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
if(p_FmPcd->guestId != NCSW_MASTER_ID)
{
prsIncludePortParams.hardwarePortId = hardwarePortId;
prsIncludePortParams.include = include;
memset(&msg, 0, sizeof(msg));
msg.msgId = FM_PCD_PRS_INC_PORT_STATS;
memcpy(msg.msgBody, &prsIncludePortParams, sizeof(prsIncludePortParams));
if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId) +sizeof(prsIncludePortParams),
NULL,
NULL,
NULL,
NULL)) != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
return E_OK;
}
return PrsIncludePortInStatistics(p_FmPcd, hardwarePortId, include);
}
uint32_t FmPcdGetSwPrsOffset(t_Handle h_FmPcd, e_NetHeaderType hdr, uint8_t indexPerHdr)
{
t_FmPcd *p_FmPcd = (t_FmPcd *)h_FmPcd;
t_Error err = E_OK;
t_FmPcdIpcSwPrsLable labelParams;
t_FmPcdIpcMsg msg;
uint32_t prsOffset = 0;
t_FmPcdIpcReply reply;
uint32_t replyLength;
if(p_FmPcd->guestId != NCSW_MASTER_ID)
{
memset(&reply, 0, sizeof(reply));
memset(&msg, 0, sizeof(msg));
labelParams.enumHdr = (uint32_t)hdr;
labelParams.indexPerHdr = indexPerHdr;
msg.msgId = FM_PCD_GET_SW_PRS_OFFSET;
memcpy(msg.msgBody, &labelParams, sizeof(labelParams));
replyLength = sizeof(uint32_t) + sizeof(uint32_t);
if ((err = XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId) +sizeof(labelParams),
(uint8_t*)&reply,
&replyLength,
NULL,
NULL)) != E_OK)
RETURN_ERROR(MAJOR, err, NO_MSG);
if(replyLength != sizeof(uint32_t) + sizeof(uint32_t))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("IPC reply length mismatch"));
memcpy((uint8_t*)&prsOffset, reply.replyBody, sizeof(uint32_t));
return prsOffset;
}
return GetSwPrsOffset(h_FmPcd, hdr, indexPerHdr);
}
void FM_PCD_SetPrsStatistics(t_Handle h_FmPcd, bool enable)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
SANITY_CHECK_RETURN(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
if(p_FmPcd->guestId != NCSW_MASTER_ID)
{
REPORT_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_SetPrsStatistics - guest mode!"));
return;
}
if(enable)
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->ppsc, FM_PCD_PRS_PPSC_ALL_PORTS);
else
WRITE_UINT32(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs->ppsc, 0);
}
t_Error FM_PCD_PrsLoadSw(t_Handle h_FmPcd, t_FmPcdPrsSwParams *p_SwPrs)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
uint32_t *p_LoadTarget, tmpReg;
int i, j;
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_SwPrs, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmPcd->enabled, E_INVALID_HANDLE);
if(p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_PrsLoadSw - guest mode!"));
if(!p_SwPrs->override)
{
if(p_FmPcd->p_FmPcdPrs->p_CurrSwPrs > p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("SW parser base must be larger than current loaded code"));
}
if(p_SwPrs->size > FM_PCD_SW_PRS_SIZE - FM_PCD_PRS_SW_TAIL_SIZE - p_SwPrs->base*2)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_SwPrs->size may not be larger than MAX_SW_PRS_CODE_SIZE"));
if(p_SwPrs->size % 4)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("p_SwPrs->size must be divisible by 4"));
/* save sw parser labels */
if(p_SwPrs->override)
p_FmPcd->p_FmPcdPrs->currLabel = 0;
if(p_FmPcd->p_FmPcdPrs->currLabel+ p_SwPrs->numOfLabels > FM_PCD_PRS_NUM_OF_LABELS)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Exceeded number of labels allowed "));
memcpy(&p_FmPcd->p_FmPcdPrs->labelsTable[p_FmPcd->p_FmPcdPrs->currLabel], p_SwPrs->labelsTable, p_SwPrs->numOfLabels*sizeof(t_FmPcdPrsLabelParams));
p_FmPcd->p_FmPcdPrs->currLabel += p_SwPrs->numOfLabels;
/* load sw parser code */
p_LoadTarget = p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4;
for(i=0;i<p_SwPrs->size/4;i++)
{
tmpReg = 0;
for(j =0;j<4;j++)
{
tmpReg <<= 8;
tmpReg |= *(p_SwPrs->p_Code+i*4+j);
}
WRITE_UINT32(*(p_LoadTarget + i), tmpReg);
}
p_FmPcd->p_FmPcdPrs->p_CurrSwPrs = p_FmPcd->p_FmPcdPrs->p_SwPrsCode + p_SwPrs->base*2/4 + p_SwPrs->size/4;
/* copy data parameters */
for(i=0;i<FM_PCD_PRS_NUM_OF_HDRS;i++)
WRITE_UINT32(*(p_FmPcd->p_FmPcdPrs->p_SwPrsCode+PRS_SW_DATA/4+i), p_SwPrs->swPrsDataParams[i]);
/* Clear last 4 bytes */
WRITE_UINT32(*(p_FmPcd->p_FmPcdPrs->p_SwPrsCode+(PRS_SW_DATA-FM_PCD_PRS_SW_TAIL_SIZE)/4), 0);
return E_OK;
}
t_Error FM_PCD_ConfigPrsMaxCycleLimit(t_Handle h_FmPcd,uint16_t value)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdDriverParam, E_INVALID_HANDLE);
if(p_FmPcd->guestId != NCSW_MASTER_ID)
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("FM_PCD_ConfigPrsMaxCycleLimit - guest mode!"));
p_FmPcd->p_FmPcdDriverParam->prsMaxParseCycleLimit = value;
return E_OK;
}
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
t_Error FM_PCD_PrsDumpRegs(t_Handle h_FmPcd)
{
t_FmPcd *p_FmPcd = (t_FmPcd*)h_FmPcd;
t_FmPcdIpcMsg msg;
DECLARE_DUMP;
SANITY_CHECK_RETURN_ERROR(p_FmPcd, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPcd->p_FmPcdPrs, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_FmPcd->p_FmPcdDriverParam, E_INVALID_STATE);
if(p_FmPcd->guestId != NCSW_MASTER_ID)
{
memset(&msg, 0, sizeof(msg));
msg.msgId = FM_PCD_PRS_DUMP_REGS;
return XX_IpcSendMessage(p_FmPcd->h_IpcSession,
(uint8_t*)&msg,
sizeof(msg.msgId),
NULL,
NULL,
NULL,
NULL);
}
DUMP_SUBTITLE(("\n"));
DUMP_TITLE(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs, ("FmPcdPrsRegs Regs"));
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,rpclim);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,rpimac);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pmeec);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pevr);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pever);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pevfr);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,perr);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,perer);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,perfr);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,ppsc);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,pds);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l2rrs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l3rrs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l4rrs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,srrs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l2rres);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l3rres);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,l4rres);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,srres);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,spcs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,spscs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,hxscs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,mrcs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,mwcs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,mrscs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,mwscs);
DUMP_VAR(p_FmPcd->p_FmPcdPrs->p_FmPcdPrsRegs,fcscs);
return E_OK;
}
#endif /* (defined(DEBUG_ERRORS) && ... */

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sys/contrib/ncsw/Peripherals/FM/Port/fm_port.c Normal file
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sys/contrib/ncsw/Peripherals/FM/Port/fm_port.h Normal file
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@ -0,0 +1,894 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_port.h
@Description FM Port internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_PORT_H
#define __FM_PORT_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_port_ext.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_PORT
#define MIN_EXT_BUF_SIZE 64
#define DATA_ALIGNMENT 64
#define MAX_LIODN_OFFSET 64
/**************************************************************************//**
@Description Memory Map defines
*//***************************************************************************/
#define BMI_PORT_REGS_OFFSET 0
#define QMI_PORT_REGS_OFFSET 0x400
#define PRS_PORT_REGS_OFFSET 0x800
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
#define DEFAULT_PORT_deqHighPriority TRUE
#define DEFAULT_PORT_deqType e_FM_PORT_DEQ_TYPE1
#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT
#define DEFAULT_PORT_deqPrefetchOption e_FM_PORT_DEQ_FULL_PREFETCH
#define DEFAULT_PORT_deqPrefetchOption_HC e_FM_PORT_DEQ_NO_PREFETCH
#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */
#define DEFAULT_PORT_deqByteCnt 2000
#define DEFAULT_PORT_bufferPrefixContent_privDataSize 0
#define DEFAULT_PORT_bufferPrefixContent_passPrsResult FALSE
#define DEFAULT_PORT_bufferPrefixContent_passTimeStamp FALSE
#define DEFAULT_PORT_bufferPrefixContent_allOtherPCDInfo FALSE
#ifdef DEBUG
#define DEFAULT_PORT_bufferPrefixContent_debugInfo FALSE
#endif /* DEBUG */
#define DEFAULT_PORT_bufferPrefixContent_dataAlign DATA_ALIGNMENT
#define DEFAULT_PORT_cheksumLastBytesIgnore 0
#define DEFAULT_PORT_cutBytesFromEnd 4
#define DEFAULT_PORT_txFifoMinFillLevel 0
#define DEFAULT_PORT_txFifoDeqPipelineDepth_IM 2
#define DEFAULT_PORT_txFifoDeqPipelineDepth_1G 2
#define DEFAULT_PORT_txFifoDeqPipelineDepth_10G 8
#define DEFAULT_PORT_txFifoLowComfLevel (5*KILOBYTE)
#define DEFAULT_PORT_rxFifoPriElevationLevel BMI_MAX_FIFO_SIZE
#define DEFAULT_PORT_rxFifoThreshold (BMI_MAX_FIFO_SIZE*3/4)
#define DEFAULT_PORT_frmDiscardOverride FALSE
#define DEFAULT_PORT_dmaSwapData e_FM_PORT_DMA_NO_SWP
#define DEFAULT_PORT_dmaIntContextCacheAttr e_FM_PORT_DMA_NO_STASH
#define DEFAULT_PORT_dmaHeaderCacheAttr e_FM_PORT_DMA_NO_STASH
#define DEFAULT_PORT_dmaScatterGatherCacheAttr e_FM_PORT_DMA_NO_STASH
#define DEFAULT_PORT_dmaWriteOptimize TRUE
#define DEFAULT_PORT_forwardIntContextReuse FALSE
#define DEFAULT_PORT_BufMargins_startMargins 32
#define DEFAULT_PORT_BufMargins_endMargins 0
#define DEFAULT_PORT_syncReq TRUE
#define DEFAULT_PORT_syncReqForHc FALSE
#define DEFAULT_PORT_color e_FM_PORT_COLOR_GREEN
#define DEFAULT_PORT_errorsToDiscard FM_PORT_FRM_ERR_CLS_DISCARD
#define DEFAULT_dualRateLimitScaleDown e_FM_PORT_DUAL_RATE_LIMITER_NONE
#define DEFAULT_rateLimitBurstSizeHighGranularity FALSE
#define DEFAULT_exception IM_EV_BSY
/* Host command port MUST NOT be changed to more than 1 !!! */
#define DEFAULT_PORT_numOfTasks(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? 16 : \
((((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX) || \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? 3 : 1))
#define DEFAULT_PORT_extraNumOfTasks(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? 8 : \
((((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX) || \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? 2 : 0))
#define DEFAULT_PORT_numOfOpenDmas(type) \
(uint32_t)(((type) == e_FM_PORT_TYPE_TX_10G) ? 8 : \
(((type) == e_FM_PORT_TYPE_RX_10G) ? 4 : 1))
#define DEFAULT_PORT_extraNumOfOpenDmas(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? 8 : \
((((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX) || \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? 1 : 0))
#if defined(CONFIG_FMAN_RESOURCE_ALLOCATION_ALGORITHM)
/* Let LLD to set minimum fifosize, otherwise fifosize settings will not work */
#define DEFAULT_PORT_sizeOfFifo(type) \
(uint32_t)(KILOBYTE)
#else
#define DEFAULT_PORT_sizeOfFifo(type) \
(uint32_t)((((type) == e_FM_PORT_TYPE_RX_10G) || \
((type) == e_FM_PORT_TYPE_TX_10G)) ? (16*KILOBYTE) : \
((((type) == e_FM_PORT_TYPE_RX) || \
((type) == e_FM_PORT_TYPE_TX) || \
((type) == e_FM_PORT_TYPE_OH_OFFLINE_PARSING)) ? (4*KILOBYTE) : (1536)))
#endif
#define DEFAULT_PORT_extraSizeOfFifo(type) \
(uint32_t)(((type) == e_FM_PORT_TYPE_RX_10G) ? (8*KILOBYTE) : \
(((type) == e_FM_PORT_TYPE_RX) ? (4*KILOBYTE) : (0)))
#define DEFAULT_PORT_txBdRingLength 16
#define DEFAULT_PORT_rxBdRingLength 128
#define DEFAULT_PORT_ImfwExtStructsMemId 0
#define DEFAULT_PORT_ImfwExtStructsMemAttr MEMORY_ATTR_CACHEABLE
#define OH_PIPELINE_DEPTH 2
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
#define FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS 8
#define FM_PORT_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS 256
typedef _Packed struct
{
volatile uint32_t fmbm_rcfg; /**< Rx Configuration */
volatile uint32_t fmbm_rst; /**< Rx Status */
volatile uint32_t fmbm_rda; /**< Rx DMA attributes*/
volatile uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
volatile uint32_t fmbm_rfed; /**< Rx Frame End Data*/
volatile uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
volatile uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
volatile uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
volatile uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/
volatile uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/
volatile uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/
volatile uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/
volatile uint32_t fmbm_rpp; /**< Rx Policer Profile */
volatile uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */
volatile uint32_t fmbm_reth; /**< Rx Excessive Threshold */
volatile uint32_t reserved1[1]; /**< (0x03C 0x03F) */
volatile uint32_t fmbm_rprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS];
/**< Rx Parse Results Array Initialization*/
volatile uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/
volatile uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/
volatile uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/
volatile uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/
volatile uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */
volatile uint32_t reserved2[0x23];/**< (0x074 0x0FF) */
volatile uint32_t fmbm_ebmpi[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS];
/**< Buffer Manager pool Information-*/
volatile uint32_t fmbm_acnt[FM_PORT_MAX_NUM_OF_EXT_POOLS_ALL_INTEGRATIONS];
/**< Allocate Counter-*/
volatile uint32_t reserved3[8];
/**< 0x130/0x140 - 0x15F reserved -*/
volatile uint32_t fmbm_cgm[FM_PORT_NUM_OF_CONGESTION_GRPS_ALL_INTEGRATIONS/32];
/**< Congestion Group Map*/
volatile uint32_t fmbm_mpd; /**< BM Pool Depletion */
volatile uint32_t reserved4[0x1F];/**< (0x184 0x1FF) */
volatile uint32_t fmbm_rstc; /**< Rx Statistics Counters*/
volatile uint32_t fmbm_rfrc; /**< Rx Frame Counter*/
volatile uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/
volatile uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/
volatile uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/
volatile uint32_t fmbm_rfcd; /**< Rx Frame Discard Counter*/
volatile uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/
volatile uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard Counter-*/
volatile uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter-*/
volatile uint32_t reserved5[0x17];/**< (0x224 0x27F) */
volatile uint32_t fmbm_rpc; /**< Rx Performance Counters*/
volatile uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/
volatile uint32_t fmbm_rccn; /**< Rx Cycle Counter*/
volatile uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/
volatile uint32_t fmbm_rrquc; /**< Rx Receive Queue Utilization Counter*/
volatile uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/
volatile uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/
volatile uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/
volatile uint32_t reserved6[0x18];/**< (0x2A0 0x2FF) */
volatile uint32_t fmbm_rdbg; /**< Rx Debug-*/
} _PackedType t_FmPortRxBmiRegs;
typedef _Packed struct
{
volatile uint32_t fmbm_tcfg; /**< Tx Configuration */
volatile uint32_t fmbm_tst; /**< Tx Status */
volatile uint32_t fmbm_tda; /**< Tx DMA attributes */
volatile uint32_t fmbm_tfp; /**< Tx FIFO Parameters */
volatile uint32_t fmbm_tfed; /**< Tx Frame End Data */
volatile uint32_t fmbm_ticp; /**< Tx Internal Context Parameters */
volatile uint32_t fmbm_tfne; /**< Tx Frame Next Engine. */
volatile uint32_t fmbm_tfca; /**< Tx Frame Command attribute. */
volatile uint32_t fmbm_tcfqid; /**< Tx Confirmation Frame Queue ID. */
volatile uint32_t fmbm_tfeqid; /**< Tx Frame Error Queue ID */
volatile uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine */
volatile uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale */
volatile uint32_t fmbm_trlmt; /**< Tx Rate Limiter */
volatile uint32_t reserved0[0x73];/**< (0x038-0x200) */
volatile uint32_t fmbm_tstc; /**< Tx Statistics Counters */
volatile uint32_t fmbm_tfrc; /**< Tx Frame Counter */
volatile uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter */
volatile uint32_t fmbm_tfledc; /**< Tx Frame Length error discard counter */
volatile uint32_t fmbm_tfufdc; /**< Tx Frame unsupported format discard Counter */
volatile uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */
volatile uint32_t reserved1[0x1A];/**< (0x218-0x280) */
volatile uint32_t fmbm_tpc; /**< Tx Performance Counters*/
volatile uint32_t fmbm_tpcp; /**< Tx Performance Count Parameters*/
volatile uint32_t fmbm_tccn; /**< Tx Cycle Counter*/
volatile uint32_t fmbm_ttuc; /**< Tx Tasks Utilization Counter*/
volatile uint32_t fmbm_ttcquc; /**< Tx Transmit Confirm Queue Utilization Counter*/
volatile uint32_t fmbm_tduc; /**< Tx DMA Utilization Counter*/
volatile uint32_t fmbm_tfuc; /**< Tx FIFO Utilization Counter*/
} _PackedType t_FmPortTxBmiRegs;
typedef _Packed struct
{
volatile uint32_t fmbm_ocfg; /**< O/H Configuration */
volatile uint32_t fmbm_ost; /**< O/H Status */
volatile uint32_t fmbm_oda; /**< O/H DMA attributes */
volatile uint32_t fmbm_oicp; /**< O/H Internal Context Parameters */
volatile uint32_t fmbm_ofdne; /**< O/H Frame Dequeue Next Engine */
volatile uint32_t fmbm_ofne; /**< O/H Frame Next Engine */
volatile uint32_t fmbm_ofca; /**< O/H Frame Command Attributes. */
volatile uint32_t fmbm_ofpne; /**< O/H Frame Parser Next Engine */
volatile uint32_t fmbm_opso; /**< O/H Parse Start Offset */
volatile uint32_t fmbm_opp; /**< O/H Policer Profile */
volatile uint32_t fmbm_occb; /**< O/H Coarse Classification base */
volatile uint32_t fmbm_oim; /**< O/H Internal margins*/
volatile uint32_t reserved0[4]; /**< (0x030 - 0x03F) */
volatile uint32_t fmbm_oprai[FM_PORT_PRS_RESULT_NUM_OF_WORDS];
/**< O/H Parse Results Array Initialization */
volatile uint32_t fmbm_ofqid; /**< O/H Frame Queue ID */
volatile uint32_t fmbm_oefqid; /**< O/H Error Frame Queue ID */
volatile uint32_t fmbm_ofsdm; /**< O/H Frame Status Discard Mask */
volatile uint32_t fmbm_ofsem; /**< O/H Frame Status Error Mask */
volatile uint32_t fmbm_ofene; /**< O/H Frame Enqueue Next Engine */
volatile uint32_t fmbm_orlmts; /**< O/H Rate Limiter Scale */
volatile uint32_t fmbm_orlmt; /**< O/H Rate Limiter */
volatile uint32_t reserved0a[0x21];
/**< 0x07C - 0x0FF Reserved */
union
{
volatile uint32_t fmbm_oebmpi[FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS];
/**< Buffer Manager Observed Pool Information */
volatile uint32_t reserved0b[0x18];
}; /**< 0x100 - 0x15F Reserved */
volatile uint32_t fmbm_ocgm; /**< Observed Congestion Group Map */
volatile uint32_t reserved0c[0x7];/**< 0x164 - 0x17F Reserved */
volatile uint32_t fmbm_ompd; /**< Observed BMan Pool Depletion */
volatile uint32_t reserved0d[0x1F];
/**< 0x184 - 0x1FF Reserved */
volatile uint32_t fmbm_ostc; /**< O/H Statistics Counters */
volatile uint32_t fmbm_ofrc; /**< O/H Frame Counter */
volatile uint32_t fmbm_ofdc; /**< O/H Frames Discard Counter */
volatile uint32_t fmbm_ofledc; /**< O/H Frames Length Error Discard Counter */
volatile uint32_t fmbm_ofufdc; /**< O/H Frames Unsupported Format Discard Counter */
volatile uint32_t fmbm_offc; /**< O/H Filter Frames Counter */
volatile uint32_t fmbm_ofwdc; /**< - Rx Frames WRED Discard Counter */
volatile uint32_t fmbm_ofldec; /**< O/H Frames List DMA Error Counter */
volatile uint32_t fmbm_obdc; /**< O/H Buffers Deallocate Counter */
volatile uint32_t reserved2[0x17];/**< (0x218 - 0x27F) */
volatile uint32_t fmbm_opc; /**< O/H Performance Counters */
volatile uint32_t fmbm_opcp; /**< O/H Performance Count Parameters */
volatile uint32_t fmbm_occn; /**< O/H Cycle Counter */
volatile uint32_t fmbm_otuc; /**< O/H Tasks Utilization Counter */
volatile uint32_t fmbm_oduc; /**< O/H DMA Utilization Counter */
volatile uint32_t fmbm_ofuc; /**< O/H FIFO Utilization Counter */
} _PackedType t_FmPortOhBmiRegs;
typedef _Packed union
{
t_FmPortRxBmiRegs rxPortBmiRegs;
t_FmPortTxBmiRegs txPortBmiRegs;
t_FmPortOhBmiRegs ohPortBmiRegs;
} _PackedType u_FmPortBmiRegs;
typedef _Packed struct
{
volatile uint32_t reserved1[2]; /**< 0xn024 - 0x02B */
volatile uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */
volatile uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */
volatile uint32_t fmqm_pndtfc; /**< PortID n Dequeue Total Frame Counter */
volatile uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID from Default Counter */
volatile uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */
} _PackedType t_FmPortNonRxQmiRegs;
typedef _Packed struct
{
volatile uint32_t fmqm_pnc; /**< PortID n Configuration Register */
volatile uint32_t fmqm_pns; /**< PortID n Status Register */
volatile uint32_t fmqm_pnts; /**< PortID n Task Status Register */
volatile uint32_t reserved0[4]; /**< 0xn00C - 0xn01B */
volatile uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */
volatile uint32_t fmqm_pnetfc; /**< PortID n Enqueue Total Frame Counter */
t_FmPortNonRxQmiRegs nonRxQmiRegs; /**< Registers for Tx Hc & Op ports */
} _PackedType t_FmPortQmiRegs;
typedef _Packed struct
{
_Packed struct
{
volatile uint32_t softSeqAttach; /**< Soft Sequence Attachment */
volatile uint32_t lcv; /**< Line-up Enable Confirmation Mask */
} _PackedType hdrs[FM_PCD_PRS_NUM_OF_HDRS];
volatile uint8_t reserved0[0x378];
volatile uint32_t pcac; /**< Parse Internal Memory Configuration Access Control Register */
volatile uint32_t pctpid; /**< Parse Internal Memory Configured TPID Register */
} _PackedType t_FmPortPrsRegs;
/**************************************************************************//*
@Description Basic buffer descriptor (BD) structure
*//***************************************************************************/
typedef _Packed struct
{
volatile uint16_t status;
volatile uint16_t length;
volatile uint8_t reserved0[0x6];
volatile uint8_t reserved1[0x1];
volatile t_FmPhysAddr buff;
} _PackedType t_FmImBd;
typedef _Packed struct
{
volatile uint16_t gen; /**< tbd */
volatile uint8_t reserved0[0x1];
volatile t_FmPhysAddr bdRingBase; /**< tbd */
volatile uint16_t bdRingSize; /**< tbd */
volatile uint16_t offsetIn; /**< tbd */
volatile uint16_t offsetOut; /**< tbd */
volatile uint8_t reserved1[0x12]; /**< 0x0e - 0x1f */
} _PackedType t_FmPortImQd;
typedef _Packed struct
{
volatile uint32_t mode; /**< Mode register */
volatile uint32_t rxQdPtr; /**< tbd */
volatile uint32_t txQdPtr; /**< tbd */
volatile uint16_t mrblr; /**< tbd */
volatile uint16_t rxQdBsyCnt; /**< tbd */
volatile uint8_t reserved0[0x10]; /**< 0x10 - 0x1f */
t_FmPortImQd rxQd;
t_FmPortImQd txQd;
volatile uint8_t reserved1[0xa0]; /**< 0x60 - 0xff */
} _PackedType t_FmPortImPram;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description Registers bit fields
*//***************************************************************************/
/**************************************************************************//**
@Description BMI defines
*//***************************************************************************/
#define BMI_PORT_CFG_EN 0x80000000
#define BMI_PORT_CFG_EN_MACSEC 0x00800000
#define BMI_PORT_CFG_FDOVR 0x02000000
#define BMI_PORT_CFG_IM 0x01000000
#define BMI_PORT_STATUS_BSY 0x80000000
#define BMI_COUNTERS_EN 0x80000000
#define BMI_DMA_ATTR_WRITE_OPTIMIZE 0x00100000
#define BMI_PORT_RFNE_FRWD_DCL4C 0x10000000
#define BMI_PORT_RFNE_FRWD_RPD 0x40000000
#define BMI_RFNE_FDCS_MASK 0xFF000000
#define BMI_CMD_MR_LEAC 0x00200000
#define BMI_CMD_MR_SLEAC 0x00100000
#define BMI_CMD_MR_MA 0x00080000
#define BMI_CMD_MR_DEAS 0x00040000
#define BMI_CMD_TX_MR_DEF (0)
#define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \
BMI_CMD_MR_SLEAC | \
BMI_CMD_MR_MA | \
BMI_CMD_MR_DEAS)
#define BMI_CMD_ATTR_ORDER 0x80000000
#define BMI_CMD_ATTR_SYNC 0x02000000
#define BMI_CMD_ATTR_MACCMD_MASK 0x0000ff00
#define BMI_CMD_ATTR_MACCMD_OVERRIDE 0x00008000
#define BMI_CMD_ATTR_MACCMD_SECURED 0x00001000
#define BMI_CMD_ATTR_MACCMD_SC_MASK 0x00000f00
#define BMI_EXT_BUF_POOL_VALID 0x80000000
#define BMI_EXT_BUF_POOL_EN_COUNTER 0x40000000
#define BMI_EXT_BUF_POOL_BACKUP 0x20000000
#define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000
#define BMI_STATUS_RX_MASK_UNUSED (uint32_t)(~(FM_PORT_FRM_ERR_DMA | \
FM_PORT_FRM_ERR_PHYSICAL | \
FM_PORT_FRM_ERR_SIZE | \
FM_PORT_FRM_ERR_CLS_DISCARD | \
FM_PORT_FRM_ERR_EXTRACTION | \
FM_PORT_FRM_ERR_NO_SCHEME | \
FM_PORT_FRM_ERR_COLOR_RED | \
FM_PORT_FRM_ERR_COLOR_YELLOW | \
FM_PORT_FRM_ERR_ILL_PLCR | \
FM_PORT_FRM_ERR_PLCR_FRAME_LEN | \
FM_PORT_FRM_ERR_PRS_TIMEOUT | \
FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \
FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \
FM_PORT_FRM_ERR_PRS_HDR_ERR | \
FM_PORT_FRM_ERR_PROCESS_TIMEOUT | \
FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW))
#define BMI_STATUS_OP_MASK_UNUSED (uint32_t)(BMI_STATUS_RX_MASK_UNUSED & \
~(FM_PORT_FRM_ERR_LENGTH | \
FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT))
#define BMI_RATE_LIMIT_EN 0x80000000
#define BMI_RATE_LIMIT_BURST_SIZE_GRAN 0x80000000
#define BMI_RATE_LIMIT_SCALE_BY_2 0x00000001
#define BMI_RATE_LIMIT_SCALE_BY_4 0x00000002
#define BMI_RATE_LIMIT_SCALE_BY_8 0x00000003
#define BMI_RX_FIFO_THRESHOLD_BC 0x80000000
#define BMI_PRS_RESULT_HIGH 0x00000000
#define BMI_PRS_RESULT_LOW 0xFFFFFFFF
#define RX_ERRS_TO_ENQ (FM_PORT_FRM_ERR_DMA | \
FM_PORT_FRM_ERR_PHYSICAL | \
FM_PORT_FRM_ERR_SIZE | \
FM_PORT_FRM_ERR_EXTRACTION | \
FM_PORT_FRM_ERR_NO_SCHEME | \
FM_PORT_FRM_ERR_ILL_PLCR | \
FM_PORT_FRM_ERR_PLCR_FRAME_LEN | \
FM_PORT_FRM_ERR_PRS_TIMEOUT | \
FM_PORT_FRM_ERR_PRS_ILL_INSTRUCT | \
FM_PORT_FRM_ERR_BLOCK_LIMIT_EXCEEDED | \
FM_PORT_FRM_ERR_PRS_HDR_ERR | \
FM_PORT_FRM_ERR_PROCESS_TIMEOUT | \
FM_PORT_FRM_ERR_KEYSIZE_OVERFLOW)
#ifdef FM_CAPWAP_SUPPORT
#define OP_ERRS_TO_ENQ (RX_ERRS_TO_ENQ | \
FM_PORT_FRM_ERR_LENGTH | \
FM_PORT_FRM_ERR_NON_FM | \
FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT)
#else
#define OP_ERRS_TO_ENQ (RX_ERRS_TO_ENQ | \
FM_PORT_FRM_ERR_LENGTH | \
FM_PORT_FRM_ERR_UNSUPPORTED_FORMAT)
#endif /* FM_CAPWAP_SUPPORT */
/* shifts */
#define BMI_PORT_CFG_MS_SEL_SHIFT 16
#define BMI_DMA_ATTR_SWP_SHIFT 30
#define BMI_DMA_ATTR_IC_CACHE_SHIFT 28
#define BMI_DMA_ATTR_HDR_CACHE_SHIFT 26
#define BMI_DMA_ATTR_SG_CACHE_SHIFT 24
#define BMI_IM_FOF_SHIFT 28
#define BMI_PR_PORTID_SHIFT 24
#define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16
#define BMI_RX_FIFO_THRESHOLD_SHIFT 0
#define BMI_RX_FRAME_END_CS_IGNORE_SHIFT 24
#define BMI_RX_FRAME_END_CUT_SHIFT 16
#define BMI_IC_TO_EXT_SHIFT 16
#define BMI_IC_FROM_INT_SHIFT 8
#define BMI_IC_SIZE_SHIFT 0
#define BMI_INT_BUF_MARG_SHIFT 28
#define BMI_EXT_BUF_MARG_START_SHIFT 16
#define BMI_EXT_BUF_MARG_END_SHIFT 0
#define BMI_CMD_ATTR_COLOR_SHIFT 26
#define BMI_CMD_ATTR_COM_MODE_SHIFT 16
#define BMI_CMD_ATTR_MACCMD_SHIFT 8
#define BMI_CMD_ATTR_MACCMD_OVERRIDE_SHIFT 15
#define BMI_CMD_ATTR_MACCMD_SECURED_SHIFT 12
#define BMI_CMD_ATTR_MACCMD_SC_SHIFT 8
#define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16
#define BMI_POOL_DEP_NUM_OF_POOLS_VECTOR_SHIFT 24
#define BMI_EXT_BUF_POOL_ID_SHIFT 16
#define BMI_TX_FIFO_MIN_FILL_SHIFT 16
#define BMI_TX_FIFO_PIPELINE_DEPTH_SHIFT 12
#define BMI_TX_LOW_COMF_SHIFT 0
#define BMI_TX_FRAME_END_CS_IGNORE_SHIFT 24
#define BMI_PERFORMANCE_TASK_COMP_SHIFT 24
#define BMI_PERFORMANCE_PORT_COMP_SHIFT 16
#define BMI_PERFORMANCE_DMA_COMP_SHIFT 12
#define BMI_PERFORMANCE_FIFO_COMP_SHIFT 0
#define BMI_MAX_BURST_SHIFT 16
#define BMI_COUNT_RATE_UNIT_SHIFT 16
/* sizes */
#define FRAME_END_DATA_SIZE 16
#define OFFSET_UNITS 16
#define FRAME_OFFSET_UNITS 16
#define MAX_EXT_OFFSET 496
#define MAX_EXT_BUFFER_OFFSET 511
#define MAX_INT_OFFSET 240
#define MIN_TX_INT_OFFSET 16
#define MAX_IC_SIZE 256
#define MAX_FRAME_OFFSET 64
#define MAX_FIFO_PIPELINE_DEPTH 8
#define MAX_PERFORMANCE_TASK_COMP 64
#define MAX_PERFORMANCE_TX_QUEUE_COMP 8
#define MAX_PERFORMANCE_RX_QUEUE_COMP 64
#define MAX_PERFORMANCE_DMA_COMP 16
#define MAX_NUM_OF_TASKS 64
#define MAX_NUM_OF_EXTRA_TASKS 8
#define MAX_NUM_OF_DMAS 16
#define MAX_NUM_OF_EXTRA_DMAS 8
#define MAX_BURST_SIZE 1024
#define FRAG_EXTRA_SPACE 32
/**************************************************************************//**
@Description QMI defines
*//***************************************************************************/
/* masks */
#define QMI_PORT_CFG_EN 0x80000000
#define QMI_PORT_CFG_EN_COUNTERS 0x10000000
#define QMI_PORT_STATUS_DEQ_TNUM_BSY 0x80000000
#define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000
#define QMI_DEQ_CFG_PREFETCH_NO_TNUM 0x02000000
#define QMI_DEQ_CFG_PREFETCH_WAITING_TNUM 0
#define QMI_DEQ_CFG_PREFETCH_1_FRAME 0
#define QMI_DEQ_CFG_PREFETCH_3_FRAMES 0x01000000
#define QMI_DEQ_CFG_PRI 0x80000000
#define QMI_DEQ_CFG_TYPE1 0x10000000
#define QMI_DEQ_CFG_TYPE2 0x20000000
#define QMI_DEQ_CFG_TYPE3 0x30000000
#define QMI_DEQ_CFG_SUBPORTAL_MASK 0x1f
#define QMI_DEQ_CFG_SUBPORTAL_SHIFT 20
/**************************************************************************//**
@Description PARSER defines
*//***************************************************************************/
/* masks */
#define PRS_HDR_ERROR_DIS 0x00000800
#define PRS_HDR_SW_PRS_EN 0x00000400
#define PRS_CP_OFFSET_MASK 0x0000000F
#define PRS_TPID1_MASK 0xFFFF0000
#define PRS_TPID2_MASK 0x0000FFFF
#define PRS_TPID_DFLT 0x91009100
#define PRS_HDR_MPLS_LBL_INTER_EN 0x00200000
#define PRS_HDR_IPV6_ROUTE_HDR_DIS 0x00008000
#define PRS_HDR_PPPOE_MTU_CHECK_EN 0x80000000
#define PRS_HDR_UDP_PAD_REMOVAL 0x80000000
#define PRS_HDR_TCP_PAD_REMOVAL 0x80000000
#define PRS_CAC_STOP 0x00000001
#define PRS_CAC_ACTIVE 0x00000100
/* shifts */
#define PRS_PCTPID_SHIFT 16
#define PRS_HDR_MPLS_NEXT_HDR_SHIFT 22
#define PRS_HDR_ETH_BC_SHIFT 28
#define PRS_HDR_ETH_MC_SHIFT 24
#define PRS_HDR_VLAN_STACKED_SHIFT 16
#define PRS_HDR_MPLS_STACKED_SHIFT 16
#define PRS_HDR_IPV4_1_BC_SHIFT 28
#define PRS_HDR_IPV4_1_MC_SHIFT 24
#define PRS_HDR_IPV4_2_UC_SHIFT 20
#define PRS_HDR_IPV4_2_MC_BC_SHIFT 16
#define PRS_HDR_IPV6_1_MC_SHIFT 24
#define PRS_HDR_IPV6_2_UC_SHIFT 20
#define PRS_HDR_IPV6_2_MC_SHIFT 16
#define PRS_HDR_ETH_BC_MASK 0x0fffffff
#define PRS_HDR_ETH_MC_MASK 0xf0ffffff
#define PRS_HDR_VLAN_STACKED_MASK 0xfff0ffff
#define PRS_HDR_MPLS_STACKED_MASK 0xfff0ffff
#define PRS_HDR_IPV4_1_BC_MASK 0x0fffffff
#define PRS_HDR_IPV4_1_MC_MASK 0xf0ffffff
#define PRS_HDR_IPV4_2_UC_MASK 0xff0fffff
#define PRS_HDR_IPV4_2_MC_BC_MASK 0xfff0ffff
#define PRS_HDR_IPV6_1_MC_MASK 0xf0ffffff
#define PRS_HDR_IPV6_2_UC_MASK 0xff0fffff
#define PRS_HDR_IPV6_2_MC_MASK 0xfff0ffff
/* others */
#define PRS_HDR_ENTRY_SIZE 8
#define DEFAULT_CLS_PLAN_VECTOR 0xFFFFFFFF
#define IPSEC_SW_PATCH_START 0x20
#define SCTP_SW_PATCH_START 0x4D
#define DCCP_SW_PATCH_START 0x41
#define IP_FRAG_SW_PATCH_IPv4 0x300
#define IP_FRAG_SW_PATCH_IPv6_0 0x320
#define IP_FRAG_SW_PATCH_IPv6_1 0x372
/**************************************************************************//**
@Description IM defines
*//***************************************************************************/
#define BD_R_E 0x80000000
#define BD_L 0x08000000
#define BD_RX_CRE 0x00080000
#define BD_RX_FTL 0x00040000
#define BD_RX_FTS 0x00020000
#define BD_RX_OV 0x00010000
#define BD_RX_ERRORS (BD_RX_CRE | BD_RX_FTL | BD_RX_FTS | BD_RX_OV)
#define BD_ERROR_PASS_FRAME BD_RX_ERRORS
#define FM_IM_SIZEOF_BD sizeof(t_FmImBd)
#define BD_STATUS_MASK 0xffff0000
#define BD_LENGTH_MASK 0x0000ffff
#define BD_STATUS_AND_LENGTH_SET(bd, val) WRITE_UINT32(*(volatile uint32_t*)(bd), (val))
#define BD_STATUS_AND_LENGTH(bd) GET_UINT32(*(volatile uint32_t*)(bd))
#define BD_GET(id) &p_FmPort->im.p_BdRing[id]
#define IM_ILEGAL_BD_ID 0xffff
/* others */
#define IM_PRAM_ALIGN 0x100
/* masks */
#define IM_MODE_GBL 0x20000000
#define IM_MODE_BO_MASK 0x18000000
#define IM_MODE_BO_SHIFT 3
#define IM_MODE_GRC_STP 0x00800000
#define IM_MODE_SET_BO(val) (uint32_t)((val << (31-IM_MODE_BO_SHIFT)) & IM_MODE_BO_MASK)
#define IM_RXQD_BSYINTM 0x0008
#define IM_RXQD_RXFINTM 0x0010
#define IM_RXQD_FPMEVT_SEL_MASK 0x0003
#define IM_EV_BSY 0x40000000
#define IM_EV_RX 0x80000000
typedef struct {
t_Handle h_FmMuram;
t_FmPortImPram *p_FmPortImPram;
uint8_t fwExtStructsMemId;
uint32_t fwExtStructsMemAttr;
uint16_t bdRingSize;
t_FmImBd *p_BdRing;
t_Handle *p_BdShadow;
uint16_t currBdId;
uint16_t firstBdOfFrameId;
/* Rx port parameters */
uint8_t dataMemId; /**< Memory partition ID for data buffers */
uint32_t dataMemAttributes; /**< Memory attributes for data buffers */
t_BufferPoolInfo rxPool;
uint16_t mrblr;
uint16_t rxFrameAccumLength;
t_FmPortImRxStoreCallback *f_RxStore;
/* Tx port parameters */
uint32_t txFirstBdStatus;
t_FmPortImTxConfCallback *f_TxConf;
} t_FmMacIm;
/**************************************************************************//**
@Description structure for defining internal context copying
*//***************************************************************************/
typedef struct
{
uint16_t extBufOffset; /**< Offset in External buffer to which internal
context is copied to (Rx) or taken from (Tx, Op). */
uint8_t intContextOffset; /**< Offset within internal context to copy from
(Rx) or to copy to (Tx, Op). */
uint16_t size; /**< Internal offset size to be copied */
} t_FmPortIntContextDataCopy;
/**************************************************************************//**
@Description struct for defining external buffer margins
*//***************************************************************************/
typedef struct {
uint16_t startMargins; /**< Number of bytes to be left at the beginning
of the external buffer (must be divisible by 16) */
uint16_t endMargins; /**< number of bytes to be left at the end
of the external buffer(must be divisible by 16) */
} t_FmPortBufMargins;
typedef struct {
uint32_t dataOffset;
uint32_t prsResultOffset;
uint32_t timeStampOffset;
uint32_t hashResultOffset;
uint32_t pcdInfoOffset;
uint32_t manipOffset;
#ifdef DEBUG
uint32_t debugOffset;
#endif /* DEBUG */
} t_FmPortBufferOffsets;
typedef struct {
uint32_t dfltFqid;
uint32_t confFqid;
uint32_t errFqid;
uintptr_t baseAddr;
uint8_t deqSubPortal;
bool deqHighPriority;
e_FmPortDeqType deqType;
#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT
e_FmPortDeqPrefetchOption deqPrefetchOption;
#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */
uint16_t deqByteCnt;
uint8_t cheksumLastBytesIgnore;
uint8_t cutBytesFromEnd;
t_FmPortBufPoolDepletion bufPoolDepletion;
uint8_t pipelineDepth;
uint16_t fifoLowComfLevel;
bool frmDiscardOverride;
bool enRateLimit;
t_FmPortRateLimit rateLimit;
e_FmPortDualRateLimiterScaleDown rateLimitDivider;
bool enBufPoolDepletion;
uint16_t liodnOffset;
uint16_t liodnBase;
t_FmPortExtPools extBufPools;
e_FmPortDmaSwap dmaSwapData;
e_FmPortDmaCache dmaIntContextCacheAttr;
e_FmPortDmaCache dmaHeaderCacheAttr;
e_FmPortDmaCache dmaScatterGatherCacheAttr;
bool dmaReadOptimize;
bool dmaWriteOptimize;
uint32_t txFifoMinFillLevel;
uint32_t txFifoLowComfLevel;
uint32_t rxFifoPriElevationLevel;
uint32_t rxFifoThreshold;
t_FmPortBufMargins bufMargins;
t_FmPortIntContextDataCopy intContext;
bool syncReq;
e_FmPortColor color;
fmPortFrameErrSelect_t errorsToDiscard;
fmPortFrameErrSelect_t errorsToEnq;
uint64_t fmMuramPhysBaseAddr;
bool forwardReuseIntContext;
t_FmPortBufferPrefixContent bufferPrefixContent;
uint8_t internalBufferOffset;
t_FmPortBackupBmPools *p_BackupBmPools;
bool dontReleaseBuf;
} t_FmPortDriverParam;
typedef struct {
t_Handle h_Fm;
t_Handle h_FmPcd;
uint8_t portId;
e_FmPortType portType;
int enabled;
char name[MODULE_NAME_SIZE];
uint8_t hardwarePortId;
uint16_t fmClkFreq;
t_FmPortQmiRegs *p_FmPortQmiRegs;
u_FmPortBmiRegs *p_FmPortBmiRegs;
t_FmPortPrsRegs *p_FmPortPrsRegs;
fmPcdEngines_t pcdEngines;
uint32_t savedBmiNia;
uint8_t netEnvId;
uint32_t optArray[FM_PCD_MAX_NUM_OF_OPTIONS(FM_PCD_MAX_NUM_OF_CLS_PLANS)];
uint32_t lcvs[FM_PCD_PRS_NUM_OF_HDRS];
uint8_t privateInfo;
uint32_t schemesPerPortVector;
bool useClsPlan;
uint8_t clsPlanGrpId;
t_Handle ccTreeId;
t_Handle completeArg;
void (*f_Complete)(t_Handle arg);
t_FmPortBufferOffsets bufferOffsets;
/* Independent-Mode parameters support */
bool imEn;
t_FmMacIm im;
uint8_t txFifoDeqPipelineDepth;
volatile bool lock;
t_Handle h_Spinlock;
t_FmPortExceptionCallback *f_Exception;
t_Handle h_App;
uint8_t internalBufferOffset;
uint8_t fmanCtrlEventId;
uint32_t exceptions;
bool polling;
uint8_t numOfTasks;
t_FmPortExtPools extBufPools;
uint32_t requiredAction;
uint32_t savedQmiPnen;
uint32_t savedNonRxQmiRegsPndn;
int savedPrsStartOffset;
t_FmPortRsrc openDmas;
t_FmPortRsrc tasks;
t_FmPortRsrc fifoBufs;
t_FmInterModulePortRxPoolsParams rxPoolsParams;
t_FmPortDriverParam *p_FmPortDriverParam;
} t_FmPort;
#define CHECK_FM_CTL_AC_POST_FETCH_PCD(savedBmiNia) \
((((savedBmiNia) & NIA_ENG_MASK) == NIA_ENG_FM_CTL) && \
((((savedBmiNia) & NIA_FM_CTL_AC_MASK) == NIA_FM_CTL_AC_POST_FETCH_PCD) || \
(((savedBmiNia) & NIA_FM_CTL_AC_MASK) == NIA_FM_CTL_AC_POST_FETCH_PCD_UDP_LEN)))
void FmPortConfigIM (t_FmPort *p_FmPort, t_FmPortParams *p_FmPortParams);
t_Error FmPortImCheckInitParameters(t_FmPort *p_FmPort);
t_Error FmPortImInit(t_FmPort *p_FmPort);
void FmPortImFree(t_FmPort *p_FmPort);
t_Error FmPortImEnable (t_FmPort *p_FmPort);
t_Error FmPortImDisable (t_FmPort *p_FmPort);
t_Error FmPortImRx (t_FmPort *p_FmPort);
void FmPortSetMacsecLcv(t_Handle h_FmPort);
void FmPortSetMacsecCmd(t_Handle h_FmPort, uint8_t dfltSci);
static __inline__ uint8_t * BdBufferGet (t_PhysToVirt *f_PhysToVirt, t_FmImBd *p_Bd)
{
uint64_t physAddr = (uint64_t)((uint64_t)GET_UINT8(p_Bd->buff.high) << 32);
physAddr |= GET_UINT32(p_Bd->buff.low);
return (uint8_t *)f_PhysToVirt((physAddress_t)(physAddr));
}
static __inline__ void SET_ADDR(volatile t_FmPhysAddr *fmPhysAddr, uint64_t value)
{
WRITE_UINT8(fmPhysAddr->high,(uint8_t)((value & 0x000000ff00000000LL) >> 32));
WRITE_UINT32(fmPhysAddr->low,(uint32_t)value);
}
static __inline__ void BdBufferSet(t_VirtToPhys *f_VirtToPhys, t_FmImBd *p_Bd, uint8_t *p_Buffer)
{
uint64_t physAddr = (uint64_t)(f_VirtToPhys(p_Buffer));
SET_ADDR(&p_Bd->buff, physAddr);
}
static __inline__ uint16_t GetNextBdId(t_FmPort *p_FmPort, uint16_t id)
{
if (id < p_FmPort->im.bdRingSize-1)
return (uint16_t)(id+1);
else
return 0;
}
#endif /* __FM_PORT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_port_im.c
@Description FM Port Independent-Mode ...
*//***************************************************************************/
#include "std_ext.h"
#include "string_ext.h"
#include "error_ext.h"
#include "fm_muram_ext.h"
#include "fm_port.h"
#define TX_CONF_STATUS_UNSENT 0x1
#ifdef CORE_8BIT_ACCESS_ERRATA
#undef WRITE_UINT16
#undef GET_UINT16
#define WRITE_UINT16(addr, val) \
do{ \
if((int)&(addr) % 4) \
WRITE_UINT32(*(uint32_t*)(uint32_t)((uint32_t)&addr & ~0x3L), \
((GET_UINT32(*(uint32_t*)(uint32_t)((uint32_t)&addr & ~0x3L)) & 0xffff0000) | (uint32_t)val)); \
else \
WRITE_UINT32(*(uint32_t*)&addr, \
((GET_UINT32(*(uint32_t*)&addr) & 0x0000ffff) | (uint32_t)val<<16)); \
}while(0);
#define GET_UINT16(addr) (((uint32_t)&addr%4) ? \
((uint16_t)GET_UINT32(*(uint32_t*)(uint32_t)((uint32_t)&addr & ~0x3L))): \
((uint16_t)(GET_UINT32(*(uint32_t*)(uint32_t)&addr) >> 16)))
#endif /* CORE_8BIT_ACCESS_ERRATA */
typedef enum e_TxConfType
{
e_TX_CONF_TYPE_CHECK = 0 /**< check if all the buffers were touched by the muxator, no confirmation callback */
,e_TX_CONF_TYPE_CALLBACK = 1 /**< confirm to user all the available sent buffers */
,e_TX_CONF_TYPE_FLUSH = 3 /**< confirm all buffers plus the unsent one with an appropriate status */
} e_TxConfType;
static void ImException(t_Handle h_FmPort, uint32_t event)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
ASSERT_COND(((event & IM_EV_RX) && FmIsMaster(p_FmPort->h_Fm)) ||
!FmIsMaster(p_FmPort->h_Fm));
if (event & IM_EV_RX)
FmPortImRx(p_FmPort);
if ((event & IM_EV_BSY) && p_FmPort->f_Exception)
p_FmPort->f_Exception(p_FmPort->h_App, e_FM_PORT_EXCEPTION_IM_BUSY);
}
static t_Error TxConf(t_FmPort *p_FmPort, e_TxConfType confType)
{
t_Error retVal = E_BUSY;
uint32_t bdStatus;
uint16_t savedStartBdId, confBdId;
ASSERT_COND(p_FmPort);
/*
if (confType==e_TX_CONF_TYPE_CHECK)
return (WfqEntryIsQueueEmpty(p_FmPort->im.h_WfqEntry) ? E_OK : E_BUSY);
*/
confBdId = savedStartBdId = p_FmPort->im.currBdId;
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(confBdId));
/* If R bit is set, we don't enter, or we break.
we run till we get to R, or complete the loop */
while ((!(bdStatus & BD_R_E) || (confType == e_TX_CONF_TYPE_FLUSH)) && (retVal != E_OK))
{
if (confType & e_TX_CONF_TYPE_CALLBACK) /* if it is confirmation with user callbacks */
BD_STATUS_AND_LENGTH_SET(BD_GET(confBdId), 0);
/* case 1: R bit is 0 and Length is set -> confirm! */
if ((confType & e_TX_CONF_TYPE_CALLBACK) && (bdStatus & BD_LENGTH_MASK))
{
if (p_FmPort->im.f_TxConf)
{
if ((confType == e_TX_CONF_TYPE_FLUSH) && (bdStatus & BD_R_E))
p_FmPort->im.f_TxConf(p_FmPort->h_App,
BdBufferGet(XX_PhysToVirt, BD_GET(confBdId)),
TX_CONF_STATUS_UNSENT,
p_FmPort->im.p_BdShadow[confBdId]);
else
p_FmPort->im.f_TxConf(p_FmPort->h_App,
BdBufferGet(XX_PhysToVirt, BD_GET(confBdId)),
0,
p_FmPort->im.p_BdShadow[confBdId]);
}
}
/* case 2: R bit is 0 and Length is 0 -> not used yet, nop! */
confBdId = GetNextBdId(p_FmPort, confBdId);
if (confBdId == savedStartBdId)
retVal = E_OK;
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(confBdId));
}
return retVal;
}
t_Error FmPortImEnable(t_FmPort *p_FmPort)
{
uint32_t tmpReg = GET_UINT32(p_FmPort->im.p_FmPortImPram->mode);
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, (uint32_t)(tmpReg & ~IM_MODE_GRC_STP));
return E_OK;
}
t_Error FmPortImDisable(t_FmPort *p_FmPort)
{
uint32_t tmpReg = GET_UINT32(p_FmPort->im.p_FmPortImPram->mode);
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, (uint32_t)(tmpReg | IM_MODE_GRC_STP));
return E_OK;
}
t_Error FmPortImRx(t_FmPort *p_FmPort)
{
t_Handle h_CurrUserPriv, h_NewUserPriv;
uint32_t bdStatus;
volatile uint8_t buffPos;
uint16_t length;
uint16_t errors/*, reportErrors*/;
uint8_t *p_CurData, *p_Data;
uint32_t flags;
ASSERT_COND(p_FmPort);
flags = XX_LockIntrSpinlock(p_FmPort->h_Spinlock);
if (p_FmPort->lock)
{
XX_UnlockIntrSpinlock(p_FmPort->h_Spinlock, flags);
return E_OK;
}
p_FmPort->lock = TRUE;
XX_UnlockIntrSpinlock(p_FmPort->h_Spinlock, flags);
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
while (!(bdStatus & BD_R_E)) /* while there is data in the Rx BD */
{
if ((p_Data = p_FmPort->im.rxPool.f_GetBuf(p_FmPort->im.rxPool.h_BufferPool, &h_NewUserPriv)) == NULL)
{
p_FmPort->lock = FALSE;
RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Data buffer"));
}
if (p_FmPort->im.firstBdOfFrameId == IM_ILEGAL_BD_ID)
p_FmPort->im.firstBdOfFrameId = p_FmPort->im.currBdId;
errors = 0;
p_CurData = BdBufferGet(p_FmPort->im.rxPool.f_PhysToVirt, BD_GET(p_FmPort->im.currBdId));
h_CurrUserPriv = p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId];
length = (uint16_t)((bdStatus & BD_L) ?
((bdStatus & BD_LENGTH_MASK) - p_FmPort->im.rxFrameAccumLength):
(bdStatus & BD_LENGTH_MASK));
p_FmPort->im.rxFrameAccumLength += length;
/* determine whether buffer is first, last, first and last (single */
/* buffer frame) or middle (not first and not last) */
buffPos = (uint8_t)((p_FmPort->im.currBdId == p_FmPort->im.firstBdOfFrameId) ?
((bdStatus & BD_L) ? SINGLE_BUF : FIRST_BUF) :
((bdStatus & BD_L) ? LAST_BUF : MIDDLE_BUF));
if (bdStatus & BD_L)
{
p_FmPort->im.rxFrameAccumLength = 0;
p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID;
}
BdBufferSet(p_FmPort->im.rxPool.f_VirtToPhys, BD_GET(p_FmPort->im.currBdId), p_Data);
BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.currBdId), BD_R_E);
errors = (uint16_t)((bdStatus & BD_RX_ERRORS) >> 16);
p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId] = h_NewUserPriv;
p_FmPort->im.currBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.offsetOut, (uint16_t)(p_FmPort->im.currBdId<<4));
/* Pass the buffer if one of the conditions is true:
- There are no errors
- This is a part of a larger frame ( the application has already received some buffers )
- There is an error, but it was defined to be passed anyway. */
if ((buffPos != SINGLE_BUF) || !errors || (errors & (uint16_t)(BD_ERROR_PASS_FRAME>>16)))
{
if (p_FmPort->im.f_RxStore(p_FmPort->h_App,
p_CurData,
length,
errors,
buffPos,
h_CurrUserPriv) == e_RX_STORE_RESPONSE_PAUSE)
break;
}
else if (p_FmPort->im.rxPool.f_PutBuf(p_FmPort->im.rxPool.h_BufferPool,
p_CurData,
h_CurrUserPriv))
{
p_FmPort->lock = FALSE;
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Failed freeing data buffer"));
}
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
}
p_FmPort->lock = FALSE;
return E_OK;
}
void FmPortConfigIM (t_FmPort *p_FmPort, t_FmPortParams *p_FmPortParams)
{
ASSERT_COND(p_FmPort);
SANITY_CHECK_RETURN(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.h_FmMuram = p_FmPortParams->specificParams.imRxTxParams.h_FmMuram;
p_FmPort->p_FmPortDriverParam->liodnOffset = p_FmPortParams->specificParams.imRxTxParams.liodnOffset;
p_FmPort->im.dataMemId = p_FmPortParams->specificParams.imRxTxParams.dataMemId;
p_FmPort->im.dataMemAttributes = p_FmPortParams->specificParams.imRxTxParams.dataMemAttributes;
p_FmPort->im.fwExtStructsMemId = DEFAULT_PORT_ImfwExtStructsMemId;
p_FmPort->im.fwExtStructsMemAttr = DEFAULT_PORT_ImfwExtStructsMemAttr;
if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) ||
(p_FmPort->portType == e_FM_PORT_TYPE_RX_10G))
{
p_FmPort->im.rxPool.h_BufferPool = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.h_BufferPool;
p_FmPort->im.rxPool.f_GetBuf = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_GetBuf;
p_FmPort->im.rxPool.f_PutBuf = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_PutBuf;
p_FmPort->im.rxPool.bufferSize = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.bufferSize;
p_FmPort->im.rxPool.f_PhysToVirt = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_PhysToVirt;
if (!p_FmPort->im.rxPool.f_PhysToVirt)
p_FmPort->im.rxPool.f_PhysToVirt = XX_PhysToVirt;
p_FmPort->im.rxPool.f_VirtToPhys = p_FmPortParams->specificParams.imRxTxParams.rxPoolParams.f_VirtToPhys;
if (!p_FmPort->im.rxPool.f_VirtToPhys)
p_FmPort->im.rxPool.f_VirtToPhys = XX_VirtToPhys;
p_FmPort->im.f_RxStore = p_FmPortParams->specificParams.imRxTxParams.f_RxStore;
p_FmPort->im.mrblr = 0x8000;
while (p_FmPort->im.mrblr)
{
if (p_FmPort->im.rxPool.bufferSize & p_FmPort->im.mrblr)
break;
p_FmPort->im.mrblr >>= 1;
}
if (p_FmPort->im.mrblr != p_FmPort->im.rxPool.bufferSize)
DBG(WARNING, ("Max-Rx-Buffer-Length set to %d", p_FmPort->im.mrblr));
p_FmPort->im.bdRingSize = DEFAULT_PORT_rxBdRingLength;
p_FmPort->exceptions = DEFAULT_exception;
if (FmIsMaster(p_FmPort->h_Fm))
p_FmPort->polling = FALSE;
else
p_FmPort->polling = TRUE;
p_FmPort->fmanCtrlEventId = (uint8_t)NO_IRQ;
}
else
{
p_FmPort->im.f_TxConf = p_FmPortParams->specificParams.imRxTxParams.f_TxConf;
p_FmPort->im.bdRingSize = DEFAULT_PORT_txBdRingLength;
}
}
t_Error FmPortImCheckInitParameters(t_FmPort *p_FmPort)
{
if ((p_FmPort->portType != e_FM_PORT_TYPE_RX) &&
(p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) &&
(p_FmPort->portType != e_FM_PORT_TYPE_TX) &&
(p_FmPort->portType != e_FM_PORT_TYPE_TX_10G))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, NO_MSG);
if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) ||
(p_FmPort->portType == e_FM_PORT_TYPE_RX_10G))
{
if (!POWER_OF_2(p_FmPort->im.mrblr))
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("max Rx buffer length must be power of 2!!!"));
if (p_FmPort->im.mrblr < 256)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("max Rx buffer length must at least 256!!!"));
if(p_FmPort->p_FmPortDriverParam->liodnOffset & ~FM_LIODN_OFFSET_MASK)
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("liodnOffset is larger than %d", FM_LIODN_OFFSET_MASK+1));
#ifdef FM_PARTITION_ARRAY
{
t_FmRevisionInfo revInfo;
FM_GetRevision(p_FmPort->h_Fm, &revInfo);
if ((revInfo.majorRev == 1) && (revInfo.minorRev == 0))
{
if(p_FmPort->p_FmPortDriverParam->liodnOffset >= MAX_LIODN_OFFSET)
{
p_FmPort->p_FmPortDriverParam->liodnOffset =
(uint16_t)(p_FmPort->p_FmPortDriverParam->liodnOffset & (MAX_LIODN_OFFSET-1));
DBG(WARNING, ("liodnOffset number is out of rev1 range - MSB bits cleard."));
}
}
}
#endif /* FM_PARTITION_ARRAY */
/* TODO - add checks */
}
else
{
/* TODO - add checks */
}
return E_OK;
}
t_Error FmPortImInit(t_FmPort *p_FmPort)
{
t_FmImBd *p_Bd=NULL;
t_Handle h_BufContext;
uint64_t tmpPhysBase;
uint16_t log2Num;
uint8_t *p_Data/*, *p_Tmp*/;
int i;
t_Error err;
uint16_t tmpReg16;
uint32_t tmpReg32;
ASSERT_COND(p_FmPort);
p_FmPort->im.p_FmPortImPram =
(t_FmPortImPram *)FM_MURAM_AllocMem(p_FmPort->im.h_FmMuram, sizeof(t_FmPortImPram), IM_PRAM_ALIGN);
if (!p_FmPort->im.p_FmPortImPram)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Parameter-RAM!!!"));
WRITE_BLOCK(p_FmPort->im.p_FmPortImPram, 0, sizeof(t_FmPortImPram));
if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) ||
(p_FmPort->portType == e_FM_PORT_TYPE_RX_10G))
{
p_FmPort->im.p_BdRing = (t_FmImBd *)XX_MallocSmart((uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize), p_FmPort->im.fwExtStructsMemId, 4);
if (!p_FmPort->im.p_BdRing)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD ring!!!"));
IOMemSet32(p_FmPort->im.p_BdRing, 0, (uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize));
p_FmPort->im.p_BdShadow = (t_Handle *)XX_Malloc((uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize));
if (!p_FmPort->im.p_BdShadow)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD shadow!!!"));
memset(p_FmPort->im.p_BdShadow, 0, (uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize));
/* Initialize the Rx-BD ring */
for (i=0; i<p_FmPort->im.bdRingSize; i++)
{
p_Bd = BD_GET(i);
BD_STATUS_AND_LENGTH_SET (p_Bd, BD_R_E);
if ((p_Data = p_FmPort->im.rxPool.f_GetBuf(p_FmPort->im.rxPool.h_BufferPool, &h_BufContext)) == NULL)
RETURN_ERROR(MAJOR, E_NOT_AVAILABLE, ("Data buffer"));
BdBufferSet(p_FmPort->im.rxPool.f_VirtToPhys, p_Bd, p_Data);
p_FmPort->im.p_BdShadow[i] = h_BufContext;
}
if ((p_FmPort->im.dataMemAttributes & MEMORY_ATTR_CACHEABLE) ||
(p_FmPort->im.fwExtStructsMemAttr & MEMORY_ATTR_CACHEABLE))
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_GBL | IM_MODE_SET_BO(2));
else
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_SET_BO(2));
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->rxQdPtr,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->p_FmPortDriverParam->fmMuramPhysBaseAddr + 0x20));
LOG2((uint64_t)p_FmPort->im.mrblr, log2Num);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->mrblr, log2Num);
/* Initialize Rx QD */
tmpPhysBase = (uint64_t)(XX_VirtToPhys(p_FmPort->im.p_BdRing));
SET_ADDR(&p_FmPort->im.p_FmPortImPram->rxQd.bdRingBase, tmpPhysBase);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.bdRingSize, (uint16_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize));
/* Update the IM PRAM address in the BMI */
WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->rxPortBmiRegs.fmbm_rfqid,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->p_FmPortDriverParam->fmMuramPhysBaseAddr));
if (!p_FmPort->polling || p_FmPort->exceptions)
{
/* Allocate, configure and register interrupts */
err = FmAllocFmanCtrlEventReg(p_FmPort->h_Fm, &p_FmPort->fmanCtrlEventId);
if(err)
RETURN_ERROR(MAJOR, err, NO_MSG);
ASSERT_COND(!(p_FmPort->fmanCtrlEventId & ~IM_RXQD_FPMEVT_SEL_MASK));
tmpReg16 = (uint16_t)(p_FmPort->fmanCtrlEventId & IM_RXQD_FPMEVT_SEL_MASK);
tmpReg32 = 0;
if(p_FmPort->exceptions & IM_EV_BSY)
{
tmpReg16 |= IM_RXQD_BSYINTM;
tmpReg32 |= IM_EV_BSY;
}
if(!p_FmPort->polling)
{
tmpReg16 |= IM_RXQD_RXFINTM;
tmpReg32 |= IM_EV_RX;
}
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, tmpReg16);
FmRegisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, ImException , (t_Handle)p_FmPort);
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, tmpReg32);
}
else
p_FmPort->fmanCtrlEventId = (uint8_t)NO_IRQ;
}
else
{
p_FmPort->im.p_BdRing = (t_FmImBd *)XX_MallocSmart((uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize), p_FmPort->im.fwExtStructsMemId, 4);
if (!p_FmPort->im.p_BdRing)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Tx BD ring!!!"));
IOMemSet32(p_FmPort->im.p_BdRing, 0, (uint32_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize));
p_FmPort->im.p_BdShadow = (t_Handle *)XX_Malloc((uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize));
if (!p_FmPort->im.p_BdShadow)
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Independent-Mode Rx BD shadow!!!"));
memset(p_FmPort->im.p_BdShadow, 0, (uint32_t)(sizeof(t_Handle)*p_FmPort->im.bdRingSize));
p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID;
if ((p_FmPort->im.dataMemAttributes & MEMORY_ATTR_CACHEABLE) ||
(p_FmPort->im.fwExtStructsMemAttr & MEMORY_ATTR_CACHEABLE))
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_GBL | IM_MODE_SET_BO(2));
else
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->mode, IM_MODE_SET_BO(2));
WRITE_UINT32(p_FmPort->im.p_FmPortImPram->txQdPtr,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->p_FmPortDriverParam->fmMuramPhysBaseAddr + 0x40));
/* Initialize Tx QD */
tmpPhysBase = (uint64_t)(XX_VirtToPhys(p_FmPort->im.p_BdRing));
SET_ADDR(&p_FmPort->im.p_FmPortImPram->txQd.bdRingBase, tmpPhysBase);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->txQd.bdRingSize, (uint16_t)(sizeof(t_FmImBd)*p_FmPort->im.bdRingSize));
/* Update the IM PRAM address in the BMI */
WRITE_UINT32(p_FmPort->p_FmPortBmiRegs->txPortBmiRegs.fmbm_tcfqid,
(uint32_t)((uint64_t)(XX_VirtToPhys(p_FmPort->im.p_FmPortImPram)) -
p_FmPort->p_FmPortDriverParam->fmMuramPhysBaseAddr));
}
return E_OK;
}
void FmPortImFree(t_FmPort *p_FmPort)
{
uint32_t bdStatus;
uint8_t *p_CurData;
ASSERT_COND(p_FmPort);
ASSERT_COND(p_FmPort->im.p_FmPortImPram);
if ((p_FmPort->portType == e_FM_PORT_TYPE_RX) ||
(p_FmPort->portType == e_FM_PORT_TYPE_RX_10G))
{
if (!p_FmPort->polling || p_FmPort->exceptions)
{
/* Deallocate and unregister interrupts */
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, 0);
FmFreeFmanCtrlEventReg(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, 0);
FmUnregisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId);
}
/* Try first clean what has received */
FmPortImRx(p_FmPort);
/* Now, get rid of the the empty buffer! */
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
while (bdStatus & BD_R_E) /* while there is data in the Rx BD */
{
p_CurData = BdBufferGet(p_FmPort->im.rxPool.f_PhysToVirt, BD_GET(p_FmPort->im.currBdId));
BdBufferSet(p_FmPort->im.rxPool.f_VirtToPhys, BD_GET(p_FmPort->im.currBdId), NULL);
BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.currBdId), 0);
p_FmPort->im.rxPool.f_PutBuf(p_FmPort->im.rxPool.h_BufferPool,
p_CurData,
p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId]);
p_FmPort->im.currBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId);
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
}
}
else
TxConf(p_FmPort, e_TX_CONF_TYPE_FLUSH);
FM_MURAM_FreeMem(p_FmPort->im.h_FmMuram, p_FmPort->im.p_FmPortImPram);
if (p_FmPort->im.p_BdShadow)
XX_Free(p_FmPort->im.p_BdShadow);
if (p_FmPort->im.p_BdRing)
XX_FreeSmart(p_FmPort->im.p_BdRing);
}
t_Error FM_PORT_ConfigIMMaxRxBufLength(t_Handle h_FmPort, uint16_t newVal)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.mrblr = newVal;
return E_OK;
}
t_Error FM_PORT_ConfigIMRxBdRingLength(t_Handle h_FmPort, uint16_t newVal)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.bdRingSize = newVal;
return E_OK;
}
t_Error FM_PORT_ConfigIMTxBdRingLength(t_Handle h_FmPort, uint16_t newVal)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.bdRingSize = newVal;
return E_OK;
}
t_Error FM_PORT_ConfigIMFmanCtrlExternalStructsMemory(t_Handle h_FmPort,
uint8_t memId,
uint32_t memAttributes)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
p_FmPort->im.fwExtStructsMemId = memId;
p_FmPort->im.fwExtStructsMemAttr = memAttributes;
return E_OK;
}
t_Error FM_PORT_ConfigIMPolling(t_Handle h_FmPort)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
if((p_FmPort->portType != e_FM_PORT_TYPE_RX_10G) && (p_FmPort->portType != e_FM_PORT_TYPE_RX))
RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("Available for Rx ports only"));
if (!FmIsMaster(p_FmPort->h_Fm))
RETURN_ERROR(MAJOR, E_INVALID_OPERATION, ("Available on master-partition only;"
"in guest-partitions, IM is always in polling!"));
p_FmPort->polling = TRUE;
return E_OK;
}
t_Error FM_PORT_SetIMExceptions(t_Handle h_FmPort, e_FmPortExceptions exception, bool enable)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
t_Error err;
uint16_t tmpReg16;
uint32_t tmpReg32;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
if(exception == e_FM_PORT_EXCEPTION_IM_BUSY)
{
if(enable)
{
p_FmPort->exceptions |= IM_EV_BSY;
if(p_FmPort->fmanCtrlEventId == (uint8_t)NO_IRQ)
{
/* Allocate, configure and register interrupts */
err = FmAllocFmanCtrlEventReg(p_FmPort->h_Fm, &p_FmPort->fmanCtrlEventId);
if(err)
RETURN_ERROR(MAJOR, err, NO_MSG);
ASSERT_COND(!(p_FmPort->fmanCtrlEventId & ~IM_RXQD_FPMEVT_SEL_MASK));
FmRegisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, ImException, (t_Handle)p_FmPort);
tmpReg16 = (uint16_t)((p_FmPort->fmanCtrlEventId & IM_RXQD_FPMEVT_SEL_MASK) | IM_RXQD_BSYINTM);
tmpReg32 = IM_EV_BSY;
}
else
{
tmpReg16 = (uint16_t)(GET_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen) | IM_RXQD_BSYINTM);
tmpReg32 = FmGetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId) | IM_EV_BSY;
}
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, tmpReg16);
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, tmpReg32);
}
else
{
p_FmPort->exceptions &= ~IM_EV_BSY;
if (!p_FmPort->exceptions && p_FmPort->polling)
{
FmFreeFmanCtrlEventReg(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId);
FmUnregisterFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId);
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, 0);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, 0);
p_FmPort->fmanCtrlEventId = (uint8_t)NO_IRQ;
}
else
{
tmpReg16 = (uint16_t)(GET_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen) & ~IM_RXQD_BSYINTM);
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->rxQd.gen, tmpReg16);
tmpReg32 = FmGetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId) & ~IM_EV_BSY;
FmSetFmanCtrlIntr(p_FmPort->h_Fm, p_FmPort->fmanCtrlEventId, tmpReg32);
}
}
}
else
RETURN_ERROR(MINOR, E_INVALID_SELECTION, ("Invalid exception."));
return E_OK;
}
t_Error FM_PORT_ImTx( t_Handle h_FmPort,
uint8_t *p_Data,
uint16_t length,
bool lastBuffer,
t_Handle h_BufContext)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
uint16_t nextBdId;
uint32_t bdStatus, nextBdStatus;
bool firstBuffer;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
bdStatus = BD_STATUS_AND_LENGTH(BD_GET(p_FmPort->im.currBdId));
nextBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId);
nextBdStatus = BD_STATUS_AND_LENGTH(BD_GET(nextBdId));
if (!(bdStatus & BD_R_E) && !(nextBdStatus & BD_R_E))
{
/* Confirm the current BD - BD is available */
if ((bdStatus & BD_LENGTH_MASK) && (p_FmPort->im.f_TxConf))
p_FmPort->im.f_TxConf (p_FmPort->h_App,
BdBufferGet(XX_PhysToVirt, BD_GET(p_FmPort->im.currBdId)),
0,
p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId]);
bdStatus = length;
/* if this is the first BD of a frame */
if (p_FmPort->im.firstBdOfFrameId == IM_ILEGAL_BD_ID)
{
firstBuffer = TRUE;
p_FmPort->im.txFirstBdStatus = (bdStatus | BD_R_E);
if (!lastBuffer)
p_FmPort->im.firstBdOfFrameId = p_FmPort->im.currBdId;
}
else
firstBuffer = FALSE;
BdBufferSet(XX_VirtToPhys, BD_GET(p_FmPort->im.currBdId), p_Data);
p_FmPort->im.p_BdShadow[p_FmPort->im.currBdId] = h_BufContext;
/* deal with last */
if (lastBuffer)
{
/* if single buffer frame */
if (firstBuffer)
BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.currBdId), p_FmPort->im.txFirstBdStatus | BD_L);
else
{
/* Set the last BD of the frame */
BD_STATUS_AND_LENGTH_SET (BD_GET(p_FmPort->im.currBdId), (bdStatus | BD_R_E | BD_L));
/* Set the first BD of the frame */
BD_STATUS_AND_LENGTH_SET(BD_GET(p_FmPort->im.firstBdOfFrameId), p_FmPort->im.txFirstBdStatus);
p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID;
}
WRITE_UINT16(p_FmPort->im.p_FmPortImPram->txQd.offsetIn, (uint16_t)(GetNextBdId(p_FmPort, p_FmPort->im.currBdId)<<4));
}
else if (!firstBuffer) /* mid frame buffer */
BD_STATUS_AND_LENGTH_SET (BD_GET(p_FmPort->im.currBdId), bdStatus | BD_R_E);
p_FmPort->im.currBdId = GetNextBdId(p_FmPort, p_FmPort->im.currBdId);
}
else
{
/* Discard current frame. Return error. */
if (p_FmPort->im.firstBdOfFrameId != IM_ILEGAL_BD_ID)
{
/* Error: No free BD */
/* Response: Discard current frame. Return error. */
uint16_t cleanBdId = p_FmPort->im.firstBdOfFrameId;
ASSERT_COND(p_FmPort->im.firstBdOfFrameId != p_FmPort->im.currBdId);
/* Since firstInFrame is not NULL, one buffer at least has already been
inserted into the BD ring. Using do-while covers the situation of a
frame spanned throughout the whole Tx BD ring (p_CleanBd is incremented
prior to testing whether or not it's equal to TxBd). */
do
{
BD_STATUS_AND_LENGTH_SET(BD_GET(cleanBdId), 0);
/* Advance BD pointer */
cleanBdId = GetNextBdId(p_FmPort, cleanBdId);
} while (cleanBdId != p_FmPort->im.currBdId);
p_FmPort->im.currBdId = cleanBdId;
p_FmPort->im.firstBdOfFrameId = IM_ILEGAL_BD_ID;
}
return ERROR_CODE(E_FULL);
}
return E_OK;
}
void FM_PORT_ImTxConf(t_Handle h_FmPort)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
TxConf(p_FmPort, e_TX_CONF_TYPE_CALLBACK);
}
t_Error FM_PORT_ImRx(t_Handle h_FmPort)
{
t_FmPort *p_FmPort = (t_FmPort*)h_FmPort;
SANITY_CHECK_RETURN_ERROR(p_FmPort, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmPort->imEn, E_INVALID_STATE);
SANITY_CHECK_RETURN_ERROR(!p_FmPort->p_FmPortDriverParam, E_INVALID_HANDLE);
return FmPortImRx(p_FmPort);
}

891
sys/contrib/ncsw/Peripherals/FM/Rtc/fm_rtc.c Normal file
View File

@ -0,0 +1,891 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_rtc.c
@Description FM RTC driver implementation.
@Cautions None
*//***************************************************************************/
#include "error_ext.h"
#include "debug_ext.h"
#include "string_ext.h"
#include "part_ext.h"
#include "xx_ext.h"
#include "ncsw_ext.h"
#include "fm_rtc.h"
#include "fm_common.h"
/*****************************************************************************/
static void SetDefaultParam(t_FmRtc *p_Rtc)
{
t_FmRtcDriverParam *p_RtcDriverParam = p_Rtc->p_RtcDriverParam;
int i;
p_Rtc->outputClockDivisor = DEFAULT_outputClockDivisor;
p_Rtc->p_RtcDriverParam->bypass = DEFAULT_bypass;
p_RtcDriverParam->srcClk = DEFAULT_srcClock;
p_RtcDriverParam->invertInputClkPhase = DEFAULT_invertInputClkPhase;
p_RtcDriverParam->invertOutputClkPhase = DEFAULT_invertOutputClkPhase;
p_RtcDriverParam->pulseRealign = DEFAULT_pulseRealign;
for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++)
{
p_RtcDriverParam->alarmPolarity[i] = DEFAULT_alarmPolarity;
}
for (i=0; i < FM_RTC_NUM_OF_EXT_TRIGGERS; i++)
{
p_RtcDriverParam->triggerPolarity[i] = DEFAULT_triggerPolarity;
}
p_Rtc->clockPeriodNanoSec = DEFAULT_clockPeriod; /* 1 usec */
}
/*****************************************************************************/
static t_Error CheckInitParameters(t_FmRtc *p_Rtc)
{
t_FmRtcDriverParam *p_RtcDriverParam = p_Rtc->p_RtcDriverParam;
int i;
if ((p_RtcDriverParam->srcClk != e_FM_RTC_SOURCE_CLOCK_EXTERNAL) &&
(p_RtcDriverParam->srcClk != e_FM_RTC_SOURCE_CLOCK_SYSTEM) &&
(p_RtcDriverParam->srcClk != e_FM_RTC_SOURCE_CLOCK_OSCILATOR))
RETURN_ERROR(MAJOR, E_INVALID_CLOCK, ("Source clock undefined"));
if (p_Rtc->outputClockDivisor == 0)
{
RETURN_ERROR(MAJOR, E_INVALID_VALUE,
("Divisor for output clock (should be positive)"));
}
for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++)
{
if ((p_RtcDriverParam->alarmPolarity[i] != e_FM_RTC_ALARM_POLARITY_ACTIVE_LOW) &&
(p_RtcDriverParam->alarmPolarity[i] != e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH))
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm %d signal polarity", i));
}
}
for (i=0; i < FM_RTC_NUM_OF_EXT_TRIGGERS; i++)
{
if ((p_RtcDriverParam->triggerPolarity[i] != e_FM_RTC_TRIGGER_ON_FALLING_EDGE) &&
(p_RtcDriverParam->triggerPolarity[i] != e_FM_RTC_TRIGGER_ON_RISING_EDGE))
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Trigger %d signal polarity", i));
}
}
#ifdef FM_1588_SRC_CLK_ERRATA_FMAN1
{
t_FmRevisionInfo revInfo;
FM_GetRevision(p_Rtc->h_Fm, &revInfo);
if ((revInfo.majorRev == 1) && (revInfo.minorRev == 0)&&
((p_RtcDriverParam->srcClk==e_FM_RTC_SOURCE_CLOCK_SYSTEM) && p_RtcDriverParam->invertInputClkPhase))
RETURN_ERROR(MAJOR, E_NOT_SUPPORTED, ("Can not use invertInputClkPhase when source clock is e_FM_RTC_SOURCE_CLOCK_SYSTEM"));
}
#endif /* FM_1588_SRC_CLK_ERRATA_FMAN1 */
return E_OK;
}
/*****************************************************************************/
static void RtcExceptions(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcMemMap *p_MemMap;
register uint32_t events;
ASSERT_COND(p_Rtc);
p_MemMap = p_Rtc->p_MemMap;
/* Get valid events */
events = GET_UINT32(p_MemMap->tmr_tevent);
events &= GET_UINT32(p_MemMap->tmr_temask);
/* Clear event bits */
WRITE_UINT32(p_MemMap->tmr_tevent, events);
if (events & TMR_TEVENT_ALM1)
{
if(p_Rtc->alarmParams[0].clearOnExpiration)
{
WRITE_UINT32(p_MemMap->tmr_alarm[0].tmr_alarm_l, 0);
WRITE_UINT32(p_MemMap->tmr_temask, GET_UINT32(p_MemMap->tmr_temask) & ~TMR_TEVENT_ALM1);
}
ASSERT_COND(p_Rtc->alarmParams[0].f_AlarmCallback);
p_Rtc->alarmParams[0].f_AlarmCallback(p_Rtc->h_App, 0);
}
if (events & TMR_TEVENT_ALM2)
{
if(p_Rtc->alarmParams[1].clearOnExpiration)
{
WRITE_UINT32(p_MemMap->tmr_alarm[1].tmr_alarm_l, 0);
WRITE_UINT32(p_MemMap->tmr_temask, GET_UINT32(p_MemMap->tmr_temask) & ~TMR_TEVENT_ALM2);
}
ASSERT_COND(p_Rtc->alarmParams[1].f_AlarmCallback);
p_Rtc->alarmParams[1].f_AlarmCallback(p_Rtc->h_App, 1);
}
if (events & TMR_TEVENT_PP1)
{
ASSERT_COND(p_Rtc->periodicPulseParams[0].f_PeriodicPulseCallback);
p_Rtc->periodicPulseParams[0].f_PeriodicPulseCallback(p_Rtc->h_App, 0);
}
if (events & TMR_TEVENT_PP2)
{
ASSERT_COND(p_Rtc->periodicPulseParams[1].f_PeriodicPulseCallback);
p_Rtc->periodicPulseParams[1].f_PeriodicPulseCallback(p_Rtc->h_App, 1);
}
if (events & TMR_TEVENT_ETS1)
{
ASSERT_COND(p_Rtc->externalTriggerParams[0].f_ExternalTriggerCallback);
p_Rtc->externalTriggerParams[0].f_ExternalTriggerCallback(p_Rtc->h_App, 0);
}
if (events & TMR_TEVENT_ETS2)
{
ASSERT_COND(p_Rtc->externalTriggerParams[1].f_ExternalTriggerCallback);
p_Rtc->externalTriggerParams[1].f_ExternalTriggerCallback(p_Rtc->h_App, 1);
}
}
/*****************************************************************************/
t_Handle FM_RTC_Config(t_FmRtcParams *p_FmRtcParam)
{
t_FmRtc *p_Rtc;
SANITY_CHECK_RETURN_VALUE(p_FmRtcParam, E_NULL_POINTER, NULL);
/* Allocate memory for the FM RTC driver parameters */
p_Rtc = (t_FmRtc *)XX_Malloc(sizeof(t_FmRtc));
if (!p_Rtc)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM RTC driver structure"));
return NULL;
}
memset(p_Rtc, 0, sizeof(t_FmRtc));
/* Allocate memory for the FM RTC driver parameters */
p_Rtc->p_RtcDriverParam = (t_FmRtcDriverParam *)XX_Malloc(sizeof(t_FmRtcDriverParam));
if (!p_Rtc->p_RtcDriverParam)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM RTC driver parameters"));
XX_Free(p_Rtc);
return NULL;
}
memset(p_Rtc->p_RtcDriverParam, 0, sizeof(t_FmRtcDriverParam));
/* Store RTC configuration parameters */
p_Rtc->h_Fm = p_FmRtcParam->h_Fm;
/* Set default RTC configuration parameters */
SetDefaultParam(p_Rtc);
/* Store RTC parameters in the RTC control structure */
p_Rtc->p_MemMap = (t_FmRtcMemMap *)UINT_TO_PTR(p_FmRtcParam->baseAddress);
p_Rtc->h_App = p_FmRtcParam->h_App;
return p_Rtc;
}
/*****************************************************************************/
t_Error FM_RTC_Init(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcDriverParam *p_RtcDriverParam;
t_FmRtcMemMap *p_MemMap;
uint32_t freqCompensation;
uint32_t tmrCtrl;
int i;
uint64_t tmpDouble;
p_RtcDriverParam = p_Rtc->p_RtcDriverParam;
p_MemMap = p_Rtc->p_MemMap;
if(CheckInitParameters(p_Rtc)!=E_OK)
RETURN_ERROR(MAJOR, E_CONFLICT,
("Init Parameters are not Valid"));
/* TODO A check must be added here, that no timestamping MAC's
* are working in this stage. */
WRITE_UINT32(p_MemMap->tmr_ctrl, TMR_CTRL_TMSR);
XX_UDelay(10);
WRITE_UINT32(p_MemMap->tmr_ctrl, 0);
/* Set the source clock */
switch (p_RtcDriverParam->srcClk)
{
case e_FM_RTC_SOURCE_CLOCK_SYSTEM:
tmrCtrl = TMR_CTRL_CKSEL_MAC_CLK;
break;
case e_FM_RTC_SOURCE_CLOCK_OSCILATOR:
tmrCtrl = TMR_CTRL_CKSEL_OSC_CLK;
break;
default:
/* Use a clock from the External TMR reference clock.*/
tmrCtrl = TMR_CTRL_CKSEL_EXT_CLK;
break;
}
/* whatever period the user picked, the timestamp will advance in '1' every time
* the period passed. */
tmrCtrl |= ((1 << TMR_CTRL_TCLK_PERIOD_SHIFT) & TMR_CTRL_TCLK_PERIOD_MASK);
if (p_RtcDriverParam->invertInputClkPhase)
tmrCtrl |= TMR_CTRL_CIPH;
if (p_RtcDriverParam->invertOutputClkPhase)
tmrCtrl |= TMR_CTRL_COPH;
for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++)
{
if (p_RtcDriverParam->alarmPolarity[i] == e_FM_RTC_ALARM_POLARITY_ACTIVE_LOW)
tmrCtrl |= (TMR_CTRL_ALMP1 >> i);
}
for (i=0; i < FM_RTC_NUM_OF_EXT_TRIGGERS; i++)
if (p_RtcDriverParam->triggerPolarity[i] == e_FM_RTC_TRIGGER_ON_FALLING_EDGE)
tmrCtrl |= (TMR_CTRL_ETEP1 << i);
if (!p_RtcDriverParam->timerSlaveMode && p_Rtc->p_RtcDriverParam->bypass)
tmrCtrl |= TMR_CTRL_BYP;
WRITE_UINT32(p_MemMap->tmr_ctrl, tmrCtrl);
for (i=0; i < FM_RTC_NUM_OF_ALARMS; i++)
{
/* Clear TMR_ALARM registers */
WRITE_UINT32(p_MemMap->tmr_alarm[i].tmr_alarm_l, 0xFFFFFFFF);
WRITE_UINT32(p_MemMap->tmr_alarm[i].tmr_alarm_h, 0xFFFFFFFF);
}
/* Clear TMR_TEVENT */
WRITE_UINT32(p_MemMap->tmr_tevent, TMR_TEVENT_ALL);
/* Initialize TMR_TEMASK */
WRITE_UINT32(p_MemMap->tmr_temask, 0);
/* find source clock frequency in Mhz */
if (p_Rtc->p_RtcDriverParam->srcClk != e_FM_RTC_SOURCE_CLOCK_SYSTEM)
p_Rtc->srcClkFreqMhz = p_Rtc->p_RtcDriverParam->extSrcClkFreq;
else
p_Rtc->srcClkFreqMhz = (uint32_t)(FmGetClockFreq(p_Rtc->h_Fm)/2);
/* if timer in Master mode Initialize TMR_CTRL */
/* We want the counter (TMR_CNT) to count in nano-seconds */
if (!p_RtcDriverParam->timerSlaveMode && p_Rtc->p_RtcDriverParam->bypass)
{
p_Rtc->clockPeriodNanoSec = (1000 / p_Rtc->srcClkFreqMhz);
}
else
{
/* Initialize TMR_ADD with the initial frequency compensation value:
freqCompensation = (2^32 / frequency ratio) */
/* frequency ratio = sorce clock/rtc clock =
* (p_Rtc->srcClkFreqMhz*1000000))/ 1/(p_Rtc->clockPeriodNanoSec * 1000000000) */
freqCompensation = (uint32_t)DIV_CEIL(ACCUMULATOR_OVERFLOW * 1000,
p_Rtc->clockPeriodNanoSec * p_Rtc->srcClkFreqMhz);
WRITE_UINT32(p_MemMap->tmr_add, freqCompensation);
}
/* check the legality of the relation between source and destination clocks */
/* should be larger than 1.0001 */
tmpDouble = 10000 * (uint64_t)p_Rtc->clockPeriodNanoSec * (uint64_t)p_Rtc->srcClkFreqMhz;
if((tmpDouble) <= 10001)
RETURN_ERROR(MAJOR, E_CONFLICT,
("Invalid relation between source and destination clocks. Should be larger than 1.0001"));
for (i=0; i < 2; i++)
/* Clear TMR_FIPER registers */
WRITE_UINT32(p_MemMap->tmr_fiper[i], 0xFFFFFFFF);
/* Initialize TMR_PRSC */
WRITE_UINT32(p_MemMap->tmr_prsc, p_Rtc->outputClockDivisor);
/* Clear TMR_OFF */
WRITE_UINT32(p_MemMap->tmr_off_l, 0);
WRITE_UINT32(p_MemMap->tmr_off_h, 0);
/* Register the FM RTC interrupt */
FmRegisterIntr(p_Rtc->h_Fm, e_FM_MOD_TMR, 0, e_FM_INTR_TYPE_NORMAL, RtcExceptions , p_Rtc);
/* Free parameters structures */
XX_Free(p_Rtc->p_RtcDriverParam);
p_Rtc->p_RtcDriverParam = NULL;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_Free(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
if (p_Rtc->p_RtcDriverParam)
{
XX_Free(p_Rtc->p_RtcDriverParam);
}
else
{
FM_RTC_Disable(h_FmRtc);
}
/* Unregister FM RTC interrupt */
FmUnregisterIntr(p_Rtc->h_Fm, e_FM_MOD_TMR, 0, e_FM_INTR_TYPE_NORMAL);
XX_Free(p_Rtc);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigSourceClock(t_Handle h_FmRtc,
e_FmSrcClk srcClk,
uint32_t freqInMhz)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->srcClk = srcClk;
if(srcClk != e_FM_RTC_SOURCE_CLOCK_SYSTEM)
p_Rtc->p_RtcDriverParam->extSrcClkFreq = freqInMhz;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigPeriod(t_Handle h_FmRtc, uint32_t period)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->clockPeriodNanoSec = period;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigFrequencyBypass(t_Handle h_FmRtc, bool enabled)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->bypass = enabled;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigInvertedInputClockPhase(t_Handle h_FmRtc, bool inverted)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->invertInputClkPhase = inverted;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigInvertedOutputClockPhase(t_Handle h_FmRtc, bool inverted)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->invertOutputClkPhase = inverted;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigOutputClockDivisor(t_Handle h_FmRtc, uint16_t divisor)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->outputClockDivisor = divisor;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigPulseRealignment(t_Handle h_FmRtc, bool enable)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_Rtc->p_RtcDriverParam->pulseRealign = enable;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigAlarmPolarity(t_Handle h_FmRtc,
uint8_t alarmId,
e_FmRtcAlarmPolarity alarmPolarity)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (alarmId >= FM_RTC_NUM_OF_ALARMS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm ID"));
}
p_Rtc->p_RtcDriverParam->alarmPolarity[alarmId] = alarmPolarity;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ConfigExternalTriggerPolarity(t_Handle h_FmRtc,
uint8_t triggerId,
e_FmRtcTriggerPolarity triggerPolarity)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (triggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External trigger ID"));
}
p_Rtc->p_RtcDriverParam->triggerPolarity[triggerId] = triggerPolarity;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_Enable(t_Handle h_FmRtc, bool resetClock)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmrCtrl;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
tmrCtrl = GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl);
/* TODO A check must be added here, that no timestamping MAC's
* are working in this stage. */
if (resetClock)
{
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, (tmrCtrl | TMR_CTRL_TMSR));
XX_UDelay(10);
/* Clear TMR_OFF */
WRITE_UINT32(p_Rtc->p_MemMap->tmr_off_l, 0);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_off_h, 0);
}
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, (tmrCtrl | TMR_CTRL_TE));
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_Disable(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmrCtrl;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* TODO A check must be added here, that no timestamping MAC's
* are working in this stage. */
tmrCtrl = GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, (tmrCtrl & ~(TMR_CTRL_TE)));
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetClockOffset(t_Handle h_FmRtc, int64_t offset)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* TMR_OFF_L must be written first */
WRITE_UINT32(p_Rtc->p_MemMap->tmr_off_l, (uint32_t)offset);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_off_h, (uint32_t)(offset >> 32));
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc, t_FmRtcAlarmParams *p_FmRtcAlarmParams)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcMemMap *p_MemMap;
uint32_t tmpReg;
uint64_t tmpAlarm;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_MemMap = p_Rtc->p_MemMap;
if (p_FmRtcAlarmParams->alarmId >= FM_RTC_NUM_OF_ALARMS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm ID"));
}
if(p_FmRtcAlarmParams->alarmTime < p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm time must be equal or larger than RTC period - %d nanoseconds", p_Rtc->clockPeriodNanoSec));
if(p_FmRtcAlarmParams->alarmTime % (uint64_t)p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Alarm time must be a multiple of RTC period - %d nanoseconds", p_Rtc->clockPeriodNanoSec));
tmpAlarm = p_FmRtcAlarmParams->alarmTime/(uint64_t)p_Rtc->clockPeriodNanoSec;
/* TMR_ALARM_L must be written first */
WRITE_UINT32(p_MemMap->tmr_alarm[p_FmRtcAlarmParams->alarmId].tmr_alarm_l, (uint32_t)tmpAlarm);
WRITE_UINT32(p_MemMap->tmr_alarm[p_FmRtcAlarmParams->alarmId].tmr_alarm_h,
(uint32_t)(tmpAlarm >> 32));
if (p_FmRtcAlarmParams->f_AlarmCallback)
{
p_Rtc->alarmParams[p_FmRtcAlarmParams->alarmId].f_AlarmCallback = p_FmRtcAlarmParams->f_AlarmCallback;
p_Rtc->alarmParams[p_FmRtcAlarmParams->alarmId].clearOnExpiration = p_FmRtcAlarmParams->clearOnExpiration;
if(p_FmRtcAlarmParams->alarmId == 0)
tmpReg = TMR_TEVENT_ALM1;
else
tmpReg = TMR_TEVENT_ALM2;
WRITE_UINT32(p_MemMap->tmr_temask, GET_UINT32(p_MemMap->tmr_temask) | tmpReg);
}
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetPeriodicPulse(t_Handle h_FmRtc, t_FmRtcPeriodicPulseParams *p_FmRtcPeriodicPulseParams)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcMemMap *p_MemMap;
uint32_t tmpReg;
uint64_t tmpFiper;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
p_MemMap = p_Rtc->p_MemMap;
if (p_FmRtcPeriodicPulseParams->periodicPulseId >= FM_RTC_NUM_OF_PERIODIC_PULSES)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse ID"));
}
if(GET_UINT32(p_MemMap->tmr_ctrl) & TMR_CTRL_TE)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Can't set Periodic pulse when RTC is enabled."));
if(p_FmRtcPeriodicPulseParams->periodicPulsePeriod < p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse must be equal or larger than RTC period - %d nanoseconds", p_Rtc->clockPeriodNanoSec));
if(p_FmRtcPeriodicPulseParams->periodicPulsePeriod % (uint64_t)p_Rtc->clockPeriodNanoSec)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse must be a multiple of RTC period - %d nanoseconds", p_Rtc->clockPeriodNanoSec));
tmpFiper = p_FmRtcPeriodicPulseParams->periodicPulsePeriod/(uint64_t)p_Rtc->clockPeriodNanoSec;
if(tmpFiper & 0xffffffff00000000LL)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse/RTC Period must be smaller than 4294967296", p_Rtc->clockPeriodNanoSec));
WRITE_UINT32(p_MemMap->tmr_fiper[p_FmRtcPeriodicPulseParams->periodicPulseId], (uint32_t)tmpFiper);
if (p_FmRtcPeriodicPulseParams->f_PeriodicPulseCallback)
{
p_Rtc->periodicPulseParams[p_FmRtcPeriodicPulseParams->periodicPulseId].f_PeriodicPulseCallback =
p_FmRtcPeriodicPulseParams->f_PeriodicPulseCallback;
if(p_FmRtcPeriodicPulseParams->periodicPulseId == 0)
tmpReg = TMR_TEVENT_PP1;
else
tmpReg = TMR_TEVENT_PP2;
WRITE_UINT32(p_MemMap->tmr_temask, GET_UINT32(p_MemMap->tmr_temask) | tmpReg);
}
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ClearPeriodicPulse(t_Handle h_FmRtc, uint8_t periodicPulseId)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmpReg;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (periodicPulseId >= FM_RTC_NUM_OF_PERIODIC_PULSES)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("Periodic pulse ID"));
}
p_Rtc->periodicPulseParams[periodicPulseId].f_PeriodicPulseCallback = NULL;
if(periodicPulseId == 0)
tmpReg = TMR_TEVENT_PP1;
else
tmpReg = TMR_TEVENT_PP2;
WRITE_UINT32(p_Rtc->p_MemMap->tmr_temask, GET_UINT32(p_Rtc->p_MemMap->tmr_temask) & ~tmpReg);
if (GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) & TMR_CTRL_FS)
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) & ~TMR_CTRL_FS);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_fiper[periodicPulseId], 0xFFFFFFFF);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetExternalTrigger(t_Handle h_FmRtc, t_FmRtcExternalTriggerParams *p_FmRtcExternalTriggerParams)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmpReg;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (p_FmRtcExternalTriggerParams->externalTriggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External Trigger ID"));
}
if (p_FmRtcExternalTriggerParams->f_ExternalTriggerCallback)
{
p_Rtc->externalTriggerParams[p_FmRtcExternalTriggerParams->externalTriggerId].f_ExternalTriggerCallback = p_FmRtcExternalTriggerParams->f_ExternalTriggerCallback;
if(p_FmRtcExternalTriggerParams->externalTriggerId == 0)
tmpReg = TMR_TEVENT_ETS1;
else
tmpReg = TMR_TEVENT_ETS2;
WRITE_UINT32(p_Rtc->p_MemMap->tmr_temask, GET_UINT32(p_Rtc->p_MemMap->tmr_temask) | tmpReg);
}
if(p_FmRtcExternalTriggerParams->usePulseAsInput)
{
if(p_FmRtcExternalTriggerParams->externalTriggerId == 0)
tmpReg = TMR_CTRL_PP1L;
else
tmpReg = TMR_CTRL_PP2L;
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) | tmpReg);
}
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_ClearExternalTrigger(t_Handle h_FmRtc, uint8_t externalTriggerId)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint32_t tmpReg;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (externalTriggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS)
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External Trigger ID"));
p_Rtc->externalTriggerParams[externalTriggerId].f_ExternalTriggerCallback = NULL;
if(externalTriggerId == 0)
tmpReg = TMR_TEVENT_ETS1;
else
tmpReg = TMR_TEVENT_ETS2;
WRITE_UINT32(p_Rtc->p_MemMap->tmr_temask, GET_UINT32(p_Rtc->p_MemMap->tmr_temask) & ~tmpReg);
if(externalTriggerId == 0)
tmpReg = TMR_CTRL_PP1L;
else
tmpReg = TMR_CTRL_PP2L;
if (GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) & tmpReg)
WRITE_UINT32(p_Rtc->p_MemMap->tmr_ctrl, GET_UINT32(p_Rtc->p_MemMap->tmr_ctrl) & ~tmpReg);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_GetExternalTriggerTimeStamp(t_Handle h_FmRtc,
uint8_t triggerId,
uint64_t *p_TimeStamp)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint64_t timeStamp;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
if (triggerId >= FM_RTC_NUM_OF_EXT_TRIGGERS)
{
RETURN_ERROR(MAJOR, E_INVALID_SELECTION, ("External trigger ID"));
}
timeStamp = (uint64_t)GET_UINT32(p_Rtc->p_MemMap->tmr_etts[triggerId].tmr_etts_l);
timeStamp |= ((uint64_t)GET_UINT32(p_Rtc->p_MemMap->tmr_etts[triggerId].tmr_etts_h) << 32);
timeStamp = timeStamp*p_Rtc->clockPeriodNanoSec;
*p_TimeStamp = timeStamp;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_GetCurrentTime(t_Handle h_FmRtc, uint64_t *p_Ts)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
uint64_t time;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* TMR_CNT_L must be read first to get an accurate value */
time = (uint64_t)GET_UINT32(p_Rtc->p_MemMap->tmr_cnt_l);
time |= ((uint64_t)GET_UINT32(p_Rtc->p_MemMap->tmr_cnt_h) << 32);
time = time*p_Rtc->clockPeriodNanoSec;
*p_Ts = time;
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetCurrentTime(t_Handle h_FmRtc, uint64_t ts)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
ts = ts/p_Rtc->clockPeriodNanoSec;
/* TMR_CNT_L must be written first to get an accurate value */
WRITE_UINT32(p_Rtc->p_MemMap->tmr_cnt_l, (uint32_t)ts);
WRITE_UINT32(p_Rtc->p_MemMap->tmr_cnt_h, (uint32_t)(ts >> 32));
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_GetFreqCompensation(t_Handle h_FmRtc, uint32_t *p_Compensation)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
*p_Compensation = (uint32_t)
DIV_CEIL(ACCUMULATOR_OVERFLOW * 1000,
p_Rtc->clockPeriodNanoSec * p_Rtc->srcClkFreqMhz);
return E_OK;
}
/*****************************************************************************/
t_Error FM_RTC_SetFreqCompensation(t_Handle h_FmRtc, uint32_t freqCompensation)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
/* set the new freqCompensation */
WRITE_UINT32(p_Rtc->p_MemMap->tmr_add, freqCompensation);
return E_OK;
}
/*****************************************************************************/
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
t_Error FM_RTC_DumpRegs(t_Handle h_FmRtc)
{
t_FmRtc *p_Rtc = (t_FmRtc *)h_FmRtc;
t_FmRtcMemMap *p_MemMap = p_Rtc->p_MemMap;
int i = 0;
DECLARE_DUMP;
if (p_MemMap)
{
DUMP_TITLE(p_MemMap, ("RTC:"));
DUMP_VAR(p_MemMap, tmr_id);
DUMP_VAR(p_MemMap, tmr_id2);
DUMP_VAR(p_MemMap, tmr_ctrl);
DUMP_VAR(p_MemMap, tmr_tevent);
DUMP_VAR(p_MemMap, tmr_temask);
DUMP_VAR(p_MemMap, tmr_cnt_h);
DUMP_VAR(p_MemMap, tmr_cnt_l);
DUMP_VAR(p_MemMap, tmr_ctrl);
DUMP_VAR(p_MemMap, tmr_add);
DUMP_VAR(p_MemMap, tmr_acc);
DUMP_VAR(p_MemMap, tmr_prsc);
DUMP_VAR(p_MemMap, tmr_off_h);
DUMP_VAR(p_MemMap, tmr_off_l);
DUMP_SUBSTRUCT_ARRAY(i, 2)
{
DUMP_VAR(p_MemMap, tmr_alarm[i].tmr_alarm_h);
DUMP_VAR(p_MemMap, tmr_alarm[i].tmr_alarm_l);
}
DUMP_SUBSTRUCT_ARRAY(i, 2)
{
DUMP_VAR(p_MemMap, tmr_fiper[i]);
DUMP_VAR(p_MemMap, tmr_fiper[i]);
}
DUMP_SUBSTRUCT_ARRAY(i, 2)
{
DUMP_VAR(p_MemMap, tmr_etts[i].tmr_etts_l);
DUMP_VAR(p_MemMap, tmr_etts[i].tmr_etts_l);
}
}
return E_OK;
}
#endif /* (defined(DEBUG_ERRORS) && ... */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm_rtc.h
@Description Memory map and internal definitions for FM RTC IEEE1588 Timer driver.
@Cautions None
*//***************************************************************************/
#ifndef __FM_RTC_H__
#define __FM_RTC_H__
#include "std_ext.h"
#include "fm_rtc_ext.h"
#define __ERR_MODULE__ MODULE_FM_RTC
/* General definitions */
#define NANOSEC_PER_ONE_HZ_TICK 1000000000
#define MIN_RTC_CLK_FREQ_HZ 1000
#define MHz 1000000
#define ACCUMULATOR_OVERFLOW ((uint64_t)(1LL << 32))
/* RTC default values */
#define DEFAULT_srcClock e_FM_RTC_SOURCE_CLOCK_SYSTEM
#define DEFAULT_bypass FALSE
#define DEFAULT_invertInputClkPhase FALSE
#define DEFAULT_invertOutputClkPhase FALSE
#define DEFAULT_outputClockDivisor 0x00000002
#define DEFAULT_alarmPolarity e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH
#define DEFAULT_triggerPolarity e_FM_RTC_TRIGGER_ON_FALLING_EDGE
#define DEFAULT_pulseRealign FALSE
#define DEFAULT_clockPeriod 1000
/* FM RTC Registers definitions */
#define TMR_CTRL_ALMP1 0x80000000
#define TMR_CTRL_ALMP2 0x40000000
#define TMR_CTRL_FS 0x10000000
#define TMR_CTRL_PP1L 0x08000000
#define TMR_CTRL_PP2L 0x04000000
#define TMR_CTRL_TCLK_PERIOD_MASK 0x03FF0000
#define TMR_CTRL_FRD 0x00004000
#define TMR_CTRL_SLV 0x00002000
#define TMR_CTRL_ETEP1 0x00000100
#define TMR_CTRL_COPH 0x00000080
#define TMR_CTRL_CIPH 0x00000040
#define TMR_CTRL_TMSR 0x00000020
#define TMR_CTRL_DBG 0x00000010
#define TMR_CTRL_BYP 0x00000008
#define TMR_CTRL_TE 0x00000004
#define TMR_CTRL_CKSEL_OSC_CLK 0x00000003
#define TMR_CTRL_CKSEL_MAC_CLK 0x00000001
#define TMR_CTRL_CKSEL_EXT_CLK 0x00000000
#define TMR_CTRL_TCLK_PERIOD_SHIFT 16
#define TMR_TEVENT_ETS2 0x02000000
#define TMR_TEVENT_ETS1 0x01000000
#define TMR_TEVENT_ALM2 0x00020000
#define TMR_TEVENT_ALM1 0x00010000
#define TMR_TEVENT_PP1 0x00000080
#define TMR_TEVENT_PP2 0x00000040
#define TMR_TEVENT_PP3 0x00000020
#define TMR_TEVENT_ALL (TMR_TEVENT_ETS2 | TMR_TEVENT_ETS1 | \
TMR_TEVENT_ALM2 | TMR_TEVENT_ALM1 | \
TMR_TEVENT_PP1 | TMR_TEVENT_PP2 | TMR_TEVENT_PP3)
#define TMR_PRSC_OCK_MASK 0x0000FFFF
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/**************************************************************************//**
@Description FM RTC timer alarm
*//***************************************************************************/
typedef _Packed struct t_TmrAlaram
{
volatile uint32_t tmr_alarm_h; /**< */
volatile uint32_t tmr_alarm_l; /**< */
} _PackedType t_TmrAlaram;
/**************************************************************************//**
@Description FM RTC timer Ex trigger
*//***************************************************************************/
typedef _Packed struct t_TmrExtTrigger
{
volatile uint32_t tmr_etts_h; /**< */
volatile uint32_t tmr_etts_l; /**< */
} _PackedType t_TmrExtTrigger;
typedef _Packed struct
{
volatile uint32_t tmr_id; /* Module ID and version register */
volatile uint32_t tmr_id2; /* Module ID and configuration register */
volatile uint32_t PTP_RESERVED1[30];
volatile uint32_t tmr_ctrl; /* timer control register */
volatile uint32_t tmr_tevent; /* timer event register */
volatile uint32_t tmr_temask; /* timer event mask register */
volatile uint32_t PTP_RESERVED2[3];
volatile uint32_t tmr_cnt_h; /* timer counter high register */
volatile uint32_t tmr_cnt_l; /* timer counter low register */
volatile uint32_t tmr_add; /* timer drift compensation addend register */
volatile uint32_t tmr_acc; /* timer accumulator register */
volatile uint32_t tmr_prsc; /* timer prescale */
volatile uint32_t PTP_RESERVED3;
volatile uint32_t tmr_off_h; /* timer offset high */
volatile uint32_t tmr_off_l; /* timer offset low */
volatile t_TmrAlaram tmr_alarm[FM_RTC_NUM_OF_ALARMS]; /* timer alarm */
volatile uint32_t PTP_RESERVED4[2];
volatile uint32_t tmr_fiper[FM_RTC_NUM_OF_PERIODIC_PULSES]; /* timer fixed period interval */
volatile uint32_t PTP_RESERVED5[2];
volatile t_TmrExtTrigger tmr_etts[FM_RTC_NUM_OF_EXT_TRIGGERS]; /*time stamp general purpose external */
volatile uint32_t PTP_RESERVED6[3];
} _PackedType t_FmRtcMemMap;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description RTC FM driver parameters structure.
*//***************************************************************************/
typedef struct t_FmRtcDriverParam
{
t_Handle h_Fm; /**< */
e_FmSrcClk srcClk; /**< */
uint32_t extSrcClkFreq; /**< */
uint32_t rtcFreqHz; /**< */
bool timerSlaveMode; /*Slave/Master Mode*/
bool invertInputClkPhase;
bool invertOutputClkPhase;
uint32_t eventsMask;
bool bypass; /**< Indicates if frequency compensation is bypassed */
bool pulseRealign;
e_FmRtcAlarmPolarity alarmPolarity[FM_RTC_NUM_OF_ALARMS];
e_FmRtcTriggerPolarity triggerPolarity[FM_RTC_NUM_OF_EXT_TRIGGERS];
} t_FmRtcDriverParam;
typedef struct t_FmRtcAlarm
{
t_FmRtcExceptionsCallback *f_AlarmCallback;
bool clearOnExpiration;
} t_FmRtcAlarm;
typedef struct t_FmRtcPeriodicPulse
{
t_FmRtcExceptionsCallback *f_PeriodicPulseCallback;
} t_FmRtcPeriodicPulse;
typedef struct t_FmRtcExternalTrigger
{
t_FmRtcExceptionsCallback *f_ExternalTriggerCallback;
} t_FmRtcExternalTrigger;
/**************************************************************************//**
@Description RTC FM driver control structure.
*//***************************************************************************/
typedef struct t_FmRtc
{
t_Part *p_Part; /**< Pointer to the integration device */
t_Handle h_Fm;
t_Handle h_App; /**< Application handle */
t_FmRtcMemMap *p_MemMap; /**< Pointer to RTC memory map */
uint32_t clockPeriodNanoSec; /**< RTC clock period in nano-seconds (for FS mode) */
uint32_t srcClkFreqMhz;
uint16_t outputClockDivisor; /**< Output clock divisor (for FS mode) */
t_FmRtcAlarm alarmParams[FM_RTC_NUM_OF_ALARMS];
t_FmRtcPeriodicPulse periodicPulseParams[FM_RTC_NUM_OF_PERIODIC_PULSES];
t_FmRtcExternalTrigger externalTriggerParams[FM_RTC_NUM_OF_EXT_TRIGGERS];
t_FmRtcDriverParam *p_RtcDriverParam; /**< RTC Driver parameters (for Init phase) */
} t_FmRtc;
#endif /* __FM_RTC_H__ */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File fm.h
@Description FM internal structures and definitions.
*//***************************************************************************/
#ifndef __FM_H
#define __FM_H
#include "error_ext.h"
#include "std_ext.h"
#include "fm_ext.h"
#include "fm_ipc.h"
#define __ERR_MODULE__ MODULE_FM
#define FM_MAX_NUM_OF_HW_PORT_IDS 64
#define FM_MAX_NUM_OF_GUESTS 100
/**************************************************************************//**
@Description Exceptions
*//***************************************************************************/
#define FM_EX_DMA_BUS_ERROR 0x80000000 /**< DMA bus error. */
#define FM_EX_DMA_READ_ECC 0x40000000
#define FM_EX_DMA_SYSTEM_WRITE_ECC 0x20000000
#define FM_EX_DMA_FM_WRITE_ECC 0x10000000
#define FM_EX_FPM_STALL_ON_TASKS 0x08000000 /**< Stall of tasks on FPM */
#define FM_EX_FPM_SINGLE_ECC 0x04000000 /**< Single ECC on FPM */
#define FM_EX_FPM_DOUBLE_ECC 0x02000000
#define FM_EX_QMI_SINGLE_ECC 0x01000000 /**< Single ECC on FPM */
#define FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 /**< Dequeu from default queue id */
#define FM_EX_QMI_DOUBLE_ECC 0x00400000
#define FM_EX_BMI_LIST_RAM_ECC 0x00200000
#define FM_EX_BMI_PIPELINE_ECC 0x00100000
#define FM_EX_BMI_STATISTICS_RAM_ECC 0x00080000
#define FM_EX_IRAM_ECC 0x00040000
#define FM_EX_NURAM_ECC 0x00020000
#define FM_EX_BMI_DISPATCH_RAM_ECC 0x00010000
#define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \
case e_FM_EX_DMA_BUS_ERROR: \
bitMask = FM_EX_DMA_BUS_ERROR; break; \
case e_FM_EX_DMA_READ_ECC: \
bitMask = FM_EX_DMA_READ_ECC; break; \
case e_FM_EX_DMA_SYSTEM_WRITE_ECC: \
bitMask = FM_EX_DMA_SYSTEM_WRITE_ECC; break; \
case e_FM_EX_DMA_FM_WRITE_ECC: \
bitMask = FM_EX_DMA_FM_WRITE_ECC; break; \
case e_FM_EX_FPM_STALL_ON_TASKS: \
bitMask = FM_EX_FPM_STALL_ON_TASKS; break; \
case e_FM_EX_FPM_SINGLE_ECC: \
bitMask = FM_EX_FPM_SINGLE_ECC; break; \
case e_FM_EX_FPM_DOUBLE_ECC: \
bitMask = FM_EX_FPM_DOUBLE_ECC; break; \
case e_FM_EX_QMI_SINGLE_ECC: \
bitMask = FM_EX_QMI_SINGLE_ECC; break; \
case e_FM_EX_QMI_DOUBLE_ECC: \
bitMask = FM_EX_QMI_DOUBLE_ECC; break; \
case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: \
bitMask = FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \
case e_FM_EX_BMI_LIST_RAM_ECC: \
bitMask = FM_EX_BMI_LIST_RAM_ECC; break; \
case e_FM_EX_BMI_PIPELINE_ECC: \
bitMask = FM_EX_BMI_PIPELINE_ECC; break; \
case e_FM_EX_BMI_STATISTICS_RAM_ECC: \
bitMask = FM_EX_BMI_STATISTICS_RAM_ECC; break; \
case e_FM_EX_BMI_DISPATCH_RAM_ECC: \
bitMask = FM_EX_BMI_DISPATCH_RAM_ECC; break; \
case e_FM_EX_IRAM_ECC: \
bitMask = FM_EX_IRAM_ECC; break; \
case e_FM_EX_MURAM_ECC: \
bitMask = FM_EX_NURAM_ECC; break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
#define DEFAULT_exceptions (FM_EX_DMA_BUS_ERROR |\
FM_EX_DMA_READ_ECC |\
FM_EX_DMA_SYSTEM_WRITE_ECC |\
FM_EX_DMA_FM_WRITE_ECC |\
FM_EX_FPM_STALL_ON_TASKS |\
FM_EX_FPM_SINGLE_ECC |\
FM_EX_FPM_DOUBLE_ECC |\
FM_EX_QMI_SINGLE_ECC |\
FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID|\
FM_EX_QMI_DOUBLE_ECC |\
FM_EX_BMI_LIST_RAM_ECC |\
FM_EX_BMI_PIPELINE_ECC |\
FM_EX_BMI_STATISTICS_RAM_ECC |\
FM_EX_BMI_DISPATCH_RAM_ECC |\
FM_EX_IRAM_ECC |\
FM_EX_NURAM_ECC )
#define DEFAULT_totalNumOfTasks (BMI_MAX_NUM_OF_TASKS*3/4)
#define DEFAULT_totalFifoSize (BMI_MAX_FIFO_SIZE*3/4)
#define DEFAULT_maxNumOfOpenDmas (BMI_MAX_NUM_OF_DMAS*3/4)
#define DEFAULT_eccEnable FALSE
#define DEFAULT_dispLimit 0
#define DEFAULT_prsDispTh 16
#define DEFAULT_plcrDispTh 16
#define DEFAULT_kgDispTh 16
#define DEFAULT_bmiDispTh 16
#define DEFAULT_qmiEnqDispTh 16
#define DEFAULT_qmiDeqDispTh 16
#define DEFAULT_fmCtl1DispTh 16
#define DEFAULT_fmCtl2DispTh 16
#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR
#ifdef FM_PEDANTIC_DMA
#define DEFAULT_aidOverride TRUE
#else
#define DEFAULT_aidOverride FALSE
#endif /* FM_PEDANTIC_DMA */
#define DEFAULT_aidMode e_FM_DMA_AID_OUT_TNUM
#define DEFAULT_dmaStopOnBusError FALSE
#define DEFAULT_stopAtBusError FALSE
#define DEFAULT_axiDbgNumOfBeats 1
#define DEFAULT_dmaCamNumOfEntries 32
#define DEFAULT_dmaCommQLow ((DMA_THRESH_MAX_COMMQ+1)/2)
#define DEFAULT_dmaCommQHigh ((DMA_THRESH_MAX_COMMQ+1)*3/4)
#define DEFAULT_dmaReadIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
#define DEFAULT_dmaReadIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
#define DEFAULT_dmaWriteIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
#define DEFAULT_dmaWriteIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
#define DEFAULT_dmaSosEmergency 0
#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT
#define DEFAULT_catastrophicErr e_FM_CATASTROPHIC_ERR_STALL_PORT
#define DEFAULT_dmaErr e_FM_DMA_ERR_CATASTROPHIC
#define DEFAULT_resetOnInit FALSE
#define DEFAULT_haltOnExternalActivation FALSE /* do not change! if changed, must be disabled for rev1 ! */
#define DEFAULT_haltOnUnrecoverableEccError FALSE /* do not change! if changed, must be disabled for rev1 ! */
#define DEFAULT_externalEccRamsEnable FALSE
#define DEFAULT_VerifyUcode FALSE
#define DEFAULT_tnumAgingPeriod 0
#define DEFAULT_dmaWatchdog 0 /* disabled */
#define DEFAULT_mtu 9600
/**************************************************************************//**
@Description Modules registers offsets
*//***************************************************************************/
#define FM_MM_MURAM 0x00000000
#define FM_MM_BMI 0x00080000
#define FM_MM_QMI 0x00080400
#define FM_MM_PRS 0x000c7000
#define FM_MM_KG 0x000C1000
#define FM_MM_DMA 0x000C2000
#define FM_MM_FPM 0x000C3000
#define FM_MM_PLCR 0x000C0000
#define FM_MM_IMEM 0x000C4000
/**************************************************************************//**
@Description Interrupt Enable/Mask
*//***************************************************************************/
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct
{
volatile uint32_t fpmtnc; /**< FPM TNUM Control */
volatile uint32_t fpmpr; /**< FPM Port_ID FmCtl Association */
volatile uint32_t brkc; /**< FPM Breakpoint Control */
volatile uint32_t fpmflc; /**< FPM Flush Control */
volatile uint32_t fpmdis1; /**< FPM Dispatch Thresholds1 */
volatile uint32_t fpmdis2; /**< FPM Dispatch Thresholds2 */
volatile uint32_t fmepi; /**< FM Error Pending Interrupts */
volatile uint32_t fmrie; /**< FM Error Interrupt Enable */
volatile uint32_t fmfpfcev[4]; /**< FPM FMan-Controller Event 1-4 */
volatile uint8_t res1[16]; /**< reserved */
volatile uint32_t fmfpfcee[4]; /**< PM FMan-Controller Event 1-4 */
volatile uint8_t res2[16]; /**< reserved */
volatile uint32_t fpmtsc1; /**< FPM TimeStamp Control1 */
volatile uint32_t fpmtsc2; /**< FPM TimeStamp Control2 */
volatile uint32_t fpmtsp; /**< FPM Time Stamp */
volatile uint32_t fpmtsf; /**< FPM Time Stamp Fraction */
volatile uint32_t fmrcr; /**< FM Rams Control */
volatile uint32_t fpmextc; /**< FPM External Requests Control */
volatile uint32_t fpmext1; /**< FPM External Requests Config1 */
volatile uint32_t fpmext2; /**< FPM External Requests Config2 */
volatile uint32_t fpmdrd[16]; /**< FPM Data_Ram Data 0-15 */
volatile uint32_t fpmdra; /**< FPM Data Ram Access */
volatile uint32_t fm_ip_rev_1; /**< FM IP Block Revision 1 */
volatile uint32_t fm_ip_rev_2; /**< FM IP Block Revision 2 */
volatile uint32_t fmrstc; /**< FM Reset Command */
volatile uint32_t fmcld; /**< FM Classifier Debug */
volatile uint32_t fmnpi; /**< FM Normal Pending Interrupts */
volatile uint32_t fmfp_exte; /**< FPM External Requests Enable */
volatile uint32_t fpmem; /**< FPM Event & Mask */
volatile uint32_t fpmcev[4]; /**< FPM CPU Event 1-4 */
volatile uint8_t res4[16]; /**< reserved */
volatile uint32_t fmfp_ps[0x40]; /**< FPM Port Status */
volatile uint8_t reserved1[0x260];
volatile uint32_t fpmts[128]; /**< 0x400: FPM Task Status */
} _PackedType t_FmFpmRegs;
#define NUM_OF_DBG_TRAPS 3
typedef _Packed struct
{
volatile uint32_t fmbm_init; /**< BMI Initialization */
volatile uint32_t fmbm_cfg1; /**< BMI Configuration 1 */
volatile uint32_t fmbm_cfg2; /**< BMI Configuration 2 */
volatile uint32_t reserved[5];
volatile uint32_t fmbm_ievr; /**< Interrupt Event Register */
volatile uint32_t fmbm_ier; /**< Interrupt Enable Register */
volatile uint32_t fmbm_ifr; /**< Interrupt Force Register */
volatile uint32_t reserved1[5];
volatile uint32_t fmbm_arb[8]; /**< BMI Arbitration */
volatile uint32_t reserved2[12];
volatile uint32_t fmbm_dtc[NUM_OF_DBG_TRAPS]; /**< BMI Debug Trap Counter */
volatile uint32_t reserved3;
volatile uint32_t fmbm_dcv[NUM_OF_DBG_TRAPS][4]; /**< BMI Debug Compare Value */
volatile uint32_t fmbm_dcm[NUM_OF_DBG_TRAPS][4]; /**< BMI Debug Compare Mask */
volatile uint32_t fmbm_gde; /**< BMI Global Debug Enable */
volatile uint32_t fmbm_pp[63]; /**< BMI Port Parameters */
volatile uint32_t reserved4;
volatile uint32_t fmbm_pfs[63]; /**< BMI Port FIFO Size */
volatile uint32_t reserved5;
volatile uint32_t fmbm_ppid[63]; /**< Port Partition ID */
} _PackedType t_FmBmiRegs;
typedef _Packed struct
{
volatile uint32_t fmqm_gc; /**< General Configuration Register */
volatile uint32_t Reserved0;
volatile uint32_t fmqm_eie; /**< Error Interrupt Event Register */
volatile uint32_t fmqm_eien; /**< Error Interrupt Enable Register */
volatile uint32_t fmqm_eif; /**< Error Interrupt Force Register */
volatile uint32_t fmqm_ie; /**< Interrupt Event Register */
volatile uint32_t fmqm_ien; /**< Interrupt Enable Register */
volatile uint32_t fmqm_if; /**< Interrupt Force Register */
volatile uint32_t fmqm_gs; /**< Global Status Register */
volatile uint32_t fmqm_ts; /**< Task Status Register */
volatile uint32_t fmqm_etfc; /**< Enqueue Total Frame Counter */
volatile uint32_t fmqm_dtfc; /**< Dequeue Total Frame Counter */
volatile uint32_t fmqm_dc0; /**< Dequeue Counter 0 */
volatile uint32_t fmqm_dc1; /**< Dequeue Counter 1 */
volatile uint32_t fmqm_dc2; /**< Dequeue Counter 2 */
volatile uint32_t fmqm_dc3; /**< Dequeue Counter 3 */
volatile uint32_t fmqm_dfdc; /**< Dequeue FQID from Default Counter */
volatile uint32_t fmqm_dfcc; /**< Dequeue FQID from Context Counter */
volatile uint32_t fmqm_dffc; /**< Dequeue FQID from FD Counter */
volatile uint32_t fmqm_dcc; /**< Dequeue Confirm Counter */
volatile uint32_t Reserved1a[7];
volatile uint32_t fmqm_tapc; /**< Tnum Aging Period Control */
volatile uint32_t fmqm_dmcvc; /**< Dequeue MAC Command Valid Counter */
volatile uint32_t fmqm_difdcc; /**< Dequeue Invalid FD Command Counter */
volatile uint32_t fmqm_da1v; /**< Dequeue A1 Valid Counter */
volatile uint32_t Reserved1b;
volatile uint32_t fmqm_dtc; /**< 0x0080 Debug Trap Counter */
volatile uint32_t fmqm_efddd; /**< 0x0084 Enqueue Frame Descriptor Dynamic Debug */
volatile uint32_t Reserved3[2];
_Packed struct {
volatile uint32_t fmqm_dtcfg1; /**< 0x0090 Debug Trap Configuration 1 Register */
volatile uint32_t fmqm_dtval1; /**< Debug Trap Value 1 Register */
volatile uint32_t fmqm_dtm1; /**< Debug Trap Mask 1 Register */
volatile uint32_t fmqm_dtc1; /**< Debug Trap Counter 1 Register */
volatile uint32_t fmqm_dtcfg2; /**< Debug Trap Configuration 2 Register */
volatile uint32_t fmqm_dtval2; /**< Debug Trap Value 2 Register */
volatile uint32_t fmqm_dtm2; /**< Debug Trap Mask 2 Register */
volatile uint32_t Reserved1;
} _PackedType dbgTraps[NUM_OF_DBG_TRAPS];
} _PackedType t_FmQmiRegs;
typedef _Packed struct
{
volatile uint32_t fmdmsr; /**< FM DMA status register 0x04 */
volatile uint32_t fmdmmr; /**< FM DMA mode register 0x08 */
volatile uint32_t fmdmtr; /**< FM DMA bus threshold register 0x0c */
volatile uint32_t fmdmhy; /**< FM DMA bus hysteresis register 0x10 */
volatile uint32_t fmdmsetr; /**< FM DMA SOS emergency Threshold Register 0x14 */
volatile uint32_t fmdmtah; /**< FM DMA transfer bus address high register 0x18 */
volatile uint32_t fmdmtal; /**< FM DMA transfer bus address low register 0x1C */
volatile uint32_t fmdmtcid; /**< FM DMA transfer bus communication ID register 0x20 */
volatile uint32_t fmdmra; /**< FM DMA bus internal ram address register 0x24 */
volatile uint32_t fmdmrd; /**< FM DMA bus internal ram data register 0x28 */
volatile uint32_t fmdmwcr; /**< FM DMA CAM watchdog counter value 0x2C */
volatile uint32_t fmdmebcr; /**< FM DMA CAM base in MURAM register 0x30 */
volatile uint32_t fmdmccqdr; /**< FM DMA CAM and CMD Queue Debug register 0x34 */
volatile uint32_t fmdmccqvr1; /**< FM DMA CAM and CMD Queue Value register #1 0x38 */
volatile uint32_t fmdmccqvr2; /**< FM DMA CAM and CMD Queue Value register #2 0x3C */
volatile uint32_t fmdmcqvr3; /**< FM DMA CMD Queue Value register #3 0x40 */
volatile uint32_t fmdmcqvr4; /**< FM DMA CMD Queue Value register #4 0x44 */
volatile uint32_t fmdmcqvr5; /**< FM DMA CMD Queue Value register #5 0x48 */
volatile uint32_t fmdmsefrc; /**< FM DMA Semaphore Entry Full Reject Counter 0x50 */
volatile uint32_t fmdmsqfrc; /**< FM DMA Semaphore Queue Full Reject Counter 0x54 */
volatile uint32_t fmdmssrc; /**< FM DMA Semaphore SYNC Reject Counter 0x54 */
volatile uint32_t fmdmdcr; /**< FM DMA Debug Counter */
volatile uint32_t fmdmemsr; /**< FM DMA Emrgency Smoother Register */
volatile uint32_t reserved;
volatile uint32_t fmdmplr[FM_SIZE_OF_LIODN_TABLE/2];
/**< FM DMA PID-LIODN # register */
} _PackedType t_FmDmaRegs;
typedef _Packed struct
{
volatile uint32_t iadd; /**< FM IRAM instruction address register */
volatile uint32_t idata; /**< FM IRAM instruction data register */
volatile uint32_t itcfg; /**< FM IRAM timing config register */
volatile uint32_t iready; /**< FM IRAM ready register */
volatile uint8_t res[0x80000-0x10];
} _PackedType t_FMIramRegs;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description General defines
*//***************************************************************************/
#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL
#define FM_UCODE_DEBUG_INSTRUCTION 0x6ffff805UL
/**************************************************************************//**
@Description DMA definitions
*//***************************************************************************/
/* masks */
#define DMA_MODE_AID_OR 0x20000000
#define DMA_MODE_SBER 0x10000000
#define DMA_MODE_BER 0x00200000
#define DMA_MODE_ECC 0x00000020
#define DMA_MODE_PRIVILEGE_PROT 0x00001000
#define DMA_MODE_SECURE_PROT 0x00000800
#define DMA_MODE_EMERGENCY_READ 0x00080000
#define DMA_MODE_EMERGENCY_WRITE 0x00040000
#define DMA_TRANSFER_PORTID_MASK 0xFF000000
#define DMA_TRANSFER_TNUM_MASK 0x00FF0000
#define DMA_TRANSFER_LIODN_MASK 0x00000FFF
#define DMA_HIGH_LIODN_MASK 0x0FFF0000
#define DMA_LOW_LIODN_MASK 0x00000FFF
#define DMA_STATUS_CMD_QUEUE_NOT_EMPTY 0x10000000
#define DMA_STATUS_BUS_ERR 0x08000000
#define DMA_STATUS_READ_ECC 0x04000000
#define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000
#define DMA_STATUS_FM_WRITE_ECC 0x01000000
#define DMA_STATUS_SYSTEM_DPEXT_ECC 0x00800000
#define DMA_STATUS_FM_DPEXT_ECC 0x00400000
#define DMA_STATUS_SYSTEM_DPDAT_ECC 0x00200000
#define DMA_STATUS_FM_DPDAT_ECC 0x00100000
#define DMA_STATUS_FM_SPDAT_ECC 0x00080000
#define FM_LIODN_BASE_MASK 0x00000FFF
/* shifts */
#define DMA_MODE_CACHE_OR_SHIFT 30
#define DMA_MODE_BUS_PRI_SHIFT 16
#define DMA_MODE_AXI_DBG_SHIFT 24
#define DMA_MODE_CEN_SHIFT 13
#define DMA_MODE_BUS_PROT_SHIFT 10
#define DMA_MODE_DBG_SHIFT 7
#define DMA_MODE_EMERGENCY_LEVEL_SHIFT 6
#define DMA_MODE_AID_MODE_SHIFT 4
#define DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS 16
#define DMA_MODE_MAX_CAM_NUM_OF_ENTRIES 32
#define DMA_THRESH_COMMQ_SHIFT 24
#define DMA_THRESH_READ_INT_BUF_SHIFT 16
#define DMA_LIODN_SHIFT 16
#define DMA_TRANSFER_PORTID_SHIFT 24
#define DMA_TRANSFER_TNUM_SHIFT 16
/* sizes */
#define DMA_MAX_WATCHDOG 0xffffffff
/* others */
#define DMA_CAM_SIZEOF_ENTRY 0x40
#define DMA_CAM_ALIGN 0x1000
#define DMA_CAM_UNITS 8
/**************************************************************************//**
@Description FPM defines
*//***************************************************************************/
/* masks */
#define FPM_EV_MASK_DOUBLE_ECC 0x80000000
#define FPM_EV_MASK_STALL 0x40000000
#define FPM_EV_MASK_SINGLE_ECC 0x20000000
#define FPM_EV_MASK_RELEASE_FM 0x00010000
#define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000
#define FPM_EV_MASK_STALL_EN 0x00004000
#define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000
#define FPM_EV_MASK_EXTERNAL_HALT 0x00000008
#define FPM_EV_MASK_ECC_ERR_HALT 0x00000004
#define FPM_RAM_CTL_RAMS_ECC_EN 0x80000000
#define FPM_RAM_CTL_IRAM_ECC_EN 0x40000000
#define FPM_RAM_CTL_MURAM_ECC 0x00008000
#define FPM_RAM_CTL_IRAM_ECC 0x00004000
#define FPM_RAM_CTL_MURAM_TEST_ECC 0x20000000
#define FPM_RAM_CTL_IRAM_TEST_ECC 0x10000000
#define FPM_RAM_CTL_RAMS_ECC_EN_SRC_SEL 0x08000000
#define FPM_IRAM_ECC_ERR_EX_EN 0x00020000
#define FPM_MURAM_ECC_ERR_EX_EN 0x00040000
#define FPM_REV1_MAJOR_MASK 0x0000FF00
#define FPM_REV1_MINOR_MASK 0x000000FF
#define FPM_REV2_INTEG_MASK 0x00FF0000
#define FPM_REV2_ERR_MASK 0x0000FF00
#define FPM_REV2_CFG_MASK 0x000000FF
#define FPM_TS_FRACTION_MASK 0x0000FFFF
#define FPM_TS_CTL_EN 0x80000000
#define FPM_PORT_FM_CTL1 0x00000001
#define FPM_PORT_FM_CTL2 0x00000002
#define FPM_PRC_REALSE_STALLED 0x00800000
#define FPM_PS_STALLED 0x00800000
#define FPM_PS_FM_CTL1_SEL 0x80000000
#define FPM_PS_FM_CTL2_SEL 0x40000000
#define FPM_PS_FM_CTL_SEL_MASK (FPM_PS_FM_CTL1_SEL | FPM_PS_FM_CTL2_SEL)
#define FPM_RSTC_FM_RESET 0x80000000
#define FPM_RSTC_10G0_RESET 0x04000000
#define FPM_RSTC_1G0_RESET 0x40000000
#define FPM_RSTC_1G1_RESET 0x20000000
#define FPM_RSTC_1G2_RESET 0x10000000
#define FPM_RSTC_1G3_RESET 0x08000000
#define FPM_RSTC_1G4_RESET 0x02000000
/* shifts */
#define FPM_DISP_LIMIT_SHIFT 24
#define FPM_THR1_PRS_SHIFT 24
#define FPM_THR1_KG_SHIFT 16
#define FPM_THR1_PLCR_SHIFT 8
#define FPM_THR1_BMI_SHIFT 0
#define FPM_THR2_QMI_ENQ_SHIFT 24
#define FPM_THR2_QMI_DEQ_SHIFT 0
#define FPM_THR2_FM_CTL1_SHIFT 16
#define FPM_THR2_FM_CTL2_SHIFT 8
#define FPM_EV_MASK_CAT_ERR_SHIFT 1
#define FPM_EV_MASK_DMA_ERR_SHIFT 0
#define FPM_REV1_MAJOR_SHIFT 8
#define FPM_REV1_MINOR_SHIFT 0
#define FPM_REV2_INTEG_SHIFT 16
#define FPM_REV2_ERR_SHIFT 8
#define FPM_REV2_CFG_SHIFT 0
#define FPM_TS_INT_SHIFT 16
#define FPM_PORT_FM_CTL_PORTID_SHIFT 24
#define FPM_PS_FM_CTL_SEL_SHIFT 30
#define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16
/* Interrupts defines */
#define FPM_EVENT_FM_CTL_0 0x00008000
#define FPM_EVENT_FM_CTL 0x0000FF00
#define FPM_EVENT_FM_CTL_BRK 0x00000080
/* others */
#define FPM_MAX_DISP_LIMIT 31
/**************************************************************************//**
@Description BMI defines
*//***************************************************************************/
/* masks */
#define BMI_INIT_START 0x80000000
#define BMI_ERR_INTR_EN_PIPELINE_ECC 0x80000000
#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000
#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000
#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000
#define BMI_NUM_OF_TASKS_MASK 0x3F000000
#define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000
#define BMI_NUM_OF_DMAS_MASK 0x00000F00
#define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F
#define BMI_FIFO_SIZE_MASK 0x000003FF
#define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000
#define BMI_CFG2_DMAS_MASK 0x0000003F
/* shifts */
#define BMI_CFG2_TASKS_SHIFT 16
#define BMI_CFG2_DMAS_SHIFT 0
#define BMI_CFG1_FIFO_SIZE_SHIFT 16
#define BMI_FIFO_SIZE_SHIFT 0
#define BMI_EXTRA_FIFO_SIZE_SHIFT 16
#define BMI_NUM_OF_TASKS_SHIFT 24
#define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16
#define BMI_NUM_OF_DMAS_SHIFT 8
#define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0
/* others */
#define BMI_FIFO_ALIGN 0x100
/**************************************************************************//**
@Description QMI defines
*//***************************************************************************/
/* masks */
#define QMI_CFG_ENQ_EN 0x80000000
#define QMI_CFG_DEQ_EN 0x40000000
#define QMI_CFG_EN_COUNTERS 0x10000000
#define QMI_CFG_SOFT_RESET 0x01000000
#define QMI_CFG_DEQ_MASK 0x0000003F
#define QMI_CFG_ENQ_MASK 0x00003F00
#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000
#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000
#define QMI_INTR_EN_SINGLE_ECC 0x80000000
/* shifts */
#define QMI_CFG_ENQ_SHIFT 8
#define QMI_TAPC_TAP 22
/**************************************************************************//**
@Description IRAM defines
*//***************************************************************************/
/* masks */
#define IRAM_IADD_AIE 0x80000000
#define IRAM_READY 0x80000000
typedef struct {
void (*f_Isr) (t_Handle h_Arg, uint32_t event);
t_Handle h_SrcHandle;
} t_FmanCtrlIntrSrc;
typedef struct
{
/* uint8_t numOfPartitions; */
bool resetOnInit;
#ifdef FM_PARTITION_ARRAY
uint16_t liodnBasePerPort[FM_SIZE_OF_LIODN_TABLE];
#endif
bool enCounters;
t_FmThresholds thresholds;
e_FmDmaCacheOverride dmaCacheOverride;
e_FmDmaAidMode dmaAidMode;
bool dmaAidOverride;
uint8_t dmaAxiDbgNumOfBeats;
uint8_t dmaCamNumOfEntries;
uint32_t dmaWatchdog;
t_FmDmaThresholds dmaCommQThresholds;
t_FmDmaThresholds dmaWriteBufThresholds;
t_FmDmaThresholds dmaReadBufThresholds;
uint32_t dmaSosEmergency;
e_FmDmaDbgCntMode dmaDbgCntMode;
bool dmaStopOnBusError;
bool dmaEnEmergency;
t_FmDmaEmergency dmaEmergency;
bool dmaEnEmergencySmoother;
uint32_t dmaEmergencySwitchCounter;
bool haltOnExternalActivation;
bool haltOnUnrecoverableEccError;
e_FmCatastrophicErr catastrophicErr;
e_FmDmaErr dmaErr;
bool enMuramTestMode;
bool enIramTestMode;
bool externalEccRamsEnable;
uint16_t tnumAgingPeriod;
t_FmPcdFirmwareParams firmware;
bool fwVerify;
} t_FmDriverParam;
typedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event);
typedef struct
{
/***************************/
/* Master/Guest parameters */
/***************************/
uint8_t fmId;
e_FmPortType portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS];
uint16_t fmClkFreq;
/**************************/
/* Master Only parameters */
/**************************/
bool enabledTimeStamp;
uint8_t count1MicroBit;
uint8_t totalNumOfTasks;
uint32_t totalFifoSize;
uint8_t maxNumOfOpenDmas;
uint8_t accumulatedNumOfTasks;
uint32_t accumulatedFifoSize;
uint8_t accumulatedNumOfOpenDmas;
#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT
uint8_t accumulatedNumOfDeqTnums;
#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */
#ifdef FM_LOW_END_RESTRICTION
bool lowEndRestriction;
#endif /* FM_LOW_END_RESTRICTION */
uint32_t exceptions;
int irq;
int errIrq;
bool ramsEccEnable;
bool explicitEnable;
bool internalCall;
uint8_t ramsEccOwners;
uint32_t extraFifoPoolSize;
uint8_t extraTasksPoolSize;
uint8_t extraOpenDmasPoolSize;
#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS)
uint16_t macMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];
#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS) */
uint16_t macMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];
} t_FmStateStruct;
typedef struct
{
/***************************/
/* Master/Guest parameters */
/***************************/
/* locals for recovery */
uintptr_t baseAddr;
/* un-needed for recovery */
t_Handle h_Pcd;
char fmModuleName[MODULE_NAME_SIZE];
char fmIpcHandlerModuleName[FM_MAX_NUM_OF_GUESTS][MODULE_NAME_SIZE];
t_Handle h_IpcSessions[FM_MAX_NUM_OF_GUESTS];
t_FmIntrSrc intrMng[e_FM_EV_DUMMY_LAST]; /* FM exceptions user callback */
uint8_t guestId;
/**************************/
/* Master Only parameters */
/**************************/
/* locals for recovery */
t_FmFpmRegs *p_FmFpmRegs;
t_FmBmiRegs *p_FmBmiRegs;
t_FmQmiRegs *p_FmQmiRegs;
t_FmDmaRegs *p_FmDmaRegs;
t_FmExceptionsCallback *f_Exception;
t_FmBusErrorCallback *f_BusError;
t_Handle h_App; /* Application handle */
t_Handle h_Spinlock;
bool recoveryMode;
t_FmStateStruct *p_FmStateStruct;
/* un-needed for recovery */
t_FmDriverParam *p_FmDriverParam;
t_Handle h_FmMuram;
uint64_t fmMuramPhysBaseAddr;
bool independentMode;
bool hcPortInitialized;
uintptr_t camBaseAddr; /* save for freeing */
uintptr_t resAddr;
uintptr_t fifoBaseAddr; /* save for freeing */
t_FmanCtrlIntrSrc fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; /* FM exceptions user callback */
bool usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS];
} t_Fm;
#endif /* __FM_H */

35
sys/contrib/ncsw/Peripherals/FM/fm_guest.c Normal file
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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

449
sys/contrib/ncsw/Peripherals/FM/fm_ipc.h Normal file
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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_ipc.h
@Description FM Inter-Partition prototypes, structures and definitions.
*//***************************************************************************/
#ifndef __FM_IPC_H
#define __FM_IPC_H
#include "error_ext.h"
#include "std_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_IPC_grp FM Inter-Partition messaging Unit
@Description FM Inter-Partition messaging unit API definitions and enums.
@{
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/**************************************************************************//**
@Description enum for defining MAC types
*//***************************************************************************/
/**************************************************************************//**
@Description A structure of parameters for specifying a MAC.
*//***************************************************************************/
typedef _Packed struct
{
uint8_t id;
uint32_t enumType;
} _PackedType t_FmIpcMacParams;
/**************************************************************************//**
@Description A structure of parameters for specifying a MAC.
*//***************************************************************************/
typedef _Packed struct
{
t_FmIpcMacParams macParams;
uint16_t maxFrameLength;
} _PackedType t_FmIpcMacMaxFrameParams;
/**************************************************************************//**
@Description FM physical Address
*//***************************************************************************/
typedef _Packed struct t_FmIpcPhysAddr
{
volatile uint8_t high;
volatile uint32_t low;
} _PackedType t_FmIpcPhysAddr;
/**************************************************************************//**
@Description Structure for IPC communication during FM_PORT_Init.
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortInInitParams {
uint8_t hardwarePortId; /**< IN. port Id */
uint32_t enumPortType; /**< IN. Port type */
uint8_t boolIndependentMode;/**< IN. TRUE if FM Port operates in independent mode */
uint16_t liodnOffset; /**< IN. Port's requested resource */
uint8_t numOfTasks; /**< IN. Port's requested resource */
uint8_t numOfExtraTasks; /**< IN. Port's requested resource */
uint8_t numOfOpenDmas; /**< IN. Port's requested resource */
uint8_t numOfExtraOpenDmas; /**< IN. Port's requested resource */
uint32_t sizeOfFifo; /**< IN. Port's requested resource */
uint32_t extraSizeOfFifo; /**< IN. Port's requested resource */
uint8_t deqPipelineDepth; /**< IN. Port's requested resource */
uint16_t liodnBase; /**< IN. Irrelevant for P4080 rev 1.
LIODN base for this port, to be
used together with LIODN offset. */
} _PackedType t_FmIpcPortInInitParams;
/**************************************************************************//**
@Description Structure for IPC communication between port and FM
regarding tasks and open DMA resources management.
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortRsrcParams {
uint8_t hardwarePortId; /**< IN. port Id */
uint32_t val; /**< IN. Port's requested resource */
uint32_t extra; /**< IN. Port's requested resource */
uint8_t boolInitialConfig;
} _PackedType t_FmIpcPortRsrcParams;
/**************************************************************************//**
@Description Structure for IPC communication between port and FM
regarding tasks and open DMA resources management.
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortFifoParams {
t_FmIpcPortRsrcParams rsrcParams;
uint32_t enumPortType;
uint8_t boolIndependentMode;
uint8_t deqPipelineDepth;
uint8_t numOfPools;
uint16_t secondLargestBufSize;
uint16_t largestBufSize;
uint8_t boolInitialConfig;
} _PackedType t_FmIpcPortFifoParams;
/**************************************************************************//**
@Description Structure for port-FM communication during FM_PORT_Free.
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortFreeParams {
uint8_t hardwarePortId; /**< IN. port Id */
uint32_t enumPortType; /**< IN. Port type */
#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT
uint8_t deqPipelineDepth; /**< IN. Port's requested resource */
#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */
} _PackedType t_FmIpcPortFreeParams;
/**************************************************************************//**
@Description Structure for defining DMA status
*//***************************************************************************/
typedef _Packed struct t_FmIpcDmaStatus {
uint8_t boolCmqNotEmpty; /**< Command queue is not empty */
uint8_t boolBusError; /**< Bus error occurred */
uint8_t boolReadBufEccError; /**< Double ECC error on buffer Read */
uint8_t boolWriteBufEccSysError; /**< Double ECC error on buffer write from system side */
uint8_t boolWriteBufEccFmError; /**< Double ECC error on buffer write from FM side */
} _PackedType t_FmIpcDmaStatus;
typedef _Packed struct t_FmIpcRegisterIntr
{
uint8_t guestId; /* IN */
uint32_t event; /* IN */
} _PackedType t_FmIpcRegisterIntr;
typedef _Packed struct t_FmIpcIsr
{
uint8_t boolErr; /* IN */
uint32_t pendingReg; /* IN */
} _PackedType t_FmIpcIsr;
/**************************************************************************//**
@Description structure for returning revision information
*//***************************************************************************/
typedef _Packed struct t_FmIpcRevisionInfo {
uint8_t majorRev; /**< OUT: Major revision */
uint8_t minorRev; /**< OUT: Minor revision */
} _PackedType t_FmIpcRevisionInfo;
/**************************************************************************//**
@Description Structure for defining Fm number of Fman controlers
*//***************************************************************************/
typedef _Packed struct t_FmIpcPortNumOfFmanCtrls {
uint8_t hardwarePortId; /**< IN. port Id */
uint8_t numOfFmanCtrls; /**< IN. Port type */
} t_FmIpcPortNumOfFmanCtrls;
/**************************************************************************//**
@Description structure for setting Fman contriller events
*//***************************************************************************/
typedef _Packed struct t_FmIpcFmanEvents {
uint8_t eventRegId; /**< IN: Fman controller event register id */
uint32_t enableEvents; /**< IN/OUT: required enabled events mask */
} _PackedType t_FmIpcFmanEvents;
#define FM_IPC_MAX_REPLY_BODY_SIZE 16
#define FM_IPC_MAX_REPLY_SIZE (FM_IPC_MAX_REPLY_BODY_SIZE + sizeof(uint32_t))
#define FM_IPC_MAX_MSG_SIZE 30
typedef _Packed struct t_FmIpcMsg
{
uint32_t msgId;
uint8_t msgBody[FM_IPC_MAX_MSG_SIZE];
} _PackedType t_FmIpcMsg;
typedef _Packed struct t_FmIpcReply
{
uint32_t error;
uint8_t replyBody[FM_IPC_MAX_REPLY_BODY_SIZE];
} _PackedType t_FmIpcReply;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/***************************************************************************/
/************************ FRONT-END-TO-BACK-END*****************************/
/***************************************************************************/
/**************************************************************************//**
@Function FM_GET_TIMESTAMP_SCALE
@Description Used by FM front-end.
@Param[out] uint32_t Pointer
*//***************************************************************************/
#define FM_GET_TIMESTAMP_SCALE 1
/**************************************************************************//**
@Function FM_GET_COUNTER
@Description Used by FM front-end.
@Param[in/out] t_FmIpcGetCounter Pointer
*//***************************************************************************/
#define FM_GET_COUNTER 2
/**************************************************************************//**
@Function FM_DUMP_REGS
@Description Used by FM front-end for the PORT module in order to set and get
parameters in/from master FM module on FM PORT initialization time.
@Param None
*//***************************************************************************/
#define FM_DUMP_REGS 3
/**************************************************************************//**
@Function FM_GET_SET_PORT_PARAMS
@Description Used by FM front-end for the PORT module in order to set and get
parameters in/from master FM module on FM PORT initialization time.
@Param[in/out] t_FmIcPortInitParams Pointer
*//***************************************************************************/
#define FM_GET_SET_PORT_PARAMS 4
/**************************************************************************//**
@Function FM_FREE_PORT
@Description Used by FM front-end for the PORT module when a port is freed
to free all FM PORT resources.
@Param[in] uint8_t Pointer
*//***************************************************************************/
#define FM_FREE_PORT 5
/**************************************************************************//**
@Function FM_RESET_MAC
@Description Used by front-end for the MAC module to reset the MAC registers
@Param[in] t_FmIpcMacParams Pointer .
*//***************************************************************************/
#define FM_RESET_MAC 6
/**************************************************************************//**
@Function FM_RESUME_STALLED_PORT
@Description Used by FM front-end for the PORT module in order to
release a stalled FM Port.
@Param[in] uint8_t Pointer
*//***************************************************************************/
#define FM_RESUME_STALLED_PORT 7
/**************************************************************************//**
@Function FM_IS_PORT_STALLED
@Description Used by FM front-end for the PORT module in order to check whether
an FM port is stalled.
@Param[in/out] t_FmIcPortIsStalled Pointer
*//***************************************************************************/
#define FM_IS_PORT_STALLED 8
/**************************************************************************//**
@Function FM_DUMP_PORT_REGS
@Description Used by FM front-end for the PORT module in order to dump
all port registers.
@Param[in] uint8_t Pointer
*//***************************************************************************/
#define FM_DUMP_PORT_REGS 9
/**************************************************************************//**
@Function FM_GET_REV
@Description Used by FM front-end for the PORT module in order to dump
all port registers.
@Param[in] uint8_t Pointer
*//***************************************************************************/
#define FM_GET_REV 10
/**************************************************************************//**
@Function FM_REGISTER_INTR
@Description Used by FM front-end to register an interrupt handler to
be called upon interrupt for guest.
@Param[out] t_FmIpcRegisterIntr Pointer
*//***************************************************************************/
#define FM_REGISTER_INTR 11
/**************************************************************************//**
@Function FM_GET_CLK_FREQ
@Description Used by FM Front-end to read the FM clock frequency.
@Param[out] uint32_t Pointer
*//***************************************************************************/
#define FM_GET_CLK_FREQ 12
/**************************************************************************//**
@Function FM_DMA_STAT
@Description Used by FM front-end to read the FM DMA status.
@Param[out] t_FmIpcDmaStatus Pointer
*//***************************************************************************/
#define FM_DMA_STAT 13
/**************************************************************************//**
@Function FM_ALLOC_FMAN_CTRL_EVENT_REG
@Description Used by FM front-end to allocate event register.
@Param[out] Event register id Pointer
*//***************************************************************************/
#define FM_ALLOC_FMAN_CTRL_EVENT_REG 14
/**************************************************************************//**
@Function FM_FREE_FMAN_CTRL_EVENT_REG
@Description Used by FM front-end to free locate event register.
@Param[in] uint8_t Pointer - Event register id
*//***************************************************************************/
#define FM_FREE_FMAN_CTRL_EVENT_REG 15
/**************************************************************************//**
@Function FM_SET_FMAN_CTRL_EVENTS_ENABLE
@Description Used by FM front-end to enable events in the FPM
Fman controller event register.
@Param[in] t_FmIpcFmanEvents Pointer
*//***************************************************************************/
#define FM_SET_FMAN_CTRL_EVENTS_ENABLE 16
/**************************************************************************//**
@Function FM_SET_FMAN_CTRL_EVENTS_ENABLE
@Description Used by FM front-end to enable events in the FPM
Fman controller event register.
@Param[in/out] t_FmIpcFmanEvents Pointer
*//***************************************************************************/
#define FM_GET_FMAN_CTRL_EVENTS_ENABLE 17
/**************************************************************************//**
@Function FM_SET_MAC_MAX_FRAME
@Description Used by FM front-end to set MAC's MTU/RTU's in
back-end.
@Param[in/out] t_FmIpcMacMaxFrameParams Pointer
*//***************************************************************************/
#define FM_SET_MAC_MAX_FRAME 18
/**************************************************************************//**
@Function FM_GET_PHYS_MURAM_BASE
@Description Used by FM front-end in order to get MURAM base address
@Param[in/out] t_FmIpcPhysAddr Pointer
*//***************************************************************************/
#define FM_GET_PHYS_MURAM_BASE 19
/**************************************************************************//**
@Function FM_MASTER_IS_ALIVE
@Description Used by FM front-end in order to verify Master is up
@Param[in/out] bool
*//***************************************************************************/
#define FM_MASTER_IS_ALIVE 20
#define FM_ENABLE_RAM_ECC 21
#define FM_DISABLE_RAM_ECC 22
#define FM_SET_NUM_OF_FMAN_CTRL 23
#define FM_SET_SIZE_OF_FIFO 24
#define FM_SET_NUM_OF_TASKS 25
#define FM_SET_NUM_OF_OPEN_DMAS 26
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
#define FM_10G_TX_ECC_WA 100
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
/***************************************************************************/
/************************ BACK-END-TO-FRONT-END*****************************/
/***************************************************************************/
/**************************************************************************//**
@Function FM_GUEST_ISR
@Description Used by FM back-end to report an interrupt to the front-end.
@Param[out] t_FmIpcIsr Pointer
*//***************************************************************************/
#define FM_GUEST_ISR 1
/** @} */ /* end of FM_IPC_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_IPC_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File FM_muram.c
@Description FM MURAM ...
*//***************************************************************************/
#include "error_ext.h"
#include "std_ext.h"
#include "mm_ext.h"
#include "string_ext.h"
#include "sprint_ext.h"
#include "fm_muram_ext.h"
#include "fm_common.h"
#define __ERR_MODULE__ MODULE_FM_MURAM
typedef struct
{
t_Handle h_Mem;
uintptr_t baseAddr;
uint32_t size;
} t_FmMuram;
void FmMuramClear(t_Handle h_FmMuram)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
SANITY_CHECK_RETURN(h_FmMuram, E_INVALID_HANDLE);
IOMemSet32(UINT_TO_PTR(p_FmMuram->baseAddr), 0, p_FmMuram->size);
}
t_Handle FM_MURAM_ConfigAndInit(uintptr_t baseAddress, uint32_t size)
{
t_Handle h_Mem;
t_FmMuram *p_FmMuram;
if (!baseAddress)
{
REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("baseAddress 0 is not supported"));
return NULL;
}
if (baseAddress%4)
{
REPORT_ERROR(MAJOR, E_INVALID_VALUE, ("baseAddress not 4 bytes aligned!"));
return NULL;
}
/* Allocate FM MURAM structure */
p_FmMuram = (t_FmMuram *) XX_Malloc(sizeof(t_FmMuram));
if (!p_FmMuram)
{
REPORT_ERROR(MAJOR, E_NO_MEMORY, ("FM MURAM driver structure"));
return NULL;
}
memset(p_FmMuram, 0, sizeof(t_FmMuram));
if ((MM_Init(&h_Mem, baseAddress, size) != E_OK) || (!h_Mem))
{
XX_Free(p_FmMuram);
REPORT_ERROR(MAJOR, E_INVALID_HANDLE, ("FM-MURAM partition!!!"));
return NULL;
}
/* Initialize FM MURAM parameters which will be kept by the driver */
p_FmMuram->baseAddr = baseAddress;
p_FmMuram->size = size;
p_FmMuram->h_Mem = h_Mem;
return p_FmMuram;
}
t_Error FM_MURAM_Free(t_Handle h_FmMuram)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
if (p_FmMuram->h_Mem)
MM_Free(p_FmMuram->h_Mem);
XX_Free(h_FmMuram);
return E_OK;
}
void * FM_MURAM_AllocMem(t_Handle h_FmMuram, uint32_t size, uint32_t align)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
uintptr_t addr;
SANITY_CHECK_RETURN_VALUE(h_FmMuram, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_FmMuram->h_Mem, E_INVALID_HANDLE, NULL);
addr = (uintptr_t)MM_Get(p_FmMuram->h_Mem, size, align ,"FM MURAM");
if (addr == ILLEGAL_BASE)
return NULL;
return UINT_TO_PTR(addr);
}
void * FM_MURAM_AllocMemForce(t_Handle h_FmMuram, uint64_t base, uint32_t size)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
uintptr_t addr;
SANITY_CHECK_RETURN_VALUE(h_FmMuram, E_INVALID_HANDLE, NULL);
SANITY_CHECK_RETURN_VALUE(p_FmMuram->h_Mem, E_INVALID_HANDLE, NULL);
addr = (uintptr_t)MM_GetForce(p_FmMuram->h_Mem, base, size, "FM MURAM");
if (addr == ILLEGAL_BASE)
return NULL;
return UINT_TO_PTR(addr);
}
t_Error FM_MURAM_FreeMem(t_Handle h_FmMuram, void *ptr)
{
t_FmMuram *p_FmMuram = ( t_FmMuram *)h_FmMuram;
SANITY_CHECK_RETURN_ERROR(h_FmMuram, E_INVALID_HANDLE);
SANITY_CHECK_RETURN_ERROR(p_FmMuram->h_Mem, E_INVALID_HANDLE);
if (MM_Put(p_FmMuram->h_Mem, PTR_TO_UINT(ptr)) == 0)
RETURN_ERROR(MINOR, E_INVALID_HANDLE, ("memory pointer!!!"));
return E_OK;
}

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __FM_HC_H
#define __FM_HC_H
#include "std_ext.h"
#include "error_ext.h"
#define __ERR_MODULE__ MODULE_FM_PCD
typedef struct t_FmHcParams {
t_Handle h_Fm;
t_Handle h_FmPcd;
t_FmPcdHcParams params;
} t_FmHcParams;
t_Handle FmHcConfigAndInit(t_FmHcParams *p_FmHcParams);
void FmHcFree(t_Handle h_FmHc);
t_Error FmHcDumpRegs(t_Handle h_FmHc);
void FmHcTxConf(t_Handle h_FmHc, t_DpaaFD *p_Fd);
t_Handle FmHcPcdKgSetScheme(t_Handle h_FmHc, t_FmPcdKgSchemeParams *p_Scheme);
t_Error FmHcPcdKgDeleteScheme(t_Handle h_FmHc, t_Handle h_Scheme);
t_Error FmHcPcdCcCapwapTimeoutReassm(t_Handle h_FmHc, t_FmPcdCcCapwapReassmTimeoutParams *p_CcCapwapReassmTimeoutParams );
t_Error FmHcPcdKgSetClsPlan(t_Handle h_FmHc, t_FmPcdKgInterModuleClsPlanSet *p_Set);
t_Error FmHcPcdKgDeleteClsPlan(t_Handle h_FmHc, uint8_t clsPlanGrpId);
t_Error FmHcPcdKgSetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t value);
uint32_t FmHcPcdKgGetSchemeCounter(t_Handle h_FmHc, t_Handle h_Scheme);
t_Error FmHcPcdCcModifyTreeNextEngine(t_Handle h_FmHc, t_Handle h_CcTree, uint8_t grpId, uint8_t index, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams);
t_Error FmHcPcdCcModifyNodeNextEngine(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams);
t_Error FmHcPcdCcModifyNodeMissNextEngine(t_Handle h_FmHc, t_Handle h_CcNode, t_FmPcdCcNextEngineParams *p_FmPcdCcNextEngineParams);
t_Error FmHcPcdCcRemoveKey(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex);
t_Error FmHcPcdCcAddKey(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex, uint8_t keySize, t_FmPcdCcKeyParams *p_KeyParams);
t_Error FmHcPcdCcModifyKeyAndNextEngine(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex, uint8_t keySize, t_FmPcdCcKeyParams *p_KeyParams);
t_Error FmHcPcdCcModifyKey(t_Handle h_FmHc, t_Handle h_CcNode, uint8_t keyIndex, uint8_t keySize, uint8_t *p_Key, uint8_t *p_Mask);
t_Handle FmHcPcdPlcrSetProfile(t_Handle h_FmHc,t_FmPcdPlcrProfileParams *p_Profile);
t_Error FmHcPcdPlcrDeleteProfile(t_Handle h_FmHc, t_Handle h_Profile);
t_Error FmHcPcdPlcrSetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter, uint32_t value);
uint32_t FmHcPcdPlcrGetProfileCounter(t_Handle h_FmHc, t_Handle h_Profile, e_FmPcdPlcrProfileCounters counter);
t_Error FmHcKgWriteSp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t spReg, bool add);
t_Error FmHcKgWriteCpp(t_Handle h_FmHc, uint8_t hardwarePortId, uint32_t cppReg);
t_Error FmHcPcdKgCcGetSetParams(t_Handle h_FmHc, t_Handle h_Scheme, uint32_t requiredAction);
t_Error FmHcPcdPlcrCcGetSetParams(t_Handle h_FmHc,uint16_t absoluteProfileId, uint32_t requiredAction);
#endif /* __FM_HC_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File qm.h
@Description QM header
*//***************************************************************************/
#ifndef __QM_H
#define __QM_H
#include "std_ext.h"
#include "list_ext.h"
#include "qm_ext.h"
#include "qman_private.h"
#include "qm_ipc.h"
#define __ERR_MODULE__ MODULE_QM
#define QM_NUM_OF_SWP 10
#define QM_NUM_OF_DCP 5
#define CACHELINE_SIZE 64
#define QM_CONTEXTA_MAX_STASH_SIZE (3 * CACHELINE_SIZE)
/**************************************************************************//**
@Description Exceptions
*//***************************************************************************/
#define QM_EX_CORENET_INITIATOR_DATA 0x20000000
#define QM_EX_CORENET_TARGET_DATA 0x10000000
#define QM_EX_CORENET_INVALID_TARGET_TRANSACTION 0x08000000
#define QM_EX_PFDR_THRESHOLD 0x04000000
#define QM_EX_MULTI_ECC 0x02000000
#define QM_EX_SINGLE_ECC 0x01000000
#define QM_EX_PFDR_ENQUEUE_BLOCKED 0x00800000
#define QM_EX_INVALID_COMMAND 0x00010000
#define QM_EX_DEQUEUE_DCP 0x00000800
#define QM_EX_DEQUEUE_FQ 0x00000400
#define QM_EX_DEQUEUE_SOURCE 0x00000200
#define QM_EX_DEQUEUE_QUEUE 0x00000100
#define QM_EX_ENQUEUE_OVERFLOW 0x00000008
#define QM_EX_ENQUEUE_STATE 0x00000004
#define QM_EX_ENQUEUE_CHANNEL 0x00000002
#define QM_EX_ENQUEUE_QUEUE 0x00000001
#define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \
case e_QM_EX_CORENET_INITIATOR_DATA: \
bitMask = QM_EX_CORENET_INITIATOR_DATA; break; \
case e_QM_EX_CORENET_TARGET_DATA: \
bitMask = QM_EX_CORENET_TARGET_DATA; break; \
case e_QM_EX_CORENET_INVALID_TARGET_TRANSACTION: \
bitMask = QM_EX_CORENET_INVALID_TARGET_TRANSACTION; break; \
case e_QM_EX_PFDR_THRESHOLD: \
bitMask = QM_EX_PFDR_THRESHOLD; break; \
case e_QM_EX_PFDR_ENQUEUE_BLOCKED: \
bitMask = QM_EX_PFDR_ENQUEUE_BLOCKED; break; \
case e_QM_EX_SINGLE_ECC: \
bitMask = QM_EX_SINGLE_ECC; break; \
case e_QM_EX_MULTI_ECC: \
bitMask = QM_EX_MULTI_ECC; break; \
case e_QM_EX_INVALID_COMMAND: \
bitMask = QM_EX_INVALID_COMMAND; break; \
case e_QM_EX_DEQUEUE_DCP: \
bitMask = QM_EX_DEQUEUE_DCP; break; \
case e_QM_EX_DEQUEUE_FQ: \
bitMask = QM_EX_DEQUEUE_FQ; break; \
case e_QM_EX_DEQUEUE_SOURCE: \
bitMask = QM_EX_DEQUEUE_SOURCE; break; \
case e_QM_EX_DEQUEUE_QUEUE: \
bitMask = QM_EX_DEQUEUE_QUEUE; break; \
case e_QM_EX_ENQUEUE_OVERFLOW: \
bitMask = QM_EX_ENQUEUE_OVERFLOW; break; \
case e_QM_EX_ENQUEUE_STATE: \
bitMask = QM_EX_ENQUEUE_STATE; break; \
case e_QM_EX_ENQUEUE_CHANNEL: \
bitMask = QM_EX_ENQUEUE_CHANNEL; break; \
case e_QM_EX_ENQUEUE_QUEUE: \
bitMask = QM_EX_ENQUEUE_QUEUE; break; \
default: bitMask = 0;break;}
/**************************************************************************//**
@Description defaults
*//***************************************************************************/
/* QM defaults */
#define DEFAULT_exceptions ((uint32_t)(QM_EX_CORENET_INITIATOR_DATA | \
QM_EX_CORENET_TARGET_DATA | \
QM_EX_CORENET_INVALID_TARGET_TRANSACTION | \
QM_EX_PFDR_THRESHOLD | \
QM_EX_SINGLE_ECC | \
QM_EX_MULTI_ECC | \
QM_EX_PFDR_ENQUEUE_BLOCKED | \
QM_EX_INVALID_COMMAND | \
QM_EX_DEQUEUE_DCP | \
QM_EX_DEQUEUE_FQ | \
QM_EX_DEQUEUE_SOURCE | \
QM_EX_DEQUEUE_QUEUE | \
QM_EX_ENQUEUE_OVERFLOW | \
QM_EX_ENQUEUE_STATE | \
QM_EX_ENQUEUE_CHANNEL | \
QM_EX_ENQUEUE_QUEUE ))
#define DEFAULT_rtFramesDepth 30000
#define DEFAULT_pfdrThreshold 0
#define DEFAULT_sfdrThreshold 0
#define DEFAULT_pfdrBaseConstant 64
/* Corenet initiator settings. Stash request queues are 4-deep to match cores'
ability to snart. Stash priority is 3, other priorities are 2. */
#define DEFAULT_initiatorSrcciv 0
#define DEFAULT_initiatorSrqW 3
#define DEFAULT_initiatorRwW 2
#define DEFAULT_initiatorBmanW 2
/* QM-Portal defaults */
#define DEFAULT_dequeueDcaMode FALSE
#define DEFAULT_dequeueUpToThreeFrames TRUE
#define DEFAULT_dequeueCommandType e_QM_PORTAL_PRIORITY_PRECEDENCE_INTRA_CLASS_SCHEDULING
#define DEFAULT_dequeueUserToken 0xab
#define DEFAULT_dequeueSpecifiedWq FALSE
#define DEFAULT_dequeueDedicatedChannel TRUE
#define DEFAULT_dequeuePoolChannelId 0
#define DEFAULT_dequeueWqId 0
#define DEFAULT_dequeueDedicatedChannelHasPrecedenceOverPoolChannels TRUE
#define DEFAULT_dqrrSize DQRR_MAXFILL
#define DEFAULT_pullMode FALSE
#define DEFAULT_portalExceptions ((uint32_t)(QM_PIRQ_EQCI | \
QM_PIRQ_EQRI | \
QM_PIRQ_DQRI | \
QM_PIRQ_MRI | \
QM_PIRQ_CSCI))
/**************************************************************************//**
@Description Memory Mapped Registers
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct
{
/* QMan Software Portal Configuration Registers */
_Packed struct {
volatile uint32_t lio_cfg; /**< QMan Software Portal LIO Configuration */
volatile uint32_t io_cfg; /**< QMan Software Portal 0 IO Configuration */
volatile uint8_t res1[4]; /**< reserved */
volatile uint32_t dd_cfg; /**< Software Portal Dynamic Debug Configuration */
} _PackedType swpConfRegs[QM_NUM_OF_SWP];
volatile uint8_t res1[352]; /**< reserved */
/* Dynamic Debug (DD) Configuration Registers */
volatile uint32_t qman_dd_cfg; /**< QMan Dynamic Debug (DD) Configuration */
volatile uint8_t res2[12]; /**< reserved */
volatile uint32_t qcsp_dd_ihrsr; /**< Software Portal DD Internal Halt Request Status */
volatile uint32_t qcsp_dd_ihrfr; /**< Software Portal DD Internal Halt Request Force */
volatile uint32_t qcsp_dd_hasr; /**< Software Portal DD Halt Acknowledge Status */
volatile uint8_t res3[4]; /**< reserved */
volatile uint32_t dcp_dd_ihrsr; /**< DCP DD Internal Halt Request Status */
volatile uint32_t dcp_dd_ihrfr; /**< DCP DD Internal Halt Request Force */
volatile uint32_t dcp_dd_hasr; /**< DCP DD Halt Acknowledge Status */
volatile uint8_t res4[212]; /**< reserved */
/* Direct Connect Portal (DCP) Configuration Registers */
_Packed struct {
volatile uint32_t cfg; /**< DCP Configuration */
volatile uint32_t dd_cfg; /**< DCP Dynamic Debug Configuration */
volatile uint32_t dlm_cfg; /**< DCP Dequeue Latency Monitor Configuration */
volatile uint32_t dlm_avg; /**< DCP Dequeue Latency Monitor Average */
} _PackedType dcpConfRegs[QM_NUM_OF_DCP];
volatile uint8_t res5[176]; /**< reserved */
/* Packed Frame Descriptor Record (PFDR) Manager Query Registers */
volatile uint32_t pfdr_fpc; /**< PFDR Free Pool Count */
volatile uint32_t pfdr_fp_head; /**< PFDR Free Pool Head Pointer */
volatile uint32_t pfdr_fp_tail; /**< PFDR Free Pool Tail Pointer */
volatile uint8_t res6[4]; /**< reserved */
volatile uint32_t pfdr_fp_lwit; /**< PFDR Free Pool Low Watermark Interrupt Threshold */
volatile uint32_t pfdr_cfg; /**< PFDR Configuration */
volatile uint8_t res7[232]; /**< reserved */
/* Single Frame Descriptor Record (SFDR) Manager Registers */
volatile uint32_t sfdr_cfg; /**< SFDR Configuration */
volatile uint32_t sfdr_in_use; /**< SFDR In Use Register */
volatile uint8_t res8[248]; /**< reserved */
/* Work Queue Semaphore and Context Manager Registers */
volatile uint32_t wq_cs_cfg[6]; /**< Work Queue Class Scheduler Configuration */
volatile uint8_t res9[24]; /**< reserved */
volatile uint32_t wq_def_enq_wqid; /**< Work Queue Default Enqueue WQID */
volatile uint8_t res10[12]; /**< reserved */
volatile uint32_t wq_sc_dd_cfg[5]; /**< WQ S/W Channel Dynamic Debug Config */
volatile uint8_t res11[44]; /**< reserved */
volatile uint32_t wq_pc_dd_cs_cfg[8]; /**< WQ Pool Channel Dynamic Debug Config */
volatile uint8_t res12[32]; /**< reserved */
volatile uint32_t wq_dc0_dd_cs_cfg[6]; /**< WQ DCP0 Chan. Dynamic Debug Config */
volatile uint8_t res13[40]; /**< reserved */
volatile uint32_t wq_dc1_dd_cs_cfg[6]; /**< WQ DCP1 Chan. Dynamic Debug Config */
volatile uint8_t res14[40]; /**< reserved */
volatile uint32_t wq_dc2_dd_cs_cfg; /**< WQ DCP2 Chan. Dynamic Debug Config */
volatile uint8_t res15[60]; /**< reserved */
volatile uint32_t wq_dc3_dd_cs_cfg; /**< WQ DCP3 Chan. Dynamic Debug Config */
volatile uint8_t res16[124]; /**< reserved */
/* Congestion Manager (CM) Registers */
volatile uint32_t cm_cfg; /**< CM Configuration Register */
volatile uint8_t res17[508]; /**< reserved */
/* QMan Error Capture Registers */
volatile uint32_t ecsr; /**< QMan Error Capture Status Register */
volatile uint32_t ecir; /**< QMan Error Capture Information Register */
volatile uint32_t eadr; /**< QMan Error Capture Address Register */
volatile uint8_t res18[4]; /**< reserved */
volatile uint32_t edata[16]; /**< QMan ECC Error Data Register */
volatile uint8_t res19[32]; /**< reserved */
volatile uint32_t sbet; /**< QMan Single Bit ECC Error Threshold Register */
volatile uint8_t res20[12]; /**< reserved */
volatile uint32_t sbec[7]; /**< QMan Single Bit ECC Error Count Register */
volatile uint8_t res21[100]; /**< reserved */
/* QMan Initialization and Debug Control Registers */
volatile uint32_t mcr; /**< QMan Management Command/Result Register */
volatile uint32_t mcp0; /**< QMan Management Command Parameter 0 Register */
volatile uint32_t mcp1; /**< QMan Management Command Parameter 1 Register */
volatile uint8_t res22[20]; /**< reserved */
volatile uint32_t mr[16]; /**< QMan Management Return Register */
volatile uint8_t res23[148]; /**< reserved */
volatile uint32_t idle_stat; /**< QMan Idle Status Register */
/* QMan ID/Revision Registers */
volatile uint32_t ip_rev_1; /**< QMan IP Block Revision 1 register */
volatile uint32_t ip_rev_2; /**< QMan IP Block Revision 2 register */
/* QMan Initiator Interface Memory Window Configuration Registers */
volatile uint32_t fqd_bare; /**< FQD Extended Base Address Register */
volatile uint32_t fqd_bar; /**< Frame Queue Descriptor (FQD) Base Address Register */
volatile uint8_t res24[8]; /**< reserved */
volatile uint32_t fqd_ar; /**< FQD Attributes Register */
volatile uint8_t res25[12]; /**< reserved */
volatile uint32_t pfdr_bare; /**< PFDR Extended Base Address Register */
volatile uint32_t pfdr_bar; /**< Packed Frame Descriptor Record (PFDR) Base Addr */
volatile uint8_t res26[8]; /**< reserved */
volatile uint32_t pfdr_ar; /**< PFDR Attributes Register */
volatile uint8_t res27[76]; /**< reserved */
volatile uint32_t qcsp_bare; /**< QCSP Extended Base Address */
volatile uint32_t qcsp_bar; /**< QMan Software Portal Base Address */
volatile uint8_t res28[120]; /**< reserved */
volatile uint32_t ci_sched_cfg; /**< Initiator Scheduling Configuration */
volatile uint32_t srcidr; /**< QMan Source ID Register */
volatile uint32_t liodnr; /**< QMan Logical I/O Device Number Register */
volatile uint8_t res29[4]; /**< reserved */
volatile uint32_t ci_rlm_cfg; /**< Initiator Read Latency Monitor Configuration */
volatile uint32_t ci_rlm_avg; /**< Initiator Read Latency Monitor Average */
volatile uint8_t res30[232]; /**< reserved */
/* QMan Interrupt and Error Registers */
volatile uint32_t err_isr; /**< QMan Error Interrupt Status Register */
volatile uint32_t err_ier; /**< QMan Error Interrupt Enable Register */
volatile uint32_t err_isdr; /**< QMan Error Interrupt Status Disable Register */
volatile uint32_t err_iir; /**< QMan Error Interrupt Inhibit Register */
volatile uint8_t res31[4]; /**< reserved */
volatile uint32_t err_her; /**< QMan Error Halt Enable Register */
} _PackedType t_QmRegs;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/**************************************************************************//**
@Description General defines
*//***************************************************************************/
#define MODULE_NAME_SIZE 30
#define PORTALS_OFFSET_CE(portal) (0x4000 * portal)
#define PORTALS_OFFSET_CI(portal) (0x1000 * portal)
#define PFDR_ENTRY_SIZE 64 /* 64 bytes */
#define FQD_ENTRY_SIZE 64 /* 64 bytes */
/* Compilation constants */
#define DQRR_MAXFILL 15
#define EQCR_THRESH 1 /* reread h/w CI when running out of space */
/**************************************************************************//**
@Description Register defines
*//***************************************************************************/
/* Assists for QMAN_MCR */
#define MCR_INIT_PFDR 0x01000000
#define MCR_get_rslt(v) (uint8_t)((v) >> 24)
#define MCR_rslt_idle(r) (!rslt || (rslt >= 0xf0))
#define MCR_rslt_ok(r) (rslt == 0xf0)
#define MCR_rslt_eaccess(r) (rslt == 0xf8)
#define MCR_rslt_inval(r) (rslt == 0xff)
/* masks */
#define REV1_MAJOR_MASK 0x0000FF00
#define REV1_MINOR_MASK 0x000000FF
#define REV2_INTEG_MASK 0x00FF0000
#define REV2_ERR_MASK 0x0000FF00
#define REV2_CFG_MASK 0x000000FF
#define AR_ENABLE 0x80000000
#define AR_PRIORITY 0x40000000
#define AR_STASH 0x20000000
#define AR_SIZE_MASK 0x0000003f
#define ECIR_PORTAL_TYPE 0x20000000
#define ECIR_PORTAL_MASK 0x1f000000
#define ECIR_FQID_MASK 0x00ffffff
#define CI_SCHED_CFG_EN 0x80000000
/* shifts */
#define REV1_MAJOR_SHIFT 8
#define REV1_MINOR_SHIFT 0
#define REV2_INTEG_SHIFT 16
#define REV2_ERR_SHIFT 8
#define REV2_CFG_SHIFT 0
#define AR_SIZE_SHIFT 0
#define ECIR_PORTAL_SHIFT 24
#define ECIR_FQID_SHIFT 0
#define CI_SCHED_CFG_SRCCIV_SHIFT 24
#define CI_SCHED_CFG_SRQ_W_SHIFT 8
#define CI_SCHED_CFG_RW_W_SHIFT 4
#define CI_SCHED_CFG_BMAN_W_SHIFT 0
/********* CGR ******************************/
#define QM_CGR_TARG_FIRST_SWPORTAL 0x80000000
#define QM_CGR_TARG_FIRST_DCPORTAL 0x00200000
#define QM_CGR_TARGET_SWP(portlaId) (QM_CGR_TARG_FIRST_SWPORTAL >> portlaId)
#define QM_CGR_TARGET_DCP(portlaId) (QM_CGR_TARG_FIRST_DCPORTAL >> portlaId)
#define QM_DCP_CFG_ED 0x00000100
/*
#define CGR_VALID 0x80
#define CGR_VERB_INIT 0x50
#define CGR_VERB_MODIFY 0x51
#define CGR_WRITE_ALL 0x07FF
#define CGR_WRITE_ENABLE_CSCN 0x0010
#define CGR_WRITE_ENABLE_GREEN_MODIFY 0x0380
#define CGR_WRITE_ENABLE_YELLOW_MODIFY 0x0240
#define CGR_WRITE_ENABLE_RED_MODIFY 0x0120
#define CGR_MODE_BYTE 0x00
#define CGR_MODE_FRAME 0x01
#define GCR_ENABLE_WRED 0x01
#define GCR_ENABLE_TD 0x01
#define GCR_ENABLE_CSCN 0x01
*/
/* Lock/unlock frame queues, subject to the "UNLOCKED" flag. This is about
* inter-processor locking only. */
#define FQLOCK(fq) \
do { \
if (fq->flags & QMAN_FQ_FLAG_LOCKED) \
XX_LockSpinlock(&fq->fqlock); \
} while(0)
#define FQUNLOCK(fq) \
do { \
if (fq->flags & QMAN_FQ_FLAG_LOCKED) \
XX_UnlockSpinlock(&fq->fqlock); \
} while(0)
/* Lock/unlock portals, subject to "UNLOCKED" flag. This is about disabling
* interrupts/preemption and, if FLAG_UNLOCKED isn't defined, inter-processor
* locking as well. */
#define NCSW_PLOCK(p) ((t_QmPortal*)(p))->irq_flags = XX_DisableAllIntr()
#define PUNLOCK(p) XX_RestoreAllIntr(((t_QmPortal*)(p))->irq_flags)
typedef void (t_QmLoopDequeueRing)(t_Handle h_QmPortal);
/* Follows WQ_CS_CFG0-5 */
typedef enum {
e_QM_WQ_SW_PORTALS = 0,
e_QM_WQ_POOLS,
e_QM_WQ_DCP0,
e_QM_WQ_DCP1,
e_QM_WQ_DCP2,
e_QM_WQ_DCP3
} e_QmWqClass;
typedef enum {
e_QM_PORTAL_NO_DEQUEUES = 0,
e_QM_PORTAL_PRIORITY_PRECEDENCE_INTRA_CLASS_SCHEDULING,
e_QM_PORTAL_ACTIVE_FQ_PRECEDENCE_INTRA_CLASS_SCHEDULING,
e_QM_PORTAL_ACTIVE_FQ_PRECEDENCE_OVERRIDE_INTRA_CLASS_SCHEDULING
} e_QmPortalDequeueCommandType;
typedef enum e_QmInterModuleCounters {
e_QM_IM_COUNTERS_SFDR_IN_USE = 0,
e_QM_IM_COUNTERS_PFDR_IN_USE,
e_QM_IM_COUNTERS_PFDR_FREE_POOL
} e_QmInterModuleCounters;
typedef struct t_QmInterModulePortalInitParams {
uint8_t portalId;
uint8_t stashDestQueue;
uint16_t liodn;
uint16_t dqrrLiodn;
uint16_t fdFqLiodn;
} t_QmInterModulePortalInitParams;
typedef struct t_QmCg {
t_Handle h_Qm;
t_Handle h_QmPortal;
t_QmExceptionsCallback *f_Exception;
t_Handle h_App;
uint8_t id;
} t_QmCg;
typedef struct {
uintptr_t swPortalsBaseAddress; /**< QM Software Portals Base Address (virtual) */
uint32_t partFqidBase;
uint32_t partNumOfFqids;
uint32_t totalNumOfFqids;
uint32_t rtFramesDepth;
uint32_t fqdMemPartitionId;
uint32_t pfdrMemPartitionId;
uint32_t pfdrThreshold;
uint32_t sfdrThreshold;
uint32_t pfdrBaseConstant;
uint16_t liodn;
t_QmDcPortalParams dcPortalsParams[DPAA_MAX_NUM_OF_DC_PORTALS];
} t_QmDriverParams;
typedef struct {
uint8_t guestId;
t_Handle h_RsrvFqidMm;
t_Handle h_FqidMm;
t_Handle h_Session;
char moduleName[MODULE_NAME_SIZE];
t_Handle h_Portals[DPAA_MAX_NUM_OF_SW_PORTALS];
t_QmRegs *p_QmRegs;
uint32_t *p_FqdBase;
uint32_t *p_PfdrBase;
uint32_t exceptions;
t_QmExceptionsCallback *f_Exception;
t_Handle h_App;
int errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */
uint32_t numOfPfdr;
uint16_t partNumOfCgs;
uint16_t partCgsBase;
uint8_t cgsUsed[QM_MAX_NUM_OF_CGS];
t_Handle lock;
t_QmDriverParams *p_QmDriverParams;
} t_Qm;
typedef struct {
uint32_t hwExtStructsMemAttr;
uint8_t dqrrSize;
bool pullMode;
bool dequeueDcaMode;
bool dequeueUpToThreeFrames;
e_QmPortalDequeueCommandType commandType;
uint8_t userToken;
bool specifiedWq;
bool dedicatedChannel;
bool dedicatedChannelHasPrecedenceOverPoolChannels;
uint8_t poolChannels[QM_MAX_NUM_OF_POOL_CHANNELS];
uint8_t poolChannelId;
uint8_t wqId;
uint16_t fdLiodnOffset;
uint8_t stashDestQueue;
uint8_t eqcr;
bool eqcrHighPri;
bool dqrr;
uint16_t dqrrLiodn;
bool dqrrHighPri;
bool fdFq;
uint16_t fdFqLiodn;
bool fdFqHighPri;
bool fdFqDrop;
} t_QmPortalDriverParams;
/*typedef struct t_QmPortalCgs{
uint32_t cgsMask[QM_MAX_NUM_OF_CGS/32];
}t_QmPortalCgs;
*/
typedef struct t_QmPortal {
t_Handle h_Qm;
struct qm_portal *p_LowQmPortal;
uint32_t bits; /* PORTAL_BITS_*** - dynamic, strictly internal */
t_Handle h_App;
t_QmLoopDequeueRing *f_LoopDequeueRingCB;
bool pullMode;
/* To avoid overloading the term "flags", we use these 2; */
uint32_t options; /* QMAN_PORTAL_FLAG_*** - static, caller-provided */
uint32_t irq_flags;
/* The wrap-around eq_[prod|cons] counters are used to support
* QMAN_ENQUEUE_FLAG_WAIT_SYNC. */
uint32_t eqProd;
volatile int disable_count;
struct qman_cgrs cgrs[2]; /* 2-element array. cgrs[0] is mask, cgrs[1] is previous snapshot. */
/* If we receive a DQRR or MR ring entry for a "null" FQ, ie. for which
* FQD::contextB is NULL rather than pointing to a FQ object, we use
* these handlers. (This is not considered a fast-path mechanism.) */
t_Handle cgsHandles[QM_MAX_NUM_OF_CGS];
struct qman_fq_cb *p_NullCB;
t_QmReceivedFrameCallback *f_DfltFrame;
t_QmRejectedFrameCallback *f_RejectedFrame;
t_QmPortalDriverParams *p_QmPortalDriverParams;
} t_QmPortal;
struct qman_fq {
struct qman_fq_cb cb;
t_Handle h_App;
t_Handle h_QmFqr;
t_Handle fqlock;
uint32_t fqid;
uint32_t fqidOffset;
uint32_t flags;
/* s/w-visible states. Ie. tentatively scheduled + truly scheduled +
* active + held-active + held-suspended are just "sched". Things like
* 'retired' will not be assumed until it is complete (ie.
* QMAN_FQ_STATE_CHANGING is set until then, to indicate it's completing
* and to gate attempts to retry the retire command). Note, park
* commands do not set QMAN_FQ_STATE_CHANGING because it's technically
* impossible in the case of enqueue DCAs (which refer to DQRR ring
* index rather than the FQ that ring entry corresponds to), so repeated
* park commands are allowed (if you're silly enough to try) but won't
* change FQ state, and the resulting park notifications move FQs from
* 'sched' to 'parked'. */
enum qman_fq_state state;
int cgr_groupid;
};
typedef struct {
t_Handle h_Qm;
t_Handle h_QmPortal;
e_QmFQChannel channel;
uint8_t workQueue;
bool shadowMode;
uint32_t fqidBase;
uint32_t numOfFqids;
t_QmFqrDrainedCompletionCB *f_CompletionCB;
t_Handle h_App;
uint32_t numOfDrainedFqids;
bool *p_DrainedFqs;
struct qman_fq **p_Fqs;
} t_QmFqr;
/****************************************/
/* Inter-Module functions */
/****************************************/
uint32_t QmGetCounter(t_Handle h_Qm, e_QmInterModuleCounters counter);
t_Error QmGetRevision(t_Handle h_Qm, t_QmRevisionInfo *p_QmRevisionInfo);
t_Error QmGetSetPortalParams(t_Handle h_Qm, t_QmInterModulePortalInitParams *p_PortalParams);
t_Error QmFreeDcPortal(t_Handle h_Qm, e_DpaaDcPortal dcPortalId);
uint32_t QmFqidGet(t_Qm *p_Qm, uint32_t size, uint32_t alignment, bool force, uint32_t base);
t_Error QmFqidPut(t_Qm *p_Qm, uint32_t base);
t_Error QmGetCgId(t_Handle h_Qm, uint8_t *p_CgId);
t_Error QmFreeCgId(t_Handle h_Qm, uint8_t cgId);
static __inline__ void QmSetPortalHandle(t_Handle h_Qm, t_Handle h_Portal, e_DpaaSwPortal portalId)
{
ASSERT_COND(!((t_Qm*)h_Qm)->h_Portals[portalId] || !h_Portal);
((t_Qm*)h_Qm)->h_Portals[portalId] = h_Portal;
}
static __inline__ t_Handle QmGetPortalHandle(t_Handle h_Qm)
{
t_Qm *p_Qm = (t_Qm*)h_Qm;
ASSERT_COND(p_Qm);
return p_Qm->h_Portals[CORE_GetId()];
}
static __inline__ uint32_t GenerateCgrThresh(uint64_t val, int roundup)
{
uint32_t e = 0; /* co-efficient, exponent */
uint32_t oddbit = 0;
while(val > 0xff) {
oddbit = (uint32_t)val & 1;
val >>= 1;
e++;
if(roundup && oddbit)
val++;
}
return (uint32_t)((val << 5) | e);
}
static __inline__ t_Error SetException(t_Qm *p_Qm, e_QmExceptions exception, bool enable)
{
uint32_t bitMask = 0;
ASSERT_COND(p_Qm);
GET_EXCEPTION_FLAG(bitMask, exception);
if(bitMask)
{
if (enable)
p_Qm->exceptions |= bitMask;
else
p_Qm->exceptions &= ~bitMask;
}
else
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception"));
return E_OK;
}
#endif /* __QM_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/**************************************************************************//**
@File QM_ipc.h
@Description QM Inter-Partition prototypes, structures and definitions.
*//***************************************************************************/
#ifndef __QM_IPC_H
#define __QM_IPC_H
#include "error_ext.h"
#include "std_ext.h"
/**************************************************************************//**
@Group QM_grp Frame Manager API
@Description QM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group QM_IPC_grp Qm Inter-Partition messaging Unit
@Description QM Inter-Partition messaging unit API definitions and enums.
@{
*//***************************************************************************/
#define QM_FORCE_FQID 1
#define QM_PUT_FQID 2
#define QM_GET_COUNTER 3
#define QM_GET_SET_PORTAL_PARAMS 4
#define QM_GET_REVISION 5
#define QM_MASTER_IS_ALIVE 6
#define QM_IPC_MAX_REPLY_BODY_SIZE 16
#define QM_IPC_MAX_REPLY_SIZE (QM_IPC_MAX_REPLY_BODY_SIZE + sizeof(uint32_t))
#define QM_IPC_MAX_MSG_SIZE 30
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
typedef _Packed struct t_QmIpcMsg
{
uint32_t msgId;
uint8_t msgBody[QM_IPC_MAX_MSG_SIZE];
} _PackedType t_QmIpcMsg;
typedef _Packed struct t_QmIpcReply
{
uint32_t error;
uint8_t replyBody[QM_IPC_MAX_REPLY_BODY_SIZE];
} _PackedType t_QmIpcReply;
typedef _Packed struct t_QmIpcGetCounter
{
uint32_t enumId; /**< IN */
} _PackedType t_QmIpcGetCounter;
typedef _Packed struct t_QmIpcFqidParams
{
uint32_t fqid; /**< IN */
uint32_t size; /**< IN */
} _PackedType t_QmIpcFqidParams;
typedef _Packed struct t_QmIpcPortalInitParams {
uint8_t portalId; /**< IN */
uint8_t stashDestQueue; /**< IN */
uint16_t liodn; /**< IN */
uint16_t dqrrLiodn; /**< IN */
uint16_t fdFqLiodn; /**< IN */
} _PackedType t_QmIpcPortalInitParams;
typedef _Packed struct t_QmIpcRevisionInfo {
uint8_t majorRev; /**< OUT: Major revision */
uint8_t minorRev; /**< OUT: Minor revision */
} _PackedType t_QmIpcRevisionInfo;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/** @} */ /* end of QM_IPC_grp group */
/** @} */ /* end of QM_grp group */
#endif /* __QM_IPC_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File qman_private.h
@Description QM private header
*//***************************************************************************/
#ifndef __QMAN_PRIVATE_H
#define __QMAN_PRIVATE_H
#include "fsl_qman.h"
#define __ERR_MODULE__ MODULE_QM
#if defined(DEBUG) || !defined(DISABLE_ASSERTIONS)
/* Optionally compile-in assertion-checking */
#define QM_CHECKING
#endif /* defined(DEBUG) || ... */
/* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers
* and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or
* execution reordering with respect to other code/instructions that manipulate
* the same cacheline. */
#ifdef CORE_E500MC
#if defined(_DIAB_TOOL)
#define hwsync() \
do { \
__asm__ __volatile__ ("sync"); \
} while(0)
#define lwsync() \
do { \
__asm__ __volatile__ ("lwsync"); \
} while(0)
__asm__ __volatile__ void dcbf (volatile void * addr)
{
%reg addr
dcbf r0, addr
}
__asm__ __volatile__ void dcbt_ro (volatile void * addr)
{
%reg addr
dcbt r0, addr
}
__asm__ __volatile__ void dcbt_rw (volatile void * addr)
{
%reg addr
dcbtst r0, addr
}
__asm__ __volatile__ void dcbzl (volatile void * addr)
{
%reg addr
dcbzl r0, addr
}
#define dcbz_64(p) \
do { \
dcbzl(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbt_ro(p); \
} while (0)
#else /* GNU C */
#define hwsync() \
do { \
__asm__ __volatile__ ("sync" : : : "memory"); \
} while(0)
#define lwsync() \
do { \
__asm__ __volatile__ ("lwsync" : : : "memory"); \
} while(0)
#define dcbf(addr) \
do { \
__asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \
} while(0)
#define dcbt_ro(addr) \
do { \
__asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \
} while(0)
#define dcbt_rw(addr) \
do { \
__asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \
} while(0)
#define dcbzl(p) \
do { \
__asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \
} while(0)
#define dcbz_64(p) \
do { \
dcbzl(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbt_ro(p); \
} while (0)
#endif /* _DIAB_TOOL */
#else
#define hwsync CORE_MemoryBarrier
#define lwsync hwsync
#define dcbf(p) \
do { \
__asm__ __volatile__ ("dcbf 0,%0" : : "r" (p)); \
} while(0)
#define dcbt_ro(p) \
do { \
__asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \
lwsync(); \
} while(0)
#define dcbt_rw(p) \
do { \
__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \
} while(0)
#define dcbz(p) \
do { \
__asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \
} while (0)
#define dcbz_64(p) \
do { \
dcbz((uint32_t)p + 32); \
dcbz(p); \
} while (0)
#define dcbf_64(p) \
do { \
dcbf((uint32_t)p + 32); \
dcbf(p); \
} while (0)
/* Commonly used combo */
#define dcbit_ro(p) \
do { \
dcbi(p); \
dcbi((uint32_t)p + 32); \
dcbt_ro(p); \
dcbt_ro((uint32_t)p + 32); \
} while (0)
#endif /* CORE_E500MC */
#define dcbi(p) dcbf(p)
struct qm_addr {
void *addr_ce; /* cache-enabled */
void *addr_ci; /* cache-inhibited */
};
/* EQCR state */
struct qm_eqcr {
struct qm_eqcr_entry *ring, *cursor;
uint8_t ci, available, ithresh, vbit;
#ifdef QM_CHECKING
uint32_t busy;
e_QmPortalProduceMode pmode;
e_QmPortalEqcrConsumeMode cmode;
#endif /* QM_CHECKING */
};
/* DQRR state */
struct qm_dqrr {
struct qm_dqrr_entry *ring, *cursor;
uint8_t pi, ci, fill, ithresh, vbit, flags;
#ifdef QM_CHECKING
e_QmPortalDequeueMode dmode;
e_QmPortalProduceMode pmode;
e_QmPortalDqrrConsumeMode cmode;
#endif /* QM_CHECKING */
};
#define QM_DQRR_FLAG_RE 0x01 /* Stash ring entries */
#define QM_DQRR_FLAG_SE 0x02 /* Stash data */
/* MR state */
struct qm_mr {
struct qm_mr_entry *ring, *cursor;
uint8_t pi, ci, fill, ithresh, vbit;
#ifdef QM_CHECKING
e_QmPortalProduceMode pmode;
e_QmPortalMrConsumeMode cmode;
#endif /* QM_CHECKING */
};
/* MC state */
struct qm_mc {
struct qm_mc_command *cr;
struct qm_mc_result *rr;
uint8_t rridx, vbit;
#ifdef QM_CHECKING
enum {
/* Can be _mc_start()ed */
mc_idle,
/* Can be _mc_commit()ed or _mc_abort()ed */
mc_user,
/* Can only be _mc_retry()ed */
mc_hw
} state;
#endif /* QM_CHECKING */
};
/********************/
/* Portal structure */
/********************/
struct qm_portal {
/* In the non-QM_CHECKING case, everything up to and
* including 'mc' fits in a cacheline (yay!). The 'config' part is setup-only, so isn't a
* cause for a concern. In other words, don't rearrange this structure
* on a whim, there be dragons ... */
struct qm_addr addr;
struct qm_eqcr eqcr;
struct qm_dqrr dqrr;
struct qm_mr mr;
struct qm_mc mc;
struct qm_portal_config config;
t_Handle bind_lock;
/* Logical index (not cell-index) */
int index;
};
#endif /* __QMAN_PRIVATE_H */

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/*-
* Copyright (c) 2011 Semihalf.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef DFLAGS_H_
#define DFLAGS_H_
#include "opt_platform.h"
#include "events_mapping.h"
#if defined(P3041DS)
#define P3041
#elif defined(P2041RDB)
#define P2041
#elif defined(P5020DS)
#define P5020
#else
#define P5020
#endif
#define NCSW_PPC_CORE
#define NCSW_FREEBSD
/* Debugging */
#define DEBUG_ERRORS 1
#define DPAA_DEBUG 1
#if defined(DPAA_DEBUG)
#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_INFO
#else
#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING
#endif
/* Events */
#define REPORT_EVENTS 1
#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR
#endif /* DFLAGS_H_ */

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/*-
* Copyright (c) 2011 Semihalf.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef EVENTS_MAPPING_H_
#define EVENTS_MAPPING_H_
#define EV_RX_DISCARD_LEVEL REPORT_LEVEL_MINOR
#define EV_RX_ERROR_LEVEL REPORT_LEVEL_MINOR
#define EV_TX_ERROR_LEVEL REPORT_LEVEL_MINOR
#define EV_NO_BUFFERS_LEVEL REPORT_LEVEL_MAJOR
#define EV_NO_MB_FRAMES_LEVEL REPORT_LEVEL_MAJOR
#define EV_NO_SB_FRAMES_LEVEL REPORT_LEVEL_MAJOR
#define EV_TX_QUEUE_FULL_LEVEL REPORT_LEVEL_MINOR
#define EV_RX_QUEUE_FULL_LEVEL REPORT_LEVEL_MAJOR
#define EV_INTR_QUEUE_FULL_LEVEL REPORT_LEVEL_MINOR
#define EV_NO_DATA_BUFFER_LEVEL REPORT_LEVEL_MAJOR
#define EV_OBJ_POOL_EMPTY_LEVEL REPORT_LEVEL_MAJOR
#define EV_BUS_ERROR_LEVEL REPORT_LEVEL_CRITICAL
#define EV_PTP_TXTS_QUEUE_FULL_LEVEL REPORT_LEVEL_MAJOR
#define EV_PTP_RXTS_QUEUE_FULL_LEVEL REPORT_LEVEL_MAJOR
#endif /* EVENTS_MAPPING_H_ */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
@File error.c
@Description General errors and events reporting utilities.
*//***************************************************************************/
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
const char *dbgLevelStrings[] =
{
"CRITICAL"
,"MAJOR"
,"MINOR"
,"WARNING"
,"INFO"
,"TRACE"
};
const char *errTypeStrings[] =
{
"Invalid State" /* E_INVALID_STATE */
,"Invalid Operation" /* E_INVALID_OPERATION */
,"Unsupported Operation" /* E_NOT_SUPPORTED */
,"No Device" /* E_NO_DEVICE */
,"Invalid Handle" /* E_INVALID_HANDLE */
,"Invalid ID" /* E_INVALID_ID */
,"Unexpected NULL Pointer" /* E_NULL_POINTER */
,"Invalid Value" /* E_INVALID_VALUE */
,"Invalid Selection" /* E_INVALID_SELECTION */
,"Invalid Communication Mode" /* E_INVALID_COMM_MODE */
,"Invalid Byte Order" /* E_INVALID_BYTE_ORDER */
,"Invalid Memory Type" /* E_INVALID_MEMORY_TYPE */
,"Invalid Interrupt Queue" /* E_INVALID_INTR_QUEUE */
,"Invalid Priority" /* E_INVALID_PRIORITY */
,"Invalid Clock" /* E_INVALID_CLOCK */
,"Invalid Rate" /* E_INVALID_RATE */
,"Invalid Address" /* E_INVALID_ADDRESS */
,"Invalid Bus" /* E_INVALID_BUS */
,"Conflict In Bus Selection" /* E_BUS_CONFLICT */
,"Conflict In Settings" /* E_CONFLICT */
,"Incorrect Alignment" /* E_NOT_ALIGNED */
,"Value Out Of Range" /* E_NOT_IN_RANGE */
,"Invalid Frame" /* E_INVALID_FRAME */
,"Frame Is Empty" /* E_EMPTY_FRAME */
,"Buffer Is Empty" /* E_EMPTY_BUFFER */
,"Memory Allocation Failed" /* E_NO_MEMORY */
,"Resource Not Found" /* E_NOT_FOUND */
,"Resource Is Unavailable" /* E_NOT_AVAILABLE */
,"Resource Already Exists" /* E_ALREADY_EXISTS */
,"Resource Is Full" /* E_FULL */
,"Resource Is Empty" /* E_EMPTY */
,"Resource Is Busy" /* E_BUSY */
,"Resource Already Free" /* E_ALREADY_FREE */
,"Read Access Failed" /* E_READ_FAILED */
,"Write Access Failed" /* E_WRITE_FAILED */
,"Send Operation Failed" /* E_SEND_FAILED */
,"Receive Operation Failed" /* E_RECEIVE_FAILED */
,"Operation Timed Out" /* E_TIMEOUT */
};
#if (defined(REPORT_EVENTS) && (REPORT_EVENTS > 0))
const char *eventStrings[] =
{
"Rx Discard" /* EV_RX_DISCARD */
,"Rx Error" /* EV_RX_ERROR */
,"Tx Error" /* EV_TX_ERROR */
,"No Buffer Objects" /* EV_NO_BUFFERS */
,"No MB-Frame Objects" /* EV_NO_MB_FRAMES */
,"No SB-Frame Objects" /* EV_NO_SB_FRAMES */
,"Tx Queue Is Full" /* EV_TX_QUEUE_FULL */
,"Rx Queue Is Full" /* EV_RX_QUEUE_FULL */
,"Interrupts Queue Is Full" /* EV_INTR_QUEUE_FULL */
,"Data Buffer Is Unavailable" /* EV_NO_DATA_BUFFER */
,"Objects Pool Is Empty" /* EV_OBJ_POOL_EMPTY */
,"Illegal bus access" /* EV_BUS_ERROR */
,"PTP Tx Timestamps Queue Is Full" /* EV_PTP_TXTS_QUEUE_FULL */
,"PTP Rx Timestamps Queue Is Full" /* EV_PTP_RXTS_QUEUE_FULL */
};
#endif /* (defined(REPORT_EVENTS) && (REPORT_EVENTS > 0)) */
#endif /* (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0)) */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File list.c
@Description Implementation of list.
*//***************************************************************************/
#include "std_ext.h"
#include "list_ext.h"
void LIST_Append(t_List *p_NewList, t_List *p_Head)
{
t_List *p_First = NCSW_LIST_FIRST(p_NewList);
if (p_First != p_NewList)
{
t_List *p_Last = LIST_LAST(p_NewList);
t_List *p_Cur = NCSW_LIST_NEXT(p_Head);
NCSW_LIST_PREV(p_First) = p_Head;
NCSW_LIST_FIRST(p_Head) = p_First;
NCSW_LIST_NEXT(p_Last) = p_Cur;
LIST_LAST(p_Cur) = p_Last;
}
}
int LIST_NumOfObjs(t_List *p_List)
{
t_List *p_Tmp;
int numOfObjs = 0;
if (!LIST_IsEmpty(p_List))
LIST_FOR_EACH(p_Tmp, p_List)
numOfObjs++;
return numOfObjs;
}

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
#ifndef __MEM_H
#define __MEM_H
#include "error_ext.h"
#include "std_ext.h"
#include "list_ext.h"
#define __ERR_MODULE__ MODULE_MEM
/**************************************************************************//**
@Description Memory allocation owner.
*//***************************************************************************/
typedef enum e_MemAllocOwner
{
e_MEM_ALLOC_OWNER_LOCAL,
e_MEM_ALLOC_OWNER_LOCAL_SMART,
e_MEM_ALLOC_OWNER_EXTERNAL
} e_MemAllocOwner;
#ifdef DEBUG_MEM_LEAKS
/**************************************************************************//**
@Description MEM block information for leaks detection.
*//***************************************************************************/
typedef struct t_MemDbg
{
uintptr_t ownerAddress;
} t_MemDbg;
#endif /* DEBUG_MEM_LEAKS */
#endif /* __MEM_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "std_ext.h"
#include "xx_ext.h"
#include "memcpy_ext.h"
#ifdef CORE_8BIT_ACCESS_ERRATA
static void MY_MY_WRITE_UINT8(uint8_t *addr, uint8_t val)
{
uint32_t newAddr, newVal;
newAddr = (uint32_t)addr & ~0x3L;
switch ((uint32_t)addr%4)
{
case (0):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0x00ffffff) | (((uint32_t)val)<<24);
WRITE_UINT32(*(uint32_t*)newAddr, newVal);
break;
case (1):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0xff00ffff) | (((uint32_t)val)<<16);
WRITE_UINT32(*(uint32_t*)newAddr, newVal);
break;
case (2):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0xffff00ff) | (((uint32_t)val)<<8);
WRITE_UINT32(*(uint32_t*)newAddr, newVal);
break;
case (3):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0xffffff00) | val;
WRITE_UINT32(*(uint32_t*)newAddr, newVal);
break;
}
}
static uint8_t MY_MY_GET_UINT8(uint8_t *addr)
{
uint32_t newAddr, newVal=0;
newAddr = (uint32_t)addr & ~0x3L;
switch ((uint32_t)addr%4)
{
case (0):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0xff000000)>>24;
break;
case (1):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0x00ff0000)>>16;
break;
case (2):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0x0000ff00)>>8;
break;
case (3):
newVal = GET_UINT32(*(uint32_t*)newAddr);
newVal = (newVal & 0x000000ff);
break;
}
return (uint8_t)newVal;
}
#define MY_WRITE_UINT8(addr,val) MY_MY_WRITE_UINT8(&addr,val)
#define MY_GET_UINT8(addr) MY_MY_GET_UINT8(&addr)
#else
#define MY_WRITE_UINT8 WRITE_UINT8
#define MY_GET_UINT8 GET_UINT8
#endif /* CORE_8BIT_ACCESS_ERRATA */
void * MemCpy32(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint32_t lastWord;
uint32_t currWord;
uint32_t *p_Src32;
uint32_t *p_Dst32;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessary to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
*p_Dst8++ = *p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
*p_Dst8++ = *p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
rightAlign = 32 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
p_Src32 = (uint32_t*)(p_Src8);
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
*p_Dst32++ = *p_Src32++;
size -= 4;
}
p_Src8 = (uint8_t*)(p_Src32);
p_Dst8 = (uint8_t*)(p_Dst32);
}
else
{
/* source is not aligned (destination is aligned)*/
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
p_Dst32 = (uint32_t*)(p_Dst8);
lastWord = *p_Src32++;
while(size >> 3) /* size >= 8 */
{
currWord = *p_Src32;
*p_Dst32 = (lastWord << leftAlign) | (currWord >> rightAlign);
lastWord = currWord;
p_Src32++;
p_Dst32++;
size -= 4;
}
p_Dst8 = (uint8_t*)(p_Dst32);
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
*p_Dst8++ = *p_Src8++;
return pDst;
}
void * IO2IOCpy32(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint32_t lastWord;
uint32_t currWord;
uint32_t *p_Src32;
uint32_t *p_Dst32;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessary to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, MY_GET_UINT8(*p_Src8));
p_Dst8++;p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, MY_GET_UINT8(*p_Src8));
p_Dst8++;p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
rightAlign = 32 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
p_Src32 = (uint32_t*)(p_Src8);
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
WRITE_UINT32(*p_Dst32, GET_UINT32(*p_Src32));
p_Dst32++;p_Src32++;
size -= 4;
}
p_Src8 = (uint8_t*)(p_Src32);
p_Dst8 = (uint8_t*)(p_Dst32);
}
else
{
/* source is not aligned (destination is aligned)*/
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
p_Dst32 = (uint32_t*)(p_Dst8);
lastWord = GET_UINT32(*p_Src32);
p_Src32++;
while(size >> 3) /* size >= 8 */
{
currWord = GET_UINT32(*p_Src32);
WRITE_UINT32(*p_Dst32, (lastWord << leftAlign) | (currWord >> rightAlign));
lastWord = currWord;
p_Src32++;p_Dst32++;
size -= 4;
}
p_Dst8 = (uint8_t*)(p_Dst32);
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
{
MY_WRITE_UINT8(*p_Dst8, MY_GET_UINT8(*p_Src8));
p_Dst8++;p_Src8++;
}
return pDst;
}
void * Mem2IOCpy32(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint32_t lastWord;
uint32_t currWord;
uint32_t *p_Src32;
uint32_t *p_Dst32;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessary to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, *p_Src8);
p_Dst8++;p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, *p_Src8);
p_Dst8++;p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
rightAlign = 32 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
p_Src32 = (uint32_t*)(p_Src8);
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
WRITE_UINT32(*p_Dst32, *p_Src32);
p_Dst32++;p_Src32++;
size -= 4;
}
p_Src8 = (uint8_t*)(p_Src32);
p_Dst8 = (uint8_t*)(p_Dst32);
}
else
{
/* source is not aligned (destination is aligned)*/
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
p_Dst32 = (uint32_t*)(p_Dst8);
lastWord = *p_Src32++;
while(size >> 3) /* size >= 8 */
{
currWord = *p_Src32;
WRITE_UINT32(*p_Dst32, (lastWord << leftAlign) | (currWord >> rightAlign));
lastWord = currWord;
p_Src32++;p_Dst32++;
size -= 4;
}
p_Dst8 = (uint8_t*)(p_Dst32);
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
{
MY_WRITE_UINT8(*p_Dst8, *p_Src8);
p_Dst8++;p_Src8++;
}
return pDst;
}
void * IO2MemCpy32(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint32_t lastWord;
uint32_t currWord;
uint32_t *p_Src32;
uint32_t *p_Dst32;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessary to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 3) && size) /* (pSrc mod 4) > 0 and size > 0 */
{
*p_Dst8 = MY_GET_UINT8(*p_Src8);
p_Dst8++;p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
*p_Dst8 = MY_GET_UINT8(*p_Src8);
p_Dst8++;p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 3) << 3); /* leftAlign = (pSrc mod 4)*8 */
rightAlign = 32 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
p_Src32 = (uint32_t*)(p_Src8);
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
*p_Dst32 = GET_UINT32(*p_Src32);
p_Dst32++;p_Src32++;
size -= 4;
}
p_Src8 = (uint8_t*)(p_Src32);
p_Dst8 = (uint8_t*)(p_Dst32);
}
else
{
/* source is not aligned (destination is aligned)*/
p_Src32 = (uint32_t*)(p_Src8 - (leftAlign >> 3));
p_Dst32 = (uint32_t*)(p_Dst8);
lastWord = GET_UINT32(*p_Src32);
p_Src32++;
while(size >> 3) /* size >= 8 */
{
currWord = GET_UINT32(*p_Src32);
*p_Dst32 = (lastWord << leftAlign) | (currWord >> rightAlign);
lastWord = currWord;
p_Src32++;p_Dst32++;
size -= 4;
}
p_Dst8 = (uint8_t*)(p_Dst32);
p_Src8 = (uint8_t*)(p_Src32) - 4 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
{
*p_Dst8 = MY_GET_UINT8(*p_Src8);
p_Dst8++;p_Src8++;
}
return pDst;
}
void * MemCpy64(void* pDst,void* pSrc, uint32_t size)
{
uint32_t leftAlign;
uint32_t rightAlign;
uint64_t lastWord;
uint64_t currWord;
uint64_t *pSrc64;
uint64_t *pDst64;
uint8_t *p_Src8;
uint8_t *p_Dst8;
p_Src8 = (uint8_t*)(pSrc);
p_Dst8 = (uint8_t*)(pDst);
/* first copy byte by byte till the source first alignment
* this step is necessarily to ensure we do not even try to access
* data which is before the source buffer, hence it is not ours.
*/
while((PTR_TO_UINT(p_Src8) & 7) && size) /* (pSrc mod 8) > 0 and size > 0 */
{
*p_Dst8++ = *p_Src8++;
size--;
}
/* align destination (possibly disaligning source)*/
while((PTR_TO_UINT(p_Dst8) & 7) && size) /* (pDst mod 8) > 0 and size > 0 */
{
*p_Dst8++ = *p_Src8++;
size--;
}
/* dest is aligned and source is not necessarily aligned */
leftAlign = (uint32_t)((PTR_TO_UINT(p_Src8) & 7) << 3); /* leftAlign = (pSrc mod 8)*8 */
rightAlign = 64 - leftAlign;
if (leftAlign == 0)
{
/* source is also aligned */
pSrc64 = (uint64_t*)(p_Src8);
pDst64 = (uint64_t*)(p_Dst8);
while (size >> 3) /* size >= 8 */
{
*pDst64++ = *pSrc64++;
size -= 8;
}
p_Src8 = (uint8_t*)(pSrc64);
p_Dst8 = (uint8_t*)(pDst64);
}
else
{
/* source is not aligned (destination is aligned)*/
pSrc64 = (uint64_t*)(p_Src8 - (leftAlign >> 3));
pDst64 = (uint64_t*)(p_Dst8);
lastWord = *pSrc64++;
while(size >> 4) /* size >= 16 */
{
currWord = *pSrc64;
*pDst64 = (lastWord << leftAlign) | (currWord >> rightAlign);
lastWord = currWord;
pSrc64++;
pDst64++;
size -= 8;
}
p_Dst8 = (uint8_t*)(pDst64);
p_Src8 = (uint8_t*)(pSrc64) - 8 + (leftAlign >> 3);
}
/* complete the left overs */
while (size--)
*p_Dst8++ = *p_Src8++;
return pDst;
}
void * MemSet32(void* pDst, uint8_t val, uint32_t size)
{
uint32_t val32;
uint32_t *p_Dst32;
uint8_t *p_Dst8;
p_Dst8 = (uint8_t*)(pDst);
/* generate four 8-bit val's in 32-bit container */
val32 = (uint32_t) val;
val32 |= (val32 << 8);
val32 |= (val32 << 16);
/* align destination to 32 */
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
*p_Dst8++ = val;
size--;
}
/* 32-bit chunks */
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
*p_Dst32++ = val32;
size -= 4;
}
/* complete the leftovers */
p_Dst8 = (uint8_t*)(p_Dst32);
while (size--)
*p_Dst8++ = val;
return pDst;
}
void * IOMemSet32(void* pDst, uint8_t val, uint32_t size)
{
uint32_t val32;
uint32_t *p_Dst32;
uint8_t *p_Dst8;
p_Dst8 = (uint8_t*)(pDst);
/* generate four 8-bit val's in 32-bit container */
val32 = (uint32_t) val;
val32 |= (val32 << 8);
val32 |= (val32 << 16);
/* align destination to 32 */
while((PTR_TO_UINT(p_Dst8) & 3) && size) /* (pDst mod 4) > 0 and size > 0 */
{
MY_WRITE_UINT8(*p_Dst8, val);
p_Dst8++;
size--;
}
/* 32-bit chunks */
p_Dst32 = (uint32_t*)(p_Dst8);
while (size >> 2) /* size >= 4 */
{
WRITE_UINT32(*p_Dst32, val32);
p_Dst32++;
size -= 4;
}
/* complete the leftovers */
p_Dst8 = (uint8_t*)(p_Dst32);
while (size--)
{
MY_WRITE_UINT8(*p_Dst8, val);
p_Dst8++;
}
return pDst;
}
void * MemSet64(void* pDst, uint8_t val, uint32_t size)
{
uint64_t val64;
uint64_t *pDst64;
uint8_t *p_Dst8;
p_Dst8 = (uint8_t*)(pDst);
/* generate four 8-bit val's in 32-bit container */
val64 = (uint64_t) val;
val64 |= (val64 << 8);
val64 |= (val64 << 16);
val64 |= (val64 << 24);
val64 |= (val64 << 32);
/* align destination to 64 */
while((PTR_TO_UINT(p_Dst8) & 7) && size) /* (pDst mod 8) > 0 and size > 0 */
{
*p_Dst8++ = val;
size--;
}
/* 64-bit chunks */
pDst64 = (uint64_t*)(p_Dst8);
while (size >> 4) /* size >= 8 */
{
*pDst64++ = val64;
size -= 8;
}
/* complete the leftovers */
p_Dst8 = (uint8_t*)(pDst64);
while (size--)
*p_Dst8++ = val;
return pDst;
}
void MemDisp(uint8_t *p, int size)
{
uint32_t space = (uint32_t)(PTR_TO_UINT(p) & 0x3);
uint8_t *p_Limit;
if (space)
{
p_Limit = (p - space + 4);
XX_Print("0x%08X: ", (p - space));
while (space--)
{
XX_Print("--");
}
while (size && (p < p_Limit))
{
XX_Print("%02x", *(uint8_t*)p);
size--;
p++;
}
XX_Print(" ");
p_Limit += 12;
while ((size > 3) && (p < p_Limit))
{
XX_Print("%08x ", *(uint32_t*)p);
size -= 4;
p += 4;
}
XX_Print("\r\n");
}
while (size > 15)
{
XX_Print("0x%08X: %08x %08x %08x %08x\r\n",
p, *(uint32_t *)p, *(uint32_t *)(p + 4),
*(uint32_t *)(p + 8), *(uint32_t *)(p + 12));
size -= 16;
p += 16;
}
if (size)
{
XX_Print("0x%08X: ", p);
while (size > 3)
{
XX_Print("%08x ", *(uint32_t *)p);
size -= 4;
p += 4;
}
while (size)
{
XX_Print("%02x", *(uint8_t *)p);
size--;
p++;
}
XX_Print("\r\n");
}
}

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/****************************************************************
*
* File: mm.h
*
*
* Description:
* MM (Memory Management) object definitions.
* It also includes definitions of the Free Block, Busy Block
* and Memory Block structures used by the MM object.
*
****************************************************************/
#ifndef __MM_H
#define __MM_H
#include "mm_ext.h"
#define __ERR_MODULE__ MODULE_MM
#define MAKE_ALIGNED(addr, align) \
(((uint64_t)(addr) + ((align) - 1)) & (~(((uint64_t)align) - 1)))
/* t_MemBlock data stucutre defines parameters of the Memory Block */
typedef struct t_MemBlock
{
struct t_MemBlock *p_Next; /* Pointer to the next memory block */
uint64_t base; /* Base address of the memory block */
uint64_t end; /* End address of the memory block */
} t_MemBlock;
/* t_FreeBlock data stucutre defines parameters of the Free Block */
typedef struct t_FreeBlock
{
struct t_FreeBlock *p_Next; /* Pointer to the next free block */
uint64_t base; /* Base address of the block */
uint64_t end; /* End address of the block */
} t_FreeBlock;
/* t_BusyBlock data stucutre defines parameters of the Busy Block */
typedef struct t_BusyBlock
{
struct t_BusyBlock *p_Next; /* Pointer to the next free block */
uint64_t base; /* Base address of the block */
uint64_t end; /* End address of the block */
char name[MM_MAX_NAME_LEN]; /* That block of memory was allocated for
something specified by the Name */
} t_BusyBlock;
/* t_MM data structure defines parameters of the MM object */
typedef struct t_MM
{
t_MemBlock *memBlocks; /* List of memory blocks (Memory list) */
t_BusyBlock *busyBlocks; /* List of busy blocks (Busy list) */
t_FreeBlock *freeBlocks[MM_MAX_ALIGNMENT + 1];
/* Alignment lists of free blocks (Free lists) */
t_Handle h_Spinlock;
} t_MM;
#endif /* __MM_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
#include "error_ext.h"
#include "part_ext.h"
#include "std_ext.h"
#include "string_ext.h"
#include "mem_ext.h"
#include "mem.h"
#include "xx_ext.h"
#define PAD_ALIGNMENT(align, x) (((x)%(align)) ? ((align)-((x)%(align))) : 0)
#define ALIGN_BLOCK(p_Block, prefixSize, alignment) \
do { \
p_Block += (prefixSize); \
p_Block += PAD_ALIGNMENT((alignment), (uintptr_t)(p_Block)); \
} while (0)
#if defined(__GNUC__)
#define GET_CALLER_ADDR \
__asm__ ("mflr %0" : "=r" (callerAddr))
#elif defined(__MWERKS__)
/* NOTE: This implementation is only valid for CodeWarrior for PowerPC */
#define GET_CALLER_ADDR \
__asm__("add %0, 0, %0" : : "r" (callerAddr))
#endif /* defined(__GNUC__) */
/*****************************************************************************/
static __inline__ void * MemGet(t_MemorySegment *p_Mem)
{
uint8_t *p_Block;
/* check if there is an available block */
if (p_Mem->current == p_Mem->num)
{
p_Mem->getFailures++;
return NULL;
}
/* get the block */
p_Block = p_Mem->p_BlocksStack[p_Mem->current];
#ifdef DEBUG
p_Mem->p_BlocksStack[p_Mem->current] = NULL;
#endif /* DEBUG */
/* advance current index */
p_Mem->current++;
return (void *)p_Block;
}
/*****************************************************************************/
static __inline__ t_Error MemPut(t_MemorySegment *p_Mem, void *p_Block)
{
/* check if blocks stack is full */
if (p_Mem->current > 0)
{
/* decrease current index */
p_Mem->current--;
/* put the block */
p_Mem->p_BlocksStack[p_Mem->current] = (uint8_t *)p_Block;
return E_OK;
}
RETURN_ERROR(MAJOR, E_FULL, NO_MSG);
}
#ifdef DEBUG_MEM_LEAKS
/*****************************************************************************/
static t_Error InitMemDebugDatabase(t_MemorySegment *p_Mem)
{
p_Mem->p_MemDbg = (void *)XX_Malloc(sizeof(t_MemDbg) * p_Mem->num);
if (!p_Mem->p_MemDbg)
{
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory debug object"));
}
memset(p_Mem->p_MemDbg, ILLEGAL_BASE, sizeof(t_MemDbg) * p_Mem->num);
return E_OK;
}
/*****************************************************************************/
static t_Error DebugMemGet(t_Handle h_Mem, void *p_Block, uintptr_t ownerAddress)
{
t_MemorySegment *p_Mem = (t_MemorySegment *)h_Mem;
t_MemDbg *p_MemDbg = (t_MemDbg *)p_Mem->p_MemDbg;
uint32_t blockIndex;
ASSERT_COND(ownerAddress != ILLEGAL_BASE);
/* Find block num */
if (p_Mem->consecutiveMem)
{
blockIndex =
(((uint8_t *)p_Block - (p_Mem->p_Bases[0] + p_Mem->blockOffset)) / p_Mem->blockSize);
}
else
{
blockIndex = *(uint32_t *)((uint8_t *)p_Block - 4);
}
ASSERT_COND(blockIndex < p_Mem->num);
ASSERT_COND(p_MemDbg[blockIndex].ownerAddress == ILLEGAL_BASE);
p_MemDbg[blockIndex].ownerAddress = ownerAddress;
return E_OK;
}
/*****************************************************************************/
static t_Error DebugMemPut(t_Handle h_Mem, void *p_Block)
{
t_MemorySegment *p_Mem = (t_MemorySegment *)h_Mem;
t_MemDbg *p_MemDbg = (t_MemDbg *)p_Mem->p_MemDbg;
uint32_t blockIndex;
uint8_t *p_Temp;
/* Find block num */
if (p_Mem->consecutiveMem)
{
blockIndex =
(((uint8_t *)p_Block - (p_Mem->p_Bases[0] + p_Mem->blockOffset)) / p_Mem->blockSize);
if (blockIndex >= p_Mem->num)
{
RETURN_ERROR(MAJOR, E_INVALID_ADDRESS,
("Freed address (0x%08x) does not belong to this pool", p_Block));
}
}
else
{
blockIndex = *(uint32_t *)((uint8_t *)p_Block - 4);
if (blockIndex >= p_Mem->num)
{
RETURN_ERROR(MAJOR, E_INVALID_ADDRESS,
("Freed address (0x%08x) does not belong to this pool", p_Block));
}
/* Verify that the block matches the corresponding base */
p_Temp = p_Mem->p_Bases[blockIndex];
ALIGN_BLOCK(p_Temp, p_Mem->prefixSize, p_Mem->alignment);
if (p_Temp == p_Mem->p_Bases[blockIndex])
p_Temp += p_Mem->alignment;
if (p_Temp != p_Block)
{
RETURN_ERROR(MAJOR, E_INVALID_ADDRESS,
("Freed address (0x%08x) does not belong to this pool", p_Block));
}
}
if (p_MemDbg[blockIndex].ownerAddress == ILLEGAL_BASE)
{
RETURN_ERROR(MAJOR, E_ALREADY_FREE,
("Attempt to free unallocated address (0x%08x)", p_Block));
}
p_MemDbg[blockIndex].ownerAddress = (uintptr_t)ILLEGAL_BASE;
return E_OK;
}
#endif /* DEBUG_MEM_LEAKS */
/*****************************************************************************/
uint32_t MEM_ComputePartitionSize(uint32_t num,
uint16_t dataSize,
uint16_t prefixSize,
uint16_t postfixSize,
uint16_t alignment)
{
uint32_t blockSize = 0, pad1 = 0, pad2 = 0;
/* Make sure that the alignment is at least 4 */
if (alignment < 4)
{
alignment = 4;
}
pad1 = (uint32_t)PAD_ALIGNMENT(4, prefixSize);
/* Block size not including 2nd padding */
blockSize = pad1 + prefixSize + dataSize + postfixSize;
pad2 = PAD_ALIGNMENT(alignment, blockSize);
/* Block size including 2nd padding */
blockSize += pad2;
return ((num * blockSize) + alignment);
}
/*****************************************************************************/
t_Error MEM_Init(char name[],
t_Handle *p_Handle,
uint32_t num,
uint16_t dataSize,
uint16_t prefixSize,
uint16_t postfixSize,
uint16_t alignment)
{
uint8_t *p_Memory;
uint32_t allocSize;
t_Error errCode;
allocSize = MEM_ComputePartitionSize(num,
dataSize,
prefixSize,
postfixSize,
alignment);
p_Memory = (uint8_t *)XX_Malloc(allocSize);
if (!p_Memory)
{
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory segment"));
}
errCode = MEM_InitByAddress(name,
p_Handle,
num,
dataSize,
prefixSize,
postfixSize,
alignment,
p_Memory);
if (errCode != E_OK)
{
RETURN_ERROR(MAJOR, errCode, NO_MSG);
}
((t_MemorySegment *)(*p_Handle))->allocOwner = e_MEM_ALLOC_OWNER_LOCAL;
return E_OK;
}
/*****************************************************************************/
t_Error MEM_InitByAddress(char name[],
t_Handle *p_Handle,
uint32_t num,
uint16_t dataSize,
uint16_t prefixSize,
uint16_t postfixSize,
uint16_t alignment,
uint8_t *p_Memory)
{
t_MemorySegment *p_Mem;
uint32_t i, blockSize;
uint16_t alignPad, endPad;
uint8_t *p_Blocks;
/* prepare in case of error */
*p_Handle = NULL;
if (!p_Memory)
{
RETURN_ERROR(MAJOR, E_NULL_POINTER, ("Memory blocks"));
}
p_Blocks = p_Memory;
/* make sure that the alignment is at least 4 and power of 2 */
if (alignment < 4)
{
alignment = 4;
}
else if (!POWER_OF_2(alignment))
{
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Alignment (should be power of 2)"));
}
/* first allocate the segment descriptor */
p_Mem = (t_MemorySegment *)XX_Malloc(sizeof(t_MemorySegment));
if (!p_Mem)
{
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory segment structure"));
}
/* allocate the blocks stack */
p_Mem->p_BlocksStack = (uint8_t **)XX_Malloc(num * sizeof(uint8_t*));
if (!p_Mem->p_BlocksStack)
{
XX_Free(p_Mem);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory segment block pointers stack"));
}
/* allocate the blocks bases array */
p_Mem->p_Bases = (uint8_t **)XX_Malloc(sizeof(uint8_t*));
if (!p_Mem->p_Bases)
{
MEM_Free(p_Mem);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory segment base pointers array"));
}
memset(p_Mem->p_Bases, 0, sizeof(uint8_t*));
/* store info about this segment */
p_Mem->num = num;
p_Mem->current = 0;
p_Mem->dataSize = dataSize;
p_Mem->p_Bases[0] = p_Blocks;
p_Mem->getFailures = 0;
p_Mem->allocOwner = e_MEM_ALLOC_OWNER_EXTERNAL;
p_Mem->consecutiveMem = TRUE;
p_Mem->prefixSize = prefixSize;
p_Mem->postfixSize = postfixSize;
p_Mem->alignment = alignment;
/* store name */
strncpy(p_Mem->name, name, MEM_MAX_NAME_LENGTH-1);
p_Mem->h_Spinlock = XX_InitSpinlock();
if (!p_Mem->h_Spinlock)
{
MEM_Free(p_Mem);
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't create spinlock!"));
}
alignPad = (uint16_t)PAD_ALIGNMENT(4, prefixSize);
/* Make sure the entire size is a multiple of alignment */
endPad = (uint16_t)PAD_ALIGNMENT(alignment, (alignPad + prefixSize + dataSize + postfixSize));
/* The following manipulation places the data of block[0] in an aligned address,
since block size is aligned the following block datas will all be aligned */
ALIGN_BLOCK(p_Blocks, prefixSize, alignment);
blockSize = (uint32_t)(alignPad + prefixSize + dataSize + postfixSize + endPad);
/* initialize the blocks */
for (i=0; i < num; i++)
{
p_Mem->p_BlocksStack[i] = p_Blocks;
p_Blocks += blockSize;
}
/* return handle to caller */
*p_Handle = (t_Handle)p_Mem;
#ifdef DEBUG_MEM_LEAKS
{
t_Error errCode = InitMemDebugDatabase(p_Mem);
if (errCode != E_OK)
RETURN_ERROR(MAJOR, errCode, NO_MSG);
p_Mem->blockOffset = (uint32_t)(p_Mem->p_BlocksStack[0] - p_Mem->p_Bases[0]);
p_Mem->blockSize = blockSize;
}
#endif /* DEBUG_MEM_LEAKS */
return E_OK;
}
/*****************************************************************************/
t_Error MEM_InitSmart(char name[],
t_Handle *p_Handle,
uint32_t num,
uint16_t dataSize,
uint16_t prefixSize,
uint16_t postfixSize,
uint16_t alignment,
uint8_t memPartitionId,
bool consecutiveMem)
{
t_MemorySegment *p_Mem;
uint32_t i, blockSize;
uint16_t alignPad, endPad;
/* prepare in case of error */
*p_Handle = NULL;
/* make sure that size is always a multiple of 4 */
if (dataSize & 3)
{
dataSize &= ~3;
dataSize += 4;
}
/* make sure that the alignment is at least 4 and power of 2 */
if (alignment < 4)
{
alignment = 4;
}
else if (!POWER_OF_2(alignment))
{
RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Alignment (should be power of 2)"));
}
/* first allocate the segment descriptor */
p_Mem = (t_MemorySegment *)XX_Malloc(sizeof(t_MemorySegment));
if (!p_Mem)
{
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory segment structure"));
}
/* allocate the blocks stack */
p_Mem->p_BlocksStack = (uint8_t **)XX_Malloc(num * sizeof(uint8_t*));
if (!p_Mem->p_BlocksStack)
{
MEM_Free(p_Mem);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory segment block pointers stack"));
}
/* allocate the blocks bases array */
p_Mem->p_Bases = (uint8_t **)XX_Malloc((consecutiveMem ? 1 : num) * sizeof(uint8_t*));
if (!p_Mem->p_Bases)
{
MEM_Free(p_Mem);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory segment base pointers array"));
}
memset(p_Mem->p_Bases, 0, (consecutiveMem ? 1 : num) * sizeof(uint8_t*));
/* store info about this segment */
p_Mem->num = num;
p_Mem->current = 0;
p_Mem->dataSize = dataSize;
p_Mem->getFailures = 0;
p_Mem->allocOwner = e_MEM_ALLOC_OWNER_LOCAL_SMART;
p_Mem->consecutiveMem = consecutiveMem;
p_Mem->prefixSize = prefixSize;
p_Mem->postfixSize = postfixSize;
p_Mem->alignment = alignment;
p_Mem->h_Spinlock = XX_InitSpinlock();
if (!p_Mem->h_Spinlock)
{
MEM_Free(p_Mem);
RETURN_ERROR(MAJOR, E_INVALID_STATE, ("Can't create spinlock!"));
}
alignPad = (uint16_t)PAD_ALIGNMENT(4, prefixSize);
/* Make sure the entire size is a multiple of alignment */
endPad = (uint16_t)PAD_ALIGNMENT(alignment, alignPad + prefixSize + dataSize + postfixSize);
/* Calculate blockSize */
blockSize = (uint32_t)(alignPad + prefixSize + dataSize + postfixSize + endPad);
/* Now allocate the blocks */
if (p_Mem->consecutiveMem)
{
/* |alignment - 1| bytes at most will be discarded in the beginning of the
received segment for alignment reasons, therefore the allocation is of:
(alignment + (num * block size)). */
uint8_t *p_Blocks = (uint8_t *)
XX_MallocSmart((uint32_t)((num * blockSize) + alignment), memPartitionId, 1);
if (!p_Blocks)
{
MEM_Free(p_Mem);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory segment blocks"));
}
/* Store the memory segment address */
p_Mem->p_Bases[0] = p_Blocks;
/* The following manipulation places the data of block[0] in an aligned address,
since block size is aligned the following block datas will all be aligned.*/
ALIGN_BLOCK(p_Blocks, prefixSize, alignment);
/* initialize the blocks */
for (i = 0; i < num; i++)
{
p_Mem->p_BlocksStack[i] = p_Blocks;
p_Blocks += blockSize;
}
#ifdef DEBUG_MEM_LEAKS
p_Mem->blockOffset = (uint32_t)(p_Mem->p_BlocksStack[0] - p_Mem->p_Bases[0]);
p_Mem->blockSize = blockSize;
#endif /* DEBUG_MEM_LEAKS */
}
else
{
/* |alignment - 1| bytes at most will be discarded in the beginning of the
received segment for alignment reasons, therefore the allocation is of:
(alignment + block size). */
for (i = 0; i < num; i++)
{
uint8_t *p_Block = (uint8_t *)
XX_MallocSmart((uint32_t)(blockSize + alignment), memPartitionId, 1);
if (!p_Block)
{
MEM_Free(p_Mem);
RETURN_ERROR(MAJOR, E_NO_MEMORY, ("Memory segment blocks"));
}
/* Store the memory segment address */
p_Mem->p_Bases[i] = p_Block;
/* The following places the data of each block in an aligned address */
ALIGN_BLOCK(p_Block, prefixSize, alignment);
#ifdef DEBUG_MEM_LEAKS
/* Need 4 bytes before the meaningful bytes to store the block index.
We know we have them because alignment is at least 4 bytes. */
if (p_Block == p_Mem->p_Bases[i])
p_Block += alignment;
*(uint32_t *)(p_Block - 4) = i;
#endif /* DEBUG_MEM_LEAKS */
p_Mem->p_BlocksStack[i] = p_Block;
}
}
/* store name */
strncpy(p_Mem->name, name, MEM_MAX_NAME_LENGTH-1);
/* return handle to caller */
*p_Handle = (t_Handle)p_Mem;
#ifdef DEBUG_MEM_LEAKS
{
t_Error errCode = InitMemDebugDatabase(p_Mem);
if (errCode != E_OK)
RETURN_ERROR(MAJOR, errCode, NO_MSG);
}
#endif /* DEBUG_MEM_LEAKS */
return E_OK;
}
/*****************************************************************************/
void MEM_Free(t_Handle h_Mem)
{
t_MemorySegment *p_Mem = (t_MemorySegment*)h_Mem;
uint32_t num, i;
/* Check MEM leaks */
MEM_CheckLeaks(h_Mem);
if (p_Mem)
{
num = p_Mem->consecutiveMem ? 1 : p_Mem->num;
if (p_Mem->allocOwner == e_MEM_ALLOC_OWNER_LOCAL_SMART)
{
for (i=0; i < num; i++)
{
if (p_Mem->p_Bases[i])
{
XX_FreeSmart(p_Mem->p_Bases[i]);
}
}
}
else if (p_Mem->allocOwner == e_MEM_ALLOC_OWNER_LOCAL)
{
for (i=0; i < num; i++)
{
if (p_Mem->p_Bases[i])
{
XX_Free(p_Mem->p_Bases[i]);
}
}
}
if (p_Mem->h_Spinlock)
XX_FreeSpinlock(p_Mem->h_Spinlock);
if (p_Mem->p_Bases)
XX_Free(p_Mem->p_Bases);
if (p_Mem->p_BlocksStack)
XX_Free(p_Mem->p_BlocksStack);
#ifdef DEBUG_MEM_LEAKS
if (p_Mem->p_MemDbg)
XX_Free(p_Mem->p_MemDbg);
#endif /* DEBUG_MEM_LEAKS */
XX_Free(p_Mem);
}
}
/*****************************************************************************/
void * MEM_Get(t_Handle h_Mem)
{
t_MemorySegment *p_Mem = (t_MemorySegment *)h_Mem;
uint8_t *p_Block;
uint32_t intFlags;
#ifdef DEBUG_MEM_LEAKS
uintptr_t callerAddr = 0;
GET_CALLER_ADDR;
#endif /* DEBUG_MEM_LEAKS */
ASSERT_COND(h_Mem);
intFlags = XX_LockIntrSpinlock(p_Mem->h_Spinlock);
/* check if there is an available block */
if ((p_Block = (uint8_t *)MemGet(p_Mem)) == NULL)
{
XX_UnlockIntrSpinlock(p_Mem->h_Spinlock, intFlags);
return NULL;
}
#ifdef DEBUG_MEM_LEAKS
DebugMemGet(p_Mem, p_Block, callerAddr);
#endif /* DEBUG_MEM_LEAKS */
XX_UnlockIntrSpinlock(p_Mem->h_Spinlock, intFlags);
return (void *)p_Block;
}
/*****************************************************************************/
uint16_t MEM_GetN(t_Handle h_Mem, uint32_t num, void *array[])
{
t_MemorySegment *p_Mem = (t_MemorySegment *)h_Mem;
uint32_t availableBlocks;
register uint32_t i;
uint32_t intFlags;
#ifdef DEBUG_MEM_LEAKS
uintptr_t callerAddr = 0;
GET_CALLER_ADDR;
#endif /* DEBUG_MEM_LEAKS */
ASSERT_COND(h_Mem);
intFlags = XX_LockIntrSpinlock(p_Mem->h_Spinlock);
/* check how many blocks are available */
availableBlocks = (uint32_t)(p_Mem->num - p_Mem->current);
if (num > availableBlocks)
{
num = availableBlocks;
}
for (i=0; i < num; i++)
{
/* get pointer to block */
if ((array[i] = MemGet(p_Mem)) == NULL)
{
break;
}
#ifdef DEBUG_MEM_LEAKS
DebugMemGet(p_Mem, array[i], callerAddr);
#endif /* DEBUG_MEM_LEAKS */
}
XX_UnlockIntrSpinlock(p_Mem->h_Spinlock, intFlags);
return (uint16_t)i;
}
/*****************************************************************************/
t_Error MEM_Put(t_Handle h_Mem, void *p_Block)
{
t_MemorySegment *p_Mem = (t_MemorySegment *)h_Mem;
t_Error rc;
uint32_t intFlags;
ASSERT_COND(h_Mem);
intFlags = XX_LockIntrSpinlock(p_Mem->h_Spinlock);
/* check if blocks stack is full */
if ((rc = MemPut(p_Mem, p_Block)) != E_OK)
{
XX_UnlockIntrSpinlock(p_Mem->h_Spinlock, intFlags);
RETURN_ERROR(MAJOR, rc, NO_MSG);
}
#ifdef DEBUG_MEM_LEAKS
DebugMemPut(p_Mem, p_Block);
#endif /* DEBUG_MEM_LEAKS */
XX_UnlockIntrSpinlock(p_Mem->h_Spinlock, intFlags);
return E_OK;
}
#ifdef DEBUG_MEM_LEAKS
/*****************************************************************************/
void MEM_CheckLeaks(t_Handle h_Mem)
{
t_MemorySegment *p_Mem = (t_MemorySegment *)h_Mem;
t_MemDbg *p_MemDbg = (t_MemDbg *)p_Mem->p_MemDbg;
uint8_t *p_Block;
int i;
ASSERT_COND(h_Mem);
if (p_Mem->consecutiveMem)
{
for (i=0; i < p_Mem->num; i++)
{
if (p_MemDbg[i].ownerAddress != ILLEGAL_BASE)
{
/* Find the block address */
p_Block = ((p_Mem->p_Bases[0] + p_Mem->blockOffset) +
(i * p_Mem->blockSize));
XX_Print("MEM leak: 0x%08x, Caller address: 0x%08x\n",
p_Block, p_MemDbg[i].ownerAddress);
}
}
}
else
{
for (i=0; i < p_Mem->num; i++)
{
if (p_MemDbg[i].ownerAddress != ILLEGAL_BASE)
{
/* Find the block address */
p_Block = p_Mem->p_Bases[i];
ALIGN_BLOCK(p_Block, p_Mem->prefixSize, p_Mem->alignment);
if (p_Block == p_Mem->p_Bases[i])
p_Block += p_Mem->alignment;
XX_Print("MEM leak: 0x%08x, Caller address: 0x%08x\n",
p_Block, p_MemDbg[i].ownerAddress);
}
}
}
}
#endif /* DEBUG_MEM_LEAKS */

81
sys/contrib/ncsw/etc/sprint.c Normal file
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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*------------------------------------------------------*/
/* File: sprint.c */
/* */
/* Description: */
/* Debug routines (externals) */
/*------------------------------------------------------*/
#include "string_ext.h"
#include "stdlib_ext.h"
#include "ctype_ext.h"
#include "stdarg_ext.h"
#include "sprint_ext.h"
#include "std_ext.h"
#include "xx_ext.h"
int Sprint(char * buf, const char *fmt, ...)
{
va_list args;
int i;
va_start(args, fmt);
i=vsprintf(buf,fmt,args);
va_end(args);
return i;
}
int Snprint(char * buf, uint32_t size, const char *fmt, ...)
{
va_list args;
int i;
va_start(args, fmt);
i=vsnprintf(buf,size,fmt,args);
va_end(args);
return i;
}
#ifndef NCSW_VXWORKS
int Sscan(const char * buf, const char * fmt, ...)
{
va_list args;
int i;
va_start(args,fmt);
i = vsscanf(buf,fmt,args);
va_end(args);
return i;
}
#endif /* NCSW_VXWORKS */

688
sys/contrib/ncsw/inc/Peripherals/bm_ext.h Normal file
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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/******************************************************************************
@File bm_ext.h
@Description BM API
*//***************************************************************************/
#ifndef __BM_EXT_H
#define __BM_EXT_H
#include "error_ext.h"
#include "std_ext.h"
/**************************************************************************//**
@Group BM_grp Buffer Manager API
@Description BM API functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description This callback type is used when handling pool depletion entry/exit.
User provides this function. Driver invokes it.
@Param[in] h_App - User's application descriptor.
@Param[in] in - TRUE when entered depletion state
FALSE when exit the depletion state.
*//***************************************************************************/
typedef void (t_BmDepletionCallback)(t_Handle h_App, bool in);
/**************************************************************************//**
@Group BM_lib_grp BM common API
@Description BM common API functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description BM Exceptions
*//***************************************************************************/
typedef enum e_BmExceptions {
e_BM_EX_INVALID_COMMAND = 0 , /**< Invalid Command Verb Interrupt */
e_BM_EX_FBPR_THRESHOLD, /**< FBPR Low Watermark Interrupt. */
e_BM_EX_SINGLE_ECC, /**< Single Bit ECC Error Interrupt. */
e_BM_EX_MULTI_ECC /**< Multi Bit ECC Error Interrupt */
} e_BmExceptions;
/**************************************************************************//**
@Group BM_init_grp BM (common) Initialization Unit
@Description BM (common) Initialization Unit
@{
*//***************************************************************************/
/**************************************************************************//**
@Function t_BmExceptionsCallback
@Description Exceptions user callback routine, will be called upon an
exception passing the exception identification.
@Param[in] h_App - User's application descriptor.
@Param[in] exception - The exception.
*//***************************************************************************/
typedef void (t_BmExceptionsCallback) (t_Handle h_App,
e_BmExceptions exception);
/**************************************************************************//**
@Description structure representing BM initialization parameters
*//***************************************************************************/
typedef struct {
uint8_t guestId; /**< BM Partition Id */
uintptr_t baseAddress; /**< Bm base address (virtual).
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID). */
uint16_t liodn; /**< This value is attached to every transaction initiated by
BMan when accessing its private data structures
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID). */
uint32_t totalNumOfBuffers; /**< Total number of buffers
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID). */
uint32_t fbprMemPartitionId; /**< FBPR's mem partition id;
NOTE: The memory partition must be non-cacheable and no-coherent area.
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID). */
t_BmExceptionsCallback *f_Exception; /**< An application callback routine to handle exceptions.
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID). */
t_Handle h_App; /**< A handle to an application layer object; This handle will
be passed by the driver upon calling the above callbacks.
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID). */
int errIrq; /**< BM error interrupt line; NO_IRQ if interrupts not used.
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID). */
uint8_t partBpidBase; /**< The first buffer-pool-id dedicated to this partition.
NOTE: this parameter relevant only when working with multiple partitions. */
uint8_t partNumOfPools; /**< Number of Pools dedicated to this partition.
NOTE: this parameter relevant only when working with multiple partitions. */
} t_BmParam;
/**************************************************************************//**
@Function BM_Config
@Description Creates descriptor for the BM module and initializes the BM module.
The routine returns a handle (descriptor) to the BM object.
This descriptor must be passed as first parameter to all other
BM function calls.
@Param[in] p_BmParam - A pointer to data structure of parameters
@Return Handle to BM object, or NULL for Failure.
*//***************************************************************************/
t_Handle BM_Config(t_BmParam *p_BmParam);
/**************************************************************************//**
@Function BM_Init
@Description Initializes the BM module
@Param[in] h_Bm - A handle to the BM module
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following BM_Config().
*//***************************************************************************/
t_Error BM_Init(t_Handle h_Bm);
/**************************************************************************//**
@Function BM_Free
@Description Frees all resources that were assigned to BM module.
Calling this routine invalidates the descriptor.
@Param[in] h_Bm - A handle to the BM module
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error BM_Free(t_Handle h_Bm);
/**************************************************************************//**
@Group BM_advanced_init_grp BM (common) Advanced Configuration Unit
@Description Configuration functions used to change default values.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function BM_ConfigFbprThreshold
@Description Change the fbpr threshold from its default
configuration [0].
An interrupt if enables is asserted when the number of FBPRs is below this threshold.
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID).
@Param[in] h_Bm - A handle to the BM module
@Param[in] threshold - threshold value.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following BM_Config() and before BM_Init().
*//***************************************************************************/
t_Error BM_ConfigFbprThreshold(t_Handle h_Bm, uint32_t threshold);
/** @} */ /* end of BM_advanced_init_grp group */
/** @} */ /* end of BM_init_grp group */
/**************************************************************************//**
@Group BM_runtime_control_grp BM (common) Runtime Control Unit
@Description BM (common) Runtime control unit API functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description enum for defining BM counters
*//***************************************************************************/
typedef enum e_BmCounters {
e_BM_COUNTERS_FBPR = 0 /**< Total Free Buffer Proxy Record (FBPR) Free Pool Count in external memory */
} e_BmCounters;
/**************************************************************************//**
@Description structure for returning revision information
*//***************************************************************************/
typedef struct t_BmRevisionInfo {
uint8_t majorRev; /**< Major revision */
uint8_t minorRev; /**< Minor revision */
} t_BmRevisionInfo;
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
/**************************************************************************//**
@Function BM_DumpRegs
@Description Dumps all BM registers
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID).
@Param[in] h_Bm A handle to an BM Module.
@Return E_OK on success;
@Cautions Allowed only after BM_Init().
*//***************************************************************************/
t_Error BM_DumpRegs(t_Handle h_Bm);
#endif /* (defined(DEBUG_ERRORS) && ... */
/**************************************************************************//**
@Function BM_SetException
@Description Calling this routine enables/disables the specified exception.
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID).
@Param[in] h_Bm - A handle to the BM Module.
@Param[in] exception - The exception to be selected.
@Param[in] enable - TRUE to enable interrupt, FALSE to mask it.
@Cautions Allowed only following BM_Init().
*//***************************************************************************/
t_Error BM_SetException(t_Handle h_Bm, e_BmExceptions exception, bool enable);
/**************************************************************************//**
@Function BM_ErrorIsr
@Description BM interrupt-service-routine for errors.
NOTE: this parameter relevant only for BM in master mode ('guestId'=NCSW_MASTER_ID).
@Param[in] h_Bm - A handle to the BM Module.
@Cautions Allowed only following BM_Init().
*//***************************************************************************/
void BM_ErrorIsr(t_Handle h_Bm);
/**************************************************************************//**
@Function BM_GetCounter
@Description Reads one of the BM counters.
@Param[in] h_Bm - A handle to the BM Module.
@Param[in] counter - The requested counter.
@Return Counter's current value.
*//***************************************************************************/
uint32_t BM_GetCounter(t_Handle h_Bm, e_BmCounters counter);
/**************************************************************************//**
@Function BM_GetRevision
@Description Returns the BM revision
@Param[in] h_Bm A handle to a BM Module.
@Param[out] p_BmRevisionInfo A structure of revision information parameters.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following QM_Init().
*//***************************************************************************/
t_Error BM_GetRevision(t_Handle h_Bm, t_BmRevisionInfo *p_BmRevisionInfo);
/** @} */ /* end of BM_runtime_control_grp group */
/** @} */ /* end of BM_lib_grp group */
/**************************************************************************//**
@Group BM_portal_grp BM-Portal API
@Description BM-Portal API functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group BM_portal_init_grp BM-Portal Initialization Unit
@Description BM-Portal Initialization Unit
@{
*//***************************************************************************/
/**************************************************************************//**
@Description structure representing BM Portal initialization parameters
*//***************************************************************************/
typedef struct {
uintptr_t ceBaseAddress; /**< Cache-enabled base address (virtual) */
uintptr_t ciBaseAddress; /**< Cache-inhibited base address (virtual) */
t_Handle h_Bm; /**< Bm Handle */
e_DpaaSwPortal swPortalId; /**< Portal id */
int irq; /**< portal interrupt line; NO_IRQ if interrupts not used */
} t_BmPortalParam;
/**************************************************************************//**
@Function BM_PORTAL_Config
@Description Creates descriptor for the BM Portal;
The routine returns a handle (descriptor) to a BM-Portal object;
This descriptor must be passed as first parameter to all other
BM-Portal function calls.
No actual initialization or configuration of QM-Portal hardware is
done by this routine.
@Param[in] p_BmPortalParam - Pointer to data structure of parameters
@Retval Handle to a BM-Portal object, or NULL for Failure.
*//***************************************************************************/
t_Handle BM_PORTAL_Config(t_BmPortalParam *p_BmPortalParam);
/**************************************************************************//**
@Function BM_PORTAL_Init
@Description Initializes a BM-Portal module
@Param[in] h_BmPortal - A handle to a BM-Portal module
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error BM_PORTAL_Init(t_Handle h_BmPortal);
/**************************************************************************//**
@Function BM_PortalFree
@Description Frees all resources that were assigned to BM Portal module.
Calling this routine invalidates the descriptor.
@Param[in] h_BmPortal - BM Portal module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error BM_PORTAL_Free(t_Handle h_BmPortal);
/**************************************************************************//**
@Function BM_PORTAL_ConfigMemAttr
@Description Change the memory attributes
from its default configuration [MEMORY_ATTR_CACHEABLE].
@Param[in] h_BmPortal - A handle to a BM-Portal module
@Param[in] hwExtStructsMemAttr - memory attributes (cache/non-cache, etc.)
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following BM_PORTAL_Config() and before BM_PORTAL_Init().
*//***************************************************************************/
t_Error BM_PORTAL_ConfigMemAttr(t_Handle h_BmPortal, uint32_t hwExtStructsMemAttr);
/** @} */ /* end of BM_portal_init_grp group */
/** @} */ /* end of BM_portal_grp group */
/**************************************************************************//**
@Group BM_pool_grp BM-Pool API
@Description BM-Pool API functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group BM_pool_init_grp BM-Pool Initialization Unit
@Description BM-Pool Initialization Unit
@{
*//***************************************************************************/
/**************************************************************************//**
@Collection BM Pool Depletion Thresholds macros
The thresholds are represent by an array of size MAX_DEPLETION_THRESHOLDS
Use the following macros to access the appropriate location in the array.
*//***************************************************************************/
#define BM_POOL_DEP_THRESH_SW_ENTRY 0
#define BM_POOL_DEP_THRESH_SW_EXIT 1
#define BM_POOL_DEP_THRESH_HW_ENTRY 2
#define BM_POOL_DEP_THRESH_HW_EXIT 3
#define MAX_DEPLETION_THRESHOLDS 4
/* @} */
/**************************************************************************//**
@Description structure representing BM Pool initialization parameters
*//***************************************************************************/
typedef struct {
t_Handle h_Bm; /**< A handle to a BM Module. */
t_Handle h_BmPortal; /**< A handle to a BM Portal Module.
will be used only for Init and Free routines.
NOTE: if NULL, assuming affinity */
uint32_t numOfBuffers; /**< Number of buffers use by this pool
NOTE: If zero, empty pool buffer is created. */
t_BufferPoolInfo bufferPoolInfo; /**< Data buffers pool information */
t_Handle h_App; /**< opaque user value passed as a parameter to callbacks */
bool shadowMode; /**< If TRUE, numOfBuffers will be set to '0'. */
uint8_t bpid; /**< index of the shadow buffer pool (0-BM_MAX_NUM_OF_POOLS).
valid only if shadowMode='TRUE'. */
} t_BmPoolParam;
/**************************************************************************//**
@Function BM_POOL_Config
@Description Creates descriptor for the BM Pool;
The routine returns a handle (descriptor) to the BM Pool object.
@Param[in] p_BmPoolParam - A pointer to data structure of parameters
@Return Handle to BM Portal object, or NULL for Failure.
*//***************************************************************************/
t_Handle BM_POOL_Config(t_BmPoolParam *p_BmPoolParam);
/**************************************************************************//**
@Function BM_POOL_Init
@Description Initializes a BM-Pool module
@Param[in] h_BmPool - A handle to a BM-Pool module
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error BM_POOL_Init(t_Handle h_BmPool);
/**************************************************************************//**
@Function BM_PoolFree
@Description Frees all resources that were assigned to BM Pool module.
Calling this routine invalidates the descriptor.
@Param[in] h_BmPool - BM Pool module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error BM_POOL_Free(t_Handle h_BmPool);
/**************************************************************************//**
@Function BM_POOL_ConfigBpid
@Description Config a specific pool id rather than dynamic pool id.
@Param[in] h_BmPool - A handle to a BM-Pool module
@Param[in] bpid - index of the buffer pool (0-BM_MAX_NUM_OF_POOLS).
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following BM_POOL_Config() and before BM_POOL_Init().
*//***************************************************************************/
t_Error BM_POOL_ConfigBpid(t_Handle h_BmPool, uint8_t bpid);
/**************************************************************************//**
@Function BM_POOL_ConfigDepletion
@Description Config depletion-entry/exit thresholds and callback.
@Param[in] h_BmPool - A handle to a BM-Pool module
@Param[in] f_Depletion - depletion-entry/exit callback.
@Param[in] thresholds - depletion-entry/exit thresholds.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following BM_POOL_Config() and before BM_POOL_Init();
Allowed only if shadowMode='FALSE'.
Allowed only if BM in master mode ('guestId'=NCSW_MASTER_ID), or
the BM is in guest mode BUT than this routine will invoke IPC
call to the master.
*//***************************************************************************/
t_Error BM_POOL_ConfigDepletion(t_Handle h_BmPool,
t_BmDepletionCallback *f_Depletion,
uint32_t thresholds[MAX_DEPLETION_THRESHOLDS]);
/**************************************************************************//**
@Function BM_POOL_ConfigStockpile
@Description Config software stockpile.
@Param[in] h_BmPool - A handle to a BM-Pool module
@Param[in] maxBuffers - the software data structure size saved for stockpile;
when reached this value, release to hw command performed.
@Param[in] minBuffers - if current capacity is equal or lower then this value,
acquire from hw command performed.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following BM_POOL_Config() and before BM_POOL_Init().
*//***************************************************************************/
t_Error BM_POOL_ConfigStockpile(t_Handle h_BmPool, uint16_t maxBuffers, uint16_t minBuffers);
/**************************************************************************//**
@Function BM_POOL_ConfigBuffContextMode
@Description Config the BM pool to set/unset buffer-context
@Param[in] h_BmPool - A handle to a BM-Pool module
@Param[in] en - enable/disable buffer context mode
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following BM_POOL_Config() and before BM_POOL_Init().
*//***************************************************************************/
t_Error BM_POOL_ConfigBuffContextMode(t_Handle h_BmPool, bool en);
/** @} */ /* end of BM_pool_init_grp group */
/**************************************************************************//**
@Group BM_pool_runtime_control_grp BM-Pool Runtime Control Unit
@Description BM-Pool Runtime control unit API functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description enum for defining BM Pool counters
*//***************************************************************************/
typedef enum e_BmPoolCounters {
e_BM_POOL_COUNTERS_CONTENT = 0, /**< number of free buffers for a particular pool */
e_BM_POOL_COUNTERS_SW_DEPLETION, /**< number of times pool entered sw depletion */
e_BM_POOL_COUNTERS_HW_DEPLETION /**< number of times pool entered hw depletion */
} e_BmPoolCounters;
/**************************************************************************//**
@Function BM_POOL_GetId
@Description return a buffer pool id.
@Param[in] h_BmPool - A handle to a BM-pool
@Return Pool ID.
*//***************************************************************************/
uint8_t BM_POOL_GetId(t_Handle h_BmPool);
/**************************************************************************//**
@Function BM_POOL_GetBufferSize
@Description returns the pool's buffer size.
@Param[in] h_BmPool - A handle to a BM-pool
@Return pool's buffer size.
*//***************************************************************************/
uint16_t BM_POOL_GetBufferSize(t_Handle h_BmPool);
/**************************************************************************//**
@Function BM_POOL_GetBufferContext
@Description Returns the user's private context that
should be associated with the buffer.
@Param[in] h_BmPool - A handle to a BM-pool
@Param[in] p_Buff - A Pointer to the buffer
@Return user's private context.
*//***************************************************************************/
t_Handle BM_POOL_GetBufferContext(t_Handle h_BmPool, void *p_Buff);
/**************************************************************************//**
@Function BM_POOL_PhysToVirt
@Description Translates a physical address to the matching virtual address.
@Param[in] h_BmPool - A handle to a BM-pool
@Param[in] addr - The physical address to translate
@Return Virtual address.
*//***************************************************************************/
void * BM_POOL_PhysToVirt(t_Handle h_BmPool, physAddress_t addr);
/**************************************************************************//**
@Function BM_POOL_VirtToPhys
@Description Translates a virtual address to the matching physical address.
@Param[in] h_BmPool - A handle to a BM-pool
@Param[in] addr - The virtual address to translate
@Return Physical address.
*//***************************************************************************/
physAddress_t BM_POOL_VirtToPhys(t_Handle h_BmPool, void *addr);
/**************************************************************************//**
@Function BM_POOL_GetCounter
@Description Reads one of the BM Pool counters.
@Param[in] h_BmPool - A handle to a BM-pool
@Param[in] counter - The requested counter.
@Return Counter's current value.
*//***************************************************************************/
uint32_t BM_POOL_GetCounter(t_Handle h_BmPool, e_BmPoolCounters counter);
/** @} */ /* end of BM_pool_runtime_control_grp group */
/**************************************************************************//**
@Group BM_pool_runtime_data_grp BM-Pool Runtime Data Unit
@Description BM-Pool Runtime data unit API functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function BM_POOL_GetBuf
@Description Allocate buffer from a buffer pool.
@Param[in] h_BmPool - A handle to a BM-pool
@Param[in] h_BmPortal - A handle to a BM Portal Module;
NOTE : if NULL, assuming affinity.
@Return A Pointer to the allocated buffer.
*//***************************************************************************/
void * BM_POOL_GetBuf(t_Handle h_BmPool, t_Handle h_BmPortal);
/**************************************************************************//**
@Function BM_POOL_PutBuf
@Description Deallocate buffer to a buffer pool.
@Param[in] h_BmPool - A handle to a BM-pool
@Param[in] h_BmPortal - A handle to a BM Portal Module;
NOTE : if NULL, assuming affinity.
@Param[in] p_Buff - A Pointer to the buffer.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error BM_POOL_PutBuf(t_Handle h_BmPool, t_Handle h_BmPortal, void *p_Buff);
/**************************************************************************//**
@Function BM_POOL_FillBufs
@Description Fill a BM pool with new buffers.
@Param[in] h_BmPool - A handle to a BM-pool
@Param[in] h_BmPortal - A handle to a BM Portal Module;
NOTE : if NULL, assuming affinity.
@Param[in] numBufs - How many buffers to fill into the pool.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error BM_POOL_FillBufs(t_Handle h_BmPool, t_Handle h_BmPortal, uint32_t numBufs);
/** @} */ /* end of BM_pool_runtime_data_grp group */
/** @} */ /* end of BM_pool_grp group */
/** @} */ /* end of BM_grp group */
#endif /* __BM_EXT_H */

363
sys/contrib/ncsw/inc/Peripherals/crc_mac_addr_ext.h Normal file
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@ -0,0 +1,363 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*------------------------------------------------------*/
/* */
/* File: crc_mac_addr_ext.h */
/* */
/* Description: */
/* Define a macro that calculate the crc value of */
/* an Ethernet MAC address (48 bitd address */
/*------------------------------------------------------*/
#ifndef __crc_mac_addr_ext_h
#define __crc_mac_addr_ext_h
#include "std_ext.h"
static uint32_t crc_table[256] =
{
0x00000000,
0x77073096,
0xee0e612c,
0x990951ba,
0x076dc419,
0x706af48f,
0xe963a535,
0x9e6495a3,
0x0edb8832,
0x79dcb8a4,
0xe0d5e91e,
0x97d2d988,
0x09b64c2b,
0x7eb17cbd,
0xe7b82d07,
0x90bf1d91,
0x1db71064,
0x6ab020f2,
0xf3b97148,
0x84be41de,
0x1adad47d,
0x6ddde4eb,
0xf4d4b551,
0x83d385c7,
0x136c9856,
0x646ba8c0,
0xfd62f97a,
0x8a65c9ec,
0x14015c4f,
0x63066cd9,
0xfa0f3d63,
0x8d080df5,
0x3b6e20c8,
0x4c69105e,
0xd56041e4,
0xa2677172,
0x3c03e4d1,
0x4b04d447,
0xd20d85fd,
0xa50ab56b,
0x35b5a8fa,
0x42b2986c,
0xdbbbc9d6,
0xacbcf940,
0x32d86ce3,
0x45df5c75,
0xdcd60dcf,
0xabd13d59,
0x26d930ac,
0x51de003a,
0xc8d75180,
0xbfd06116,
0x21b4f4b5,
0x56b3c423,
0xcfba9599,
0xb8bda50f,
0x2802b89e,
0x5f058808,
0xc60cd9b2,
0xb10be924,
0x2f6f7c87,
0x58684c11,
0xc1611dab,
0xb6662d3d,
0x76dc4190,
0x01db7106,
0x98d220bc,
0xefd5102a,
0x71b18589,
0x06b6b51f,
0x9fbfe4a5,
0xe8b8d433,
0x7807c9a2,
0x0f00f934,
0x9609a88e,
0xe10e9818,
0x7f6a0dbb,
0x086d3d2d,
0x91646c97,
0xe6635c01,
0x6b6b51f4,
0x1c6c6162,
0x856530d8,
0xf262004e,
0x6c0695ed,
0x1b01a57b,
0x8208f4c1,
0xf50fc457,
0x65b0d9c6,
0x12b7e950,
0x8bbeb8ea,
0xfcb9887c,
0x62dd1ddf,
0x15da2d49,
0x8cd37cf3,
0xfbd44c65,
0x4db26158,
0x3ab551ce,
0xa3bc0074,
0xd4bb30e2,
0x4adfa541,
0x3dd895d7,
0xa4d1c46d,
0xd3d6f4fb,
0x4369e96a,
0x346ed9fc,
0xad678846,
0xda60b8d0,
0x44042d73,
0x33031de5,
0xaa0a4c5f,
0xdd0d7cc9,
0x5005713c,
0x270241aa,
0xbe0b1010,
0xc90c2086,
0x5768b525,
0x206f85b3,
0xb966d409,
0xce61e49f,
0x5edef90e,
0x29d9c998,
0xb0d09822,
0xc7d7a8b4,
0x59b33d17,
0x2eb40d81,
0xb7bd5c3b,
0xc0ba6cad,
0xedb88320,
0x9abfb3b6,
0x03b6e20c,
0x74b1d29a,
0xead54739,
0x9dd277af,
0x04db2615,
0x73dc1683,
0xe3630b12,
0x94643b84,
0x0d6d6a3e,
0x7a6a5aa8,
0xe40ecf0b,
0x9309ff9d,
0x0a00ae27,
0x7d079eb1,
0xf00f9344,
0x8708a3d2,
0x1e01f268,
0x6906c2fe,
0xf762575d,
0x806567cb,
0x196c3671,
0x6e6b06e7,
0xfed41b76,
0x89d32be0,
0x10da7a5a,
0x67dd4acc,
0xf9b9df6f,
0x8ebeeff9,
0x17b7be43,
0x60b08ed5,
0xd6d6a3e8,
0xa1d1937e,
0x38d8c2c4,
0x4fdff252,
0xd1bb67f1,
0xa6bc5767,
0x3fb506dd,
0x48b2364b,
0xd80d2bda,
0xaf0a1b4c,
0x36034af6,
0x41047a60,
0xdf60efc3,
0xa867df55,
0x316e8eef,
0x4669be79,
0xcb61b38c,
0xbc66831a,
0x256fd2a0,
0x5268e236,
0xcc0c7795,
0xbb0b4703,
0x220216b9,
0x5505262f,
0xc5ba3bbe,
0xb2bd0b28,
0x2bb45a92,
0x5cb36a04,
0xc2d7ffa7,
0xb5d0cf31,
0x2cd99e8b,
0x5bdeae1d,
0x9b64c2b0,
0xec63f226,
0x756aa39c,
0x026d930a,
0x9c0906a9,
0xeb0e363f,
0x72076785,
0x05005713,
0x95bf4a82,
0xe2b87a14,
0x7bb12bae,
0x0cb61b38,
0x92d28e9b,
0xe5d5be0d,
0x7cdcefb7,
0x0bdbdf21,
0x86d3d2d4,
0xf1d4e242,
0x68ddb3f8,
0x1fda836e,
0x81be16cd,
0xf6b9265b,
0x6fb077e1,
0x18b74777,
0x88085ae6,
0xff0f6a70,
0x66063bca,
0x11010b5c,
0x8f659eff,
0xf862ae69,
0x616bffd3,
0x166ccf45,
0xa00ae278,
0xd70dd2ee,
0x4e048354,
0x3903b3c2,
0xa7672661,
0xd06016f7,
0x4969474d,
0x3e6e77db,
0xaed16a4a,
0xd9d65adc,
0x40df0b66,
0x37d83bf0,
0xa9bcae53,
0xdebb9ec5,
0x47b2cf7f,
0x30b5ffe9,
0xbdbdf21c,
0xcabac28a,
0x53b39330,
0x24b4a3a6,
0xbad03605,
0xcdd70693,
0x54de5729,
0x23d967bf,
0xb3667a2e,
0xc4614ab8,
0x5d681b02,
0x2a6f2b94,
0xb40bbe37,
0xc30c8ea1,
0x5a05df1b,
0x2d02ef8d
};
#define GET_MAC_ADDR_CRC(addr, crc) \
{ \
uint32_t i; \
uint8_t data; \
\
/* CRC calculation */ \
crc = 0xffffffff; \
for (i=0; i < 6; i++) \
{ \
data = (uint8_t)(addr >> ((5-i)*8)); \
crc = crc^data; \
crc = crc_table[crc&0xff] ^ (crc>>8); \
} \
} \
/* Define a macro for getting the mirrored value of */
/* a byte size number. (0x11010011 --> 0x11001011) */
/* Sometimes the mirrored value of the CRC is required */
static __inline__ uint8_t GetMirror(uint8_t n)
{
uint8_t mirror[16] =
{
0x00,
0x08,
0x04,
0x0c,
0x02,
0x0a,
0x06,
0x0e,
0x01,
0x09,
0x05,
0x0d,
0x03,
0x0b,
0x07,
0x0f
};
return ((uint8_t)(((mirror[n & 0x0f] << 4) | (mirror[n >> 4]))));
}
static __inline__ uint32_t GetMirror32(uint32_t n)
{
return (((uint32_t)GetMirror((uint8_t)(n))<<24) |
((uint32_t)GetMirror((uint8_t)(n>>8))<<16) |
((uint32_t)GetMirror((uint8_t)(n>>16))<<8) |
((uint32_t)GetMirror((uint8_t)(n>>24))));
}
#define MIRROR GetMirror
#define MIRROR_32 GetMirror32
#endif /* __crc_mac_addr_ext_h */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File dpaa_ext.h
@Description DPAA Application Programming Interface.
*//***************************************************************************/
#ifndef __DPAA_EXT_H
#define __DPAA_EXT_H
#include "std_ext.h"
#include "error_ext.h"
/**************************************************************************//**
@Group DPAA_grp Data Path Acceleration Architecture API
@Description DPAA API functions, definitions and enums.
@{
*//***************************************************************************/
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
/**************************************************************************//**
@Description Frame descriptor
*//***************************************************************************/
typedef _Packed struct t_DpaaFD {
volatile uint32_t id; /**< FD id */
volatile uint32_t addrl; /**< Data Address */
volatile uint32_t length; /**< Frame length */
volatile uint32_t status; /**< FD status */
} _PackedType t_DpaaFD;
/**************************************************************************//**
@Description enum for defining frame format
*//***************************************************************************/
typedef enum e_DpaaFDFormatType {
e_DPAA_FD_FORMAT_TYPE_SHORT_SBSF = 0x0, /**< Simple frame Single buffer; Offset and
small length (9b OFFSET, 20b LENGTH) */
e_DPAA_FD_FORMAT_TYPE_LONG_SBSF = 0x2, /**< Simple frame, single buffer; big length
(29b LENGTH ,No OFFSET) */
e_DPAA_FD_FORMAT_TYPE_SHORT_MBSF = 0x4, /**< Simple frame, Scatter Gather table; Offset
and small length (9b OFFSET, 20b LENGTH) */
e_DPAA_FD_FORMAT_TYPE_LONG_MBSF = 0x6, /**< Simple frame, Scatter Gather table;
big length (29b LENGTH ,No OFFSET) */
e_DPAA_FD_FORMAT_TYPE_COMPOUND = 0x1, /**< Compound Frame (29b CONGESTION-WEIGHT
No LENGTH or OFFSET) */
e_DPAA_FD_FORMAT_TYPE_DUMMY
} e_DpaaFDFormatType;
/**************************************************************************//**
@Collection Frame descriptor macros
*//***************************************************************************/
#define DPAA_FD_DD_MASK 0xc0000000 /**< FD DD field mask */
#define DPAA_FD_PID_MASK 0x3f000000 /**< FD PID field mask */
#define DPAA_FD_ELIODN_MASK 0x0000f000 /**< FD ELIODN field mask */
#define DPAA_FD_BPID_MASK 0x00ff0000 /**< FD BPID field mask */
#define DPAA_FD_ADDRH_MASK 0x000000ff /**< FD ADDRH field mask */
#define DPAA_FD_ADDRL_MASK 0xffffffff /**< FD ADDRL field mask */
#define DPAA_FD_FORMAT_MASK 0xe0000000 /**< FD FORMAT field mask */
#define DPAA_FD_OFFSET_MASK 0x1ff00000 /**< FD OFFSET field mask */
#define DPAA_FD_LENGTH_MASK 0x000fffff /**< FD LENGTH field mask */
#define DPAA_FD_GET_DD(fd) ((((t_DpaaFD *)fd)->id & DPAA_FD_DD_MASK) >> (31-1)) /**< Macro to get FD DD field */
#define DPAA_FD_GET_PID(fd) (((((t_DpaaFD *)fd)->id & DPAA_FD_PID_MASK) >> (31-7)) | \
((((t_DpaaFD *)fd)->id & DPAA_FD_ELIODN_MASK) >> (31-19-6))) /**< Macro to get FD PID field */
#define DPAA_FD_GET_BPID(fd) ((((t_DpaaFD *)fd)->id & DPAA_FD_BPID_MASK) >> (31-15)) /**< Macro to get FD BPID field */
#define DPAA_FD_GET_ADDRH(fd) (((t_DpaaFD *)fd)->id & DPAA_FD_ADDRH_MASK) /**< Macro to get FD ADDRH field */
#define DPAA_FD_GET_ADDRL(fd) ((t_DpaaFD *)fd)->addrl /**< Macro to get FD ADDRL field */
#define DPAA_FD_GET_PHYS_ADDR(fd) ((physAddress_t)(((uint64_t)DPAA_FD_GET_ADDRH(fd) << 32) | (uint64_t)DPAA_FD_GET_ADDRL(fd))) /**< Macro to get FD ADDR field */
#define DPAA_FD_GET_FORMAT(fd) ((((t_DpaaFD *)fd)->length & DPAA_FD_FORMAT_MASK) >> (31-2)) /**< Macro to get FD FORMAT field */
#define DPAA_FD_GET_OFFSET(fd) ((((t_DpaaFD *)fd)->length & DPAA_FD_OFFSET_MASK) >> (31-11)) /**< Macro to get FD OFFSET field */
#define DPAA_FD_GET_LENGTH(fd) (((t_DpaaFD *)fd)->length & DPAA_FD_LENGTH_MASK) /**< Macro to get FD LENGTH field */
#define DPAA_FD_GET_STATUS(fd) ((t_DpaaFD *)fd)->status /**< Macro to get FD STATUS field */
#define DPAA_FD_GET_ADDR(fd) XX_PhysToVirt(DPAA_FD_GET_PHYS_ADDR(fd))
#define DPAA_FD_SET_DD(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~DPAA_FD_DD_MASK) | (((val) << (31-1)) & DPAA_FD_DD_MASK ))) /**< Macro to set FD DD field */
/**< Macro to set FD PID field or LIODN offset*/
#define DPAA_FD_SET_PID(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~(DPAA_FD_PID_MASK|DPAA_FD_ELIODN_MASK)) | ((((val) << (31-7)) & DPAA_FD_PID_MASK) | ((((val)>>6) << (31-19)) & DPAA_FD_ELIODN_MASK))))
#define DPAA_FD_SET_BPID(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~DPAA_FD_BPID_MASK) | (((val) << (31-15)) & DPAA_FD_BPID_MASK))) /**< Macro to set FD BPID field */
#define DPAA_FD_SET_ADDRH(fd,val) (((t_DpaaFD *)fd)->id = ((((t_DpaaFD *)fd)->id & ~DPAA_FD_ADDRH_MASK) | ((val) & DPAA_FD_ADDRH_MASK))) /**< Macro to set FD ADDRH field */
#define DPAA_FD_SET_ADDRL(fd,val) ((t_DpaaFD *)fd)->addrl = (val) /**< Macro to set FD ADDRL field */
#define DPAA_FD_SET_ADDR(fd,val) \
do { \
uint64_t physAddr = (uint64_t)(XX_VirtToPhys(val)); \
DPAA_FD_SET_ADDRH(fd, ((uint32_t)(physAddr >> 32))); \
DPAA_FD_SET_ADDRL(fd, (uint32_t)physAddr); \
} while (0) /**< Macro to set FD ADDR field */
#define DPAA_FD_SET_FORMAT(fd,val) (((t_DpaaFD *)fd)->length = ((((t_DpaaFD *)fd)->length & ~DPAA_FD_FORMAT_MASK) | (((val) << (31-2))& DPAA_FD_FORMAT_MASK))) /**< Macro to set FD FORMAT field */
#define DPAA_FD_SET_OFFSET(fd,val) (((t_DpaaFD *)fd)->length = ((((t_DpaaFD *)fd)->length & ~DPAA_FD_OFFSET_MASK) | (((val) << (31-11))& DPAA_FD_OFFSET_MASK) )) /**< Macro to set FD OFFSET field */
#define DPAA_FD_SET_LENGTH(fd,val) (((t_DpaaFD *)fd)->length = (((t_DpaaFD *)fd)->length & ~DPAA_FD_LENGTH_MASK) | ((val) & DPAA_FD_LENGTH_MASK)) /**< Macro to set FD LENGTH field */
#define DPAA_FD_SET_STATUS(fd,val) ((t_DpaaFD *)fd)->status = (val) /**< Macro to set FD STATUS field */
/* @} */
/**************************************************************************//**
@Description Frame Scatter/Gather Table Entry
*//***************************************************************************/
typedef _Packed struct t_DpaaSGTE {
volatile uint32_t addrh; /**< Buffer Address high */
volatile uint32_t addrl; /**< Buffer Address low */
volatile uint32_t length; /**< Buffer length */
volatile uint32_t offset; /**< SGTE offset */
} _PackedType t_DpaaSGTE;
#define DPAA_NUM_OF_SG_TABLE_ENTRY 16
/**************************************************************************//**
@Description Frame Scatter/Gather Table
*//***************************************************************************/
typedef _Packed struct t_DpaaSGT {
t_DpaaSGTE tableEntry[DPAA_NUM_OF_SG_TABLE_ENTRY];
/**< structure that hold the information about
a single S/G entry. */
} _PackedType t_DpaaSGT;
/**************************************************************************//**
@Description Compound Frame Table
*//***************************************************************************/
typedef _Packed struct t_DpaaCompTbl {
t_DpaaSGTE outputBuffInfo; /**< structure that holds the information about
the compound-frame output buffer;
NOTE: this may point to a S/G table */
t_DpaaSGTE inputBuffInfo; /**< structure that holds the information about
the compound-frame input buffer;
NOTE: this may point to a S/G table */
} _PackedType t_DpaaCompTbl;
/**************************************************************************//**
@Collection Frame Scatter/Gather Table Entry macros
*//***************************************************************************/
#define DPAA_SGTE_ADDRH_MASK 0x000000ff /**< SGTE ADDRH field mask */
#define DPAA_SGTE_ADDRL_MASK 0xffffffff /**< SGTE ADDRL field mask */
#define DPAA_SGTE_E_MASK 0x80000000 /**< SGTE Extension field mask */
#define DPAA_SGTE_F_MASK 0x40000000 /**< SGTE Final field mask */
#define DPAA_SGTE_LENGTH_MASK 0x3fffffff /**< SGTE LENGTH field mask */
#define DPAA_SGTE_BPID_MASK 0x00ff0000 /**< SGTE BPID field mask */
#define DPAA_SGTE_OFFSET_MASK 0x00001fff /**< SGTE OFFSET field mask */
#define DPAA_SGTE_GET_ADDRH(sgte) (((t_DpaaSGTE *)sgte)->addrh & DPAA_SGTE_ADDRH_MASK) /**< Macro to get SGTE ADDRH field */
#define DPAA_SGTE_GET_ADDRL(sgte) ((t_DpaaSGTE *)sgte)->addrl /**< Macro to get SGTE ADDRL field */
#define DPAA_SGTE_GET_PHYS_ADDR(sgte) ((physAddress_t)(((uint64_t)DPAA_SGTE_GET_ADDRH(sgte) << 32) | (uint64_t)DPAA_SGTE_GET_ADDRL(sgte))) /**< Macro to get FD ADDR field */
#define DPAA_SGTE_GET_EXTENSION(sgte) ((((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_E_MASK) >> (31-0)) /**< Macro to get SGTE EXTENSION field */
#define DPAA_SGTE_GET_FINAL(sgte) ((((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_F_MASK) >> (31-1)) /**< Macro to get SGTE FINAL field */
#define DPAA_SGTE_GET_LENGTH(sgte) (((t_DpaaSGTE *)sgte)->length & DPAA_SGTE_LENGTH_MASK) /**< Macro to get SGTE LENGTH field */
#define DPAA_SGTE_GET_BPID(sgte) ((((t_DpaaSGTE *)sgte)->offset & DPAA_SGTE_BPID_MASK) >> (31-15)) /**< Macro to get SGTE BPID field */
#define DPAA_SGTE_GET_OFFSET(sgte) (((t_DpaaSGTE *)sgte)->offset & DPAA_SGTE_OFFSET_MASK) /**< Macro to get SGTE OFFSET field */
#define DPAA_SGTE_GET_ADDR(sgte) XX_PhysToVirt(DPAA_SGTE_GET_PHYS_ADDR(sgte))
#define DPAA_SGTE_SET_ADDRH(sgte,val) (((t_DpaaSGTE *)sgte)->addrh = ((((t_DpaaSGTE *)sgte)->addrh & ~DPAA_SGTE_ADDRH_MASK) | ((val) & DPAA_SGTE_ADDRH_MASK))) /**< Macro to set SGTE ADDRH field */
#define DPAA_SGTE_SET_ADDRL(sgte,val) ((t_DpaaSGTE *)sgte)->addrl = (val) /**< Macro to set SGTE ADDRL field */
#define DPAA_SGTE_SET_ADDR(sgte,val) \
do { \
uint64_t physAddr = (uint64_t)(XX_VirtToPhys(val)); \
DPAA_SGTE_SET_ADDRH(sgte, ((uint32_t)(physAddr >> 32))); \
DPAA_SGTE_SET_ADDRL(sgte, (uint32_t)physAddr); \
} while (0) /**< Macro to set SGTE ADDR field */
#define DPAA_SGTE_SET_EXTENSION(sgte,val) (((t_DpaaSGTE *)sgte)->length = ((((t_DpaaSGTE *)sgte)->length & ~DPAA_SGTE_E_MASK) | (((val) << (31-0))& DPAA_SGTE_E_MASK))) /**< Macro to set SGTE EXTENSION field */
#define DPAA_SGTE_SET_FINAL(sgte,val) (((t_DpaaSGTE *)sgte)->length = ((((t_DpaaSGTE *)sgte)->length & ~DPAA_SGTE_F_MASK) | (((val) << (31-1))& DPAA_SGTE_F_MASK))) /**< Macro to set SGTE FINAL field */
#define DPAA_SGTE_SET_LENGTH(sgte,val) (((t_DpaaSGTE *)sgte)->length = (((t_DpaaSGTE *)sgte)->length & ~DPAA_SGTE_LENGTH_MASK) | ((val) & DPAA_SGTE_LENGTH_MASK)) /**< Macro to set SGTE LENGTH field */
#define DPAA_SGTE_SET_BPID(sgte,val) (((t_DpaaSGTE *)sgte)->offset = ((((t_DpaaSGTE *)sgte)->offset & ~DPAA_SGTE_BPID_MASK) | (((val) << (31-15))& DPAA_SGTE_BPID_MASK))) /**< Macro to set SGTE BPID field */
#define DPAA_SGTE_SET_OFFSET(sgte,val) (((t_DpaaSGTE *)sgte)->offset = ((((t_DpaaSGTE *)sgte)->offset & ~DPAA_SGTE_OFFSET_MASK) | (((val) << (31-31))& DPAA_SGTE_OFFSET_MASK) )) /**< Macro to set SGTE OFFSET field */
/* @} */
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
/** @} */ /* end of DPAA_grp group */
#endif /* __DPAA_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_mac_ext.h
@Description FM MAC ...
*//***************************************************************************/
#ifndef __FM_MAC_EXT_H
#define __FM_MAC_EXT_H
#include "std_ext.h"
#include "enet_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_mac_grp FM MAC
@Description FM MAC API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Description FM MAC Exceptions
*//***************************************************************************/
typedef enum e_FmMacExceptions {
e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO = 0
,e_FM_MAC_EX_10G_MDIO_CMD_CMPL
,e_FM_MAC_EX_10G_REM_FAULT
,e_FM_MAC_EX_10G_LOC_FAULT
,e_FM_MAC_EX_10G_1TX_ECC_ER
,e_FM_MAC_EX_10G_TX_FIFO_UNFL
,e_FM_MAC_EX_10G_TX_FIFO_OVFL
,e_FM_MAC_EX_10G_TX_ER
,e_FM_MAC_EX_10G_RX_FIFO_OVFL
,e_FM_MAC_EX_10G_RX_ECC_ER
,e_FM_MAC_EX_10G_RX_JAB_FRM
,e_FM_MAC_EX_10G_RX_OVRSZ_FRM
,e_FM_MAC_EX_10G_RX_RUNT_FRM
,e_FM_MAC_EX_10G_RX_FRAG_FRM
,e_FM_MAC_EX_10G_RX_LEN_ER
,e_FM_MAC_EX_10G_RX_CRC_ER
,e_FM_MAC_EX_10G_RX_ALIGN_ER
,e_FM_MAC_EX_1G_BAB_RX
,e_FM_MAC_EX_1G_RX_CTL
,e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET
,e_FM_MAC_EX_1G_BAB_TX
,e_FM_MAC_EX_1G_TX_CTL
,e_FM_MAC_EX_1G_TX_ERR
,e_FM_MAC_EX_1G_LATE_COL
,e_FM_MAC_EX_1G_COL_RET_LMT
,e_FM_MAC_EX_1G_TX_FIFO_UNDRN
,e_FM_MAC_EX_1G_MAG_PCKT
,e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET
,e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET
,e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET
,e_FM_MAC_EX_1G_TX_DATA_ERR
,e_FM_MAC_EX_1G_RX_DATA_ERR
,e_FM_MAC_EX_1G_1588_TS_RX_ERR
,e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL
} e_FmMacExceptions;
/**************************************************************************//**
@Description TM MAC statistics level
*//***************************************************************************/
typedef enum e_FmMacStatisticsLevel {
e_FM_MAC_NONE_STATISTICS = 0, /**< No statistics */
e_FM_MAC_PARTIAL_STATISTICS, /**< Only error counters are available. Optimized for performance */
e_FM_MAC_FULL_STATISTICS /**< All counters available. Not optimized for performance */
} e_FmMacStatisticsLevel;
/**************************************************************************//**
@Function t_FmMacExceptionCallback
@Description Fm Mac Exception Callback from FM MAC to the user
@Param[in] h_App - Handle to the upper layer handler
@Param[in] exceptions - The exception that occurred
@Return void.
*//***************************************************************************/
typedef void (t_FmMacExceptionCallback)(t_Handle h_App, e_FmMacExceptions exceptions);
/**************************************************************************//**
@Description TM MAC statistics rfc3635
*//***************************************************************************/
typedef struct t_FmMacStatistics {
/* RMON */
uint64_t eStatPkts64; /**< r-10G tr-DT 64 byte frame counter */
uint64_t eStatPkts65to127; /**< r-10G 65 to 127 byte frame counter */
uint64_t eStatPkts128to255; /**< r-10G 128 to 255 byte frame counter */
uint64_t eStatPkts256to511; /**< r-10G 256 to 511 byte frame counter */
uint64_t eStatPkts512to1023; /**< r-10G 512 to 1023 byte frame counter */
uint64_t eStatPkts1024to1518; /**< r-10G 1024 to 1518 byte frame counter */
uint64_t eStatPkts1519to1522; /**< r-10G 1519 to 1522 byte good frame count */
/* */
uint64_t eStatFragments; /**< Total number of packets that were less than 64 octets long with a wrong CRC.*/
uint64_t eStatJabbers; /**< Total number of packets longer than valid maximum length octets */
uint64_t eStatsDropEvents; /**< number of dropped packets due to internal errors of the MAC Client. */
uint64_t eStatCRCAlignErrors; /**< Incremented when frames of correct length but with CRC error are received.*/
uint64_t eStatUndersizePkts; /**< Total number of packets that were less than 64 octets long with a good CRC.*/
uint64_t eStatOversizePkts; /**< T,B.D*/
/* Pause */
uint64_t teStatPause; /**< Pause MAC Control received */
uint64_t reStatPause; /**< Pause MAC Control sent */
/* MIB II */
uint64_t ifInOctets; /**< Total number of byte received. */
uint64_t ifInPkts; /**< Total number of packets received.*/
uint64_t ifInMcastPkts; /**< Total number of multicast frame received*/
uint64_t ifInBcastPkts; /**< Total number of broadcast frame received */
uint64_t ifInDiscards; /**< Frames received, but discarded due to problems within the MAC RX. */
uint64_t ifInErrors; /**< Number of frames received with error:
- FIFO Overflow Error
- CRC Error
- Frame Too Long Error
- Alignment Error
- The dedicated Error Code (0xfe, not a code error) was received */
uint64_t ifOutOctets; /**< Total number of byte sent. */
uint64_t ifOutPkts; /**< Total number of packets sent .*/
uint64_t ifOutMcastPkts; /**< Total number of multicast frame sent */
uint64_t ifOutBcastPkts; /**< Total number of multicast frame sent */
uint64_t ifOutDiscards; /**< Frames received, but discarded due to problems within the MAC TX N/A!.*/
uint64_t ifOutErrors; /**< Number of frames transmitted with error:
- FIFO Overflow Error
- FIFO Underflow Error
- Other */
} t_FmMacStatistics;
/**************************************************************************//**
@Group FM_mac_init_grp Initialization Unit
@Description FM MAC Initialization Unit
@{
*//***************************************************************************/
/**************************************************************************//**
@Description FM MAC config input
*//***************************************************************************/
typedef struct t_FmMacParams {
uintptr_t baseAddr; /**< Base of memory mapped FM MAC registers */
t_EnetAddr addr; /**< MAC address of device; First octet is sent first */
uint8_t macId; /**< MAC ID <dTSEC 0-3> <10G 0> */
e_EnetMode enetMode; /**< Ethernet operation mode (MAC-PHY interface and speed) */
t_Handle h_Fm; /**< A handle to the FM object this port related to */
int mdioIrq; /**< MDIO exceptions interrupt source - not valid for all
MACs; MUST be set to 'NO_IRQ' for MACs that don't have
mdio-irq, or for polling */
t_FmMacExceptionCallback *f_Event; /**< MDIO Events Callback Routine */
t_FmMacExceptionCallback *f_Exception; /**< Exception Callback Routine */
t_Handle h_App; /**< A handle to an application layer object; This handle will
be passed by the driver upon calling the above callbacks */
} t_FmMacParams;
/**************************************************************************//**
@Function FM_MAC_Config
@Description Creates descriptor for the FM MAC module.
The routine returns a handle (descriptor) to the FM MAC object.
This descriptor must be passed as first parameter to all other
FM MAC function calls.
No actual initialization or configuration of FM MAC hardware is
done by this routine.
@Param[in] p_FmMacParam - Pointer to data structure of parameters
@Retval Handle to FM MAC object, or NULL for Failure.
*//***************************************************************************/
t_Handle FM_MAC_Config (t_FmMacParams *p_FmMacParam);
/**************************************************************************//**
@Function FM_MAC_Init
@Description Initializes the FM MAC module
@Param[in] h_FmMac - FM module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_Init (t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_Free
@Description Frees all resources that were assigned to FM MAC module.
Calling this routine invalidates the descriptor.
@Param[in] h_FmMac - FM module descriptor
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_Free (t_Handle h_FmMac);
/**************************************************************************//**
@Group FM_mac_advanced_init_grp Advanced Configuration Unit
@Description Configuration functions used to change default values.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_MAC_ConfigResetOnInit
@Description Tell the driver whether to reset the FM MAC before initialization or
not. It changes the default configuration [FALSE].
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable When TRUE, FM will be reset before any initialization.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigResetOnInit (t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigLoopback
@Description Enable/Disable internal loopback mode
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigLoopback (t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigMaxFrameLength
@Description Setup maximum Frame Length
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] newVal MAX Frame length
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigMaxFrameLength (t_Handle h_FmMac, uint16_t newVal);
/**************************************************************************//**
@Function FM_MAC_ConfigWan
@Description ENABLE WAN mode in 10G MAC
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigWan (t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigPadAndCrc
@Description Config PAD and CRC mode
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigPadAndCrc (t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigHalfDuplex
@Description Config Half Duplex Mode
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigHalfDuplex (t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigLengthCheck
@Description Configure thef frame length checking.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] enable TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigLengthCheck (t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_ConfigException
@Description Change Exception selection from default
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] ex Type of the desired exceptions
@Param[in] enable TRUE to enable the specified exception, FALSE to disable it.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Config() and before FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ConfigException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable);
#ifdef FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
t_Error FM_MAC_ConfigSkipFman11Workaround (t_Handle h_FmMac);
#endif /* FM_TX_ECC_FRMS_ERRATA_10GMAC_A004 */
/** @} */ /* end of FM_mac_advanced_init_grp group */
/** @} */ /* end of FM_mac_init_grp group */
/**************************************************************************//**
@Group FM_mac_runtime_control_grp Runtime Control Unit
@Description FM MAC Runtime control unit API functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_MAC_Enable
@Description Enable the MAC
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] mode Mode of operation (RX, TX, Both)
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Enable (t_Handle h_FmMac, e_CommMode mode);
/**************************************************************************//**
@Function FM_MAC_Disable
@Description DISABLE the MAC
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] mode Define what part to Disable (RX, TX or BOTH)
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Disable (t_Handle h_FmMac, e_CommMode mode);
/**************************************************************************//**
@Function FM_MAC_Enable1588TimeStamp
@Description Enables the TSU operation.
@Param[in] h_Fm - Handle to the PTP as returned from the FM_MAC_PtpConfig.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Enable1588TimeStamp(t_Handle h_Fm);
/**************************************************************************//**
@Function FM_MAC_Disable1588TimeStamp
@Description Disables the TSU operation.
@Param[in] h_Fm - Handle to the PTP as returned from the FM_MAC_PtpConfig.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_Disable1588TimeStamp(t_Handle h_Fm);
/**************************************************************************//**
@Function FM_MAC_SetTxAutoPauseFrames
@Description Enable/Disable transmition of Pause-Frames.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] pauseTime Pause quanta value used with transmitted pause frames.
Each quanta represents a 512 bit-times; Note that '0'
as an input here will be used as disabling the
transmission of the pause-frames.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetTxAutoPauseFrames (t_Handle h_FmMac, uint16_t pauseTime);
/**************************************************************************//**
@Function FM_MAC_SetRxIgnorePauseFrames
@Description Enable/Disable ignoring of Pause-Frames.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] en boolean indicates whether to ignore the incoming pause
frames or not.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetRxIgnorePauseFrames (t_Handle h_FmMac, bool en);
/**************************************************************************//**
@Function FM_MAC_ResetCounters
@Description reset all statistics counters
@Param[in] h_FmMac A handle to a FM MAC Module.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ResetCounters (t_Handle h_FmMac);
/**************************************************************************//**
@Function FM_MAC_SetException
@Description Enable/Disable a specific Exception
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] ex Type of the desired exceptions
@Param[in] enable TRUE to enable the specified exception, FALSE to disable it.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetException(t_Handle h_FmMac, e_FmMacExceptions ex, bool enable);
/**************************************************************************//**
@Function FM_MAC_SetStatistics
@Description Define Statistics level.
Where applicable, the routine also enables the MIB counters
overflow interrupt in order to keep counters accurate
and account for overflows.
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] statisticsLevel Full statistics level provides all standard counters but may
reduce performance. Partial statistics provides only special
event counters (errors etc.). If selected, regular counters (such as
byte/packet) will be invalid and will return -1.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetStatistics (t_Handle h_FmMac, e_FmMacStatisticsLevel statisticsLevel);
/**************************************************************************//**
@Function FM_MAC_GetStatistics
@Description get all statistics counters
@Param[in] h_FmMac A handle to a FM MAC Module.
@Param[in] p_Statistics Staructure with statistics
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_Init().
*//***************************************************************************/
t_Error FM_MAC_GetStatistics (t_Handle h_FmMac, t_FmMacStatistics *p_Statistics);
/**************************************************************************//**
@Function FM_MAC_ModifyMacAddr
@Description Replace the main MAC Address
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - Ethernet Mac address
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_ModifyMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_AddHashMacAddr
@Description Add an Address to the hash table. This is for filter purpose only.
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - Ethernet Mac address
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init(). It is a filter only address.
@Cautions Some address need to be filterd out in upper FM blocks.
*//***************************************************************************/
t_Error FM_MAC_AddHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_RemoveHashMacAddr
@Description Delete an Address to the hash table. This is for filter purpose only.
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - Ethernet Mac address
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only following FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_RemoveHashMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_AddExactMatchMacAddr
@Description Add a unicast or multicast mac address for exact-match filtering
(8 on dTSEC, 2 for 10G-MAC)
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - MAC Address to ADD
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_AddExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_RemovelExactMatchMacAddr
@Description Remove a uni cast or multi cast mac address.
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] p_EnetAddr - MAC Address to remove
@Return E_OK on success; Error code otherwise..
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_RemovelExactMatchMacAddr (t_Handle h_FmMac, t_EnetAddr *p_EnetAddr);
/**************************************************************************//**
@Function FM_MAC_SetPromiscuous
@Description Enable/Disable MAC Promiscuous mode for ALL mac addresses.
@Param[in] h_FmMac - A handle to a FM MAC Module.
@Param[in] enable - TRUE to enable or FALSE to disable.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_SetPromiscuous (t_Handle h_FmMac, bool enable);
/**************************************************************************//**
@Function FM_MAC_AdjustLink
@Description Adjusts the Ethernet link with new speed/duplex setup.
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] speed - Ethernet speed.
@Param[in] fullDuplex - TRUE for Full-Duplex mode;
FALSE for Half-Duplex mode.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MAC_AdjustLink(t_Handle h_FmMac, e_EnetSpeed speed, bool fullDuplex);
/**************************************************************************//**
@Function FM_MAC_GetId
@Description Return the MAC ID
@Param[in] h_FmMac - A handle to a FM Module.
@Param[out] p_MacId - MAC ID of device
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_GetId (t_Handle h_FmMac, uint32_t *p_MacId);
/**************************************************************************//**
@Function FM_MAC_GetVesrion
@Description Return Mac HW chip version
@Param[in] h_FmMac - A handle to a FM Module.
@Param[out] p_MacVresion - Mac version as defined by the chip
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_GetVesrion (t_Handle h_FmMac, uint32_t *p_MacVresion);
/**************************************************************************//**
@Function FM_MAC_MII_WritePhyReg
@Description Write data into Phy Register
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] phyAddr - Phy Address on the MII bus
@Param[in] reg - Register Number.
@Param[in] data - Data to write.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_MII_WritePhyReg (t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t data);
/**************************************************************************//**
@Function FM_MAC_MII_ReadPhyReg
@Description Read data from Phy Register
@Param[in] h_FmMac - A handle to a FM Module.
@Param[in] phyAddr - Phy Address on the MII bus
@Param[in] reg - Register Number.
@Param[out] p_Data - Data from PHY.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_MII_ReadPhyReg(t_Handle h_FmMac, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
/**************************************************************************//**
@Function FM_MAC_DumpRegs
@Description Dump internal registers
@Param[in] h_FmMac - A handle to a FM Module.
@Return E_OK on success; Error code otherwise.
@Cautions Allowed only after FM_MAC_Init().
*//***************************************************************************/
t_Error FM_MAC_DumpRegs(t_Handle h_FmMac);
#endif /* (defined(DEBUG_ERRORS) && ... */
/** @} */ /* end of FM_mac_runtime_control_grp group */
/** @} */ /* end of FM_mac_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_MAC_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_muram_ext.h
@Description FM MURAM Application Programming Interface.
*//***************************************************************************/
#ifndef __FM_MURAM_EXT
#define __FM_MURAM_EXT
#include "error_ext.h"
#include "std_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_muram_grp FM MURAM
@Description FM MURAM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group FM_muram_init_grp FM MURAM Initialization
@Description FM MURAM initialization API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_MURAM_ConfigAndInit
@Description Creates partition in the MURAM.
The routine returns a handle (descriptor) to the MURAM partition.
This descriptor must be passed as first parameter to all other
FM-MURAM function calls.
No actual initialization or configuration of FM_MURAM hardware is
done by this routine.
@Param[in] baseAddress - Pointer to base of memory mapped FM-MURAM.
@Param[in] size - Size of the FM-MURAM partition.
@Return Handle to FM-MURAM object, or NULL for Failure.
*//***************************************************************************/
t_Handle FM_MURAM_ConfigAndInit(uintptr_t baseAddress, uint32_t size);
/**************************************************************************//**
@Function FM_MURAM_Free
@Description Frees all resources that were assigned to FM-MURAM module.
Calling this routine invalidates the descriptor.
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MURAM_Free(t_Handle h_FmMuram);
/** @} */ /* end of FM_muram_init_grp group */
/**************************************************************************//**
@Group FM_muram_ctrl_grp FM MURAM Control
@Description FM MURAM control API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_MURAM_AllocMem
@Description Allocate some memory from FM-MURAM partition.
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Param[in] size - size of the memory to be allocated.
@Param[in] align - Alignment of the memory.
@Return address of the allocated memory; NULL otherwise.
*//***************************************************************************/
void * FM_MURAM_AllocMem(t_Handle h_FmMuram, uint32_t size, uint32_t align);
/**************************************************************************//**
@Function FM_MURAM_AllocMemForce
@Description Allocate some specific memory from FM-MURAM partition (according
to base).
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Param[in] base - the desired base-address to be allocated.
@Param[in] size - size of the memory to be allocated.
@Return address of the allocated memory; NULL otherwise.
*//***************************************************************************/
void * FM_MURAM_AllocMemForce(t_Handle h_FmMuram, uint64_t base, uint32_t size);
/**************************************************************************//**
@Function FM_MURAM_FreeMem
@Description Free an allocated memory from FM-MURAM partition.
@Param[in] h_FmMuram - FM-MURAM module descriptor.
@Param[in] ptr - A pointer to an allocated memory.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error FM_MURAM_FreeMem(t_Handle h_FmMuram, void *ptr);
/** @} */ /* end of FM_muram_ctrl_grp group */
/** @} */ /* end of FM_muram_grp group */
/** @} */ /* end of FM_grp group */
#endif /* __FM_MURAM_EXT */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File fm_rtc_ext.h
@Description External definitions and API for FM RTC IEEE1588 Timer Module.
@Cautions None.
*//***************************************************************************/
#ifndef __FM_RTC_EXT_H__
#define __FM_RTC_EXT_H__
#include "error_ext.h"
#include "std_ext.h"
/**************************************************************************//**
@Group FM_grp Frame Manager API
@Description FM API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group fm_rtc_grp FM RTC
@Description FM RTC functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group fm_rtc_init_grp FM RTC Initialization Unit
@Description FM RTC initialization API.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description FM RTC Alarm Polarity Options.
*//***************************************************************************/
typedef enum e_FmRtcAlarmPolarity
{
e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH, /**< Active-high output polarity */
e_FM_RTC_ALARM_POLARITY_ACTIVE_LOW /**< Active-low output polarity */
} e_FmRtcAlarmPolarity;
/**************************************************************************//**
@Description FM RTC Trigger Polarity Options.
*//***************************************************************************/
typedef enum e_FmRtcTriggerPolarity
{
e_FM_RTC_TRIGGER_ON_RISING_EDGE, /**< Trigger on rising edge */
e_FM_RTC_TRIGGER_ON_FALLING_EDGE /**< Trigger on falling edge */
} e_FmRtcTriggerPolarity;
/**************************************************************************//**
@Description IEEE1588 Timer Module FM RTC Optional Clock Sources.
*//***************************************************************************/
typedef enum e_FmSrcClock
{
e_FM_RTC_SOURCE_CLOCK_EXTERNAL, /**< external high precision timer reference clock */
e_FM_RTC_SOURCE_CLOCK_SYSTEM, /**< MAC system clock */
e_FM_RTC_SOURCE_CLOCK_OSCILATOR /**< RTC clock oscilator */
}e_FmSrcClk;
/**************************************************************************//**
@Description FM RTC configuration parameters structure.
This structure should be passed to FM_RTC_Config().
*//***************************************************************************/
typedef struct t_FmRtcParams
{
t_Handle h_Fm; /**< FM Handle*/
uintptr_t baseAddress; /**< Base address of FM RTC registers */
t_Handle h_App; /**< A handle to an application layer object; This handle will
be passed by the driver upon calling the above callbacks */
} t_FmRtcParams;
/**************************************************************************//**
@Function FM_RTC_Config
@Description Configures the FM RTC module according to user's parameters.
The driver assigns default values to some FM RTC parameters.
These parameters can be overwritten using the advanced
configuration routines.
@Param[in] p_FmRtcParam - FM RTC configuration parameters.
@Return Handle to the new FM RTC object; NULL pointer on failure.
@Cautions None
*//***************************************************************************/
t_Handle FM_RTC_Config(t_FmRtcParams *p_FmRtcParam);
/**************************************************************************//**
@Function FM_RTC_Init
@Description Initializes the FM RTC driver and hardware.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_Init(t_Handle h_FmRtc);
/**************************************************************************//**
@Function FM_RTC_Free
@Description Frees the FM RTC object and all allocated resources.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_Free(t_Handle h_FmRtc);
/**************************************************************************//**
@Group fm_rtc_adv_config_grp FM RTC Advanced Configuration Unit
@Description FM RTC advanced configuration functions.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function FM_RTC_ConfigPeriod
@Description Configures the period of the timestamp if different than
default [1000].
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] period - Period in nano-seconds.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigPeriod(t_Handle h_FmRtc, uint32_t period);
/**************************************************************************//**
@Function FM_RTC_ConfigSourceClock
@Description Configures the source clock of the RTC.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] srcClk - Source clock selection.
@Param[in] freqInMhz - the source-clock frequency (in MHz).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigSourceClock(t_Handle h_FmRtc,
e_FmSrcClk srcClk,
uint32_t freqInMhz);
/**************************************************************************//**
@Function FM_RTC_ConfigPulseRealignment
@Description Configures the RTC to automatic FIPER pulse realignment in
response to timer adjustments [FALSE]
In this mode, the RTC clock is identical to the source clock.
This feature can be useful when the system contains an external
RTC with inherent frequency compensation.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] enable - TRUE to enable automatic realignment.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigPulseRealignment(t_Handle h_FmRtc, bool enable);
/**************************************************************************//**
@Function FM_RTC_ConfigFrequencyBypass
@Description Configures the RTC to bypass the frequency compensation
mechanism. [FALSE]
In this mode, the RTC clock is identical to the source clock.
This feature can be useful when the system contains an external
RTC with inherent frequency compensation.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] enabled - TRUE to bypass frequency compensation;
FALSE otherwise.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigFrequencyBypass(t_Handle h_FmRtc, bool enabled);
/**************************************************************************//**
@Function FM_RTC_ConfigInvertedInputClockPhase
@Description Configures the RTC to invert the source clock phase on input.
[FALSE]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] inverted - TRUE to invert the source clock phase on input.
FALSE otherwise.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigInvertedInputClockPhase(t_Handle h_FmRtc, bool inverted);
/**************************************************************************//**
@Function FM_RTC_ConfigInvertedOutputClockPhase
@Description Configures the RTC to invert the output clock phase.
[FALSE]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] inverted - TRUE to invert the output clock phase.
FALSE otherwise.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigInvertedOutputClockPhase(t_Handle h_FmRtc, bool inverted);
/**************************************************************************//**
@Function FM_RTC_ConfigOutputClockDivisor
@Description Configures the divisor for generating the output clock from
the RTC clock. [0x00000002]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] divisor - Divisor for generation of the output clock.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigOutputClockDivisor(t_Handle h_FmRtc, uint16_t divisor);
/**************************************************************************//**
@Function FM_RTC_ConfigAlarmPolarity
@Description Configures the polarity (active-high/active-low) of a specific
alarm signal. [e_FM_RTC_ALARM_POLARITY_ACTIVE_HIGH]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] alarmId - Alarm ID.
@Param[in] alarmPolarity - Alarm polarity.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigAlarmPolarity(t_Handle h_FmRtc,
uint8_t alarmId,
e_FmRtcAlarmPolarity alarmPolarity);
/**************************************************************************//**
@Function FM_RTC_ConfigExternalTriggerPolarity
@Description Configures the polarity (rising/falling edge) of a specific
external trigger signal. [e_FM_RTC_TRIGGER_ON_FALLING_EDGE]
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] triggerId - Trigger ID.
@Param[in] triggerPolarity - Trigger polarity.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously created using FM_RTC_Config().
*//***************************************************************************/
t_Error FM_RTC_ConfigExternalTriggerPolarity(t_Handle h_FmRtc,
uint8_t triggerId,
e_FmRtcTriggerPolarity triggerPolarity);
/** @} */ /* end of fm_rtc_adv_config_grp */
/** @} */ /* end of fm_rtc_init_grp */
/**************************************************************************//**
@Group fm_rtc_control_grp FM RTC Control Unit
@Description FM RTC runtime control API.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function t_FmRtcExceptionsCallback
@Description Exceptions user callback routine, used for RTC different mechanisms.
@Param[in] h_App - User's application descriptor.
@Param[in] id - source id.
*//***************************************************************************/
typedef void (t_FmRtcExceptionsCallback) ( t_Handle h_App, uint8_t id);
/**************************************************************************//**
@Description FM RTC alarm parameters.
*//***************************************************************************/
typedef struct t_FmRtcAlarmParams {
uint8_t alarmId; /**< 0 or 1 */
uint64_t alarmTime; /**< In nanoseconds, the time when the alarm
should go off - must be a multiple of
the RTC period */
t_FmRtcExceptionsCallback *f_AlarmCallback; /**< This routine will be called when RTC
reaches alarmTime */
bool clearOnExpiration; /**< TRUE to turn off the alarm once expired. */
} t_FmRtcAlarmParams;
/**************************************************************************//**
@Description FM RTC Periodic Pulse parameters.
*//***************************************************************************/
typedef struct t_FmRtcPeriodicPulseParams {
uint8_t periodicPulseId; /**< 0 or 1 */
uint64_t periodicPulsePeriod; /**< In Nanoseconds. Must be
a multiple of the RTC period */
t_FmRtcExceptionsCallback *f_PeriodicPulseCallback; /**< This routine will be called every
periodicPulsePeriod. */
} t_FmRtcPeriodicPulseParams;
/**************************************************************************//**
@Description FM RTC Periodic Pulse parameters.
*//***************************************************************************/
typedef struct t_FmRtcExternalTriggerParams {
uint8_t externalTriggerId; /**< 0 or 1 */
bool usePulseAsInput; /**< Use the pulse interrupt instead of
an external signal */
t_FmRtcExceptionsCallback *f_ExternalTriggerCallback; /**< This routine will be called every
periodicPulsePeriod. */
} t_FmRtcExternalTriggerParams;
/**************************************************************************//**
@Function FM_RTC_Enable
@Description Enable the RTC (time count is started).
The user can select to resume the time count from previous
point, or to restart the time count.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] resetClock - Restart the time count from zero.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_Enable(t_Handle h_FmRtc, bool resetClock);
/**************************************************************************//**
@Function FM_RTC_Disable
@Description Disables the RTC (time count is stopped).
@Param[in] h_FmRtc - Handle to FM RTC object.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_Disable(t_Handle h_FmRtc);
/**************************************************************************//**
@Function FM_RTC_SetClockOffset
@Description Sets the clock offset (usually relative to another clock).
The user can pass a negative offset value.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] offset - New clock offset (in nanoseconds).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_SetClockOffset(t_Handle h_FmRtc, int64_t offset);
/**************************************************************************//**
@Function FM_RTC_SetAlarm
@Description Schedules an alarm event to a given RTC time.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] p_FmRtcAlarmParams - Alarm parameters.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
Must be called only prior to FM_RTC_Enable().
*//***************************************************************************/
t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc, t_FmRtcAlarmParams *p_FmRtcAlarmParams);
/**************************************************************************//**
@Function FM_RTC_SetPeriodicPulse
@Description Sets a periodic pulse.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] p_FmRtcPeriodicPulseParams - Periodic pulse parameters.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
Must be called only prior to FM_RTC_Enable().
*//***************************************************************************/
t_Error FM_RTC_SetPeriodicPulse(t_Handle h_FmRtc, t_FmRtcPeriodicPulseParams *p_FmRtcPeriodicPulseParams);
/**************************************************************************//**
@Function FM_RTC_ClearPeriodicPulse
@Description Clears a periodic pulse.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] periodicPulseId - Periodic pulse id.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_ClearPeriodicPulse(t_Handle h_FmRtc, uint8_t periodicPulseId);
/**************************************************************************//**
@Function FM_RTC_SetExternalTrigger
@Description Sets an external trigger indication and define a callback
routine to be called on such event.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] p_FmRtcExternalTriggerParams - External Trigger parameters.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_SetExternalTrigger(t_Handle h_FmRtc, t_FmRtcExternalTriggerParams *p_FmRtcExternalTriggerParams);
/**************************************************************************//**
@Function FM_RTC_ClearExternalTrigger
@Description Clears external trigger indication.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] id - External Trigger id.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_ClearExternalTrigger(t_Handle h_FmRtc, uint8_t id);
/**************************************************************************//**
@Function FM_RTC_GetExternalTriggerTimeStamp
@Description Reads the External Trigger TimeStamp.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] triggerId - External Trigger id.
@Param[out] p_TimeStamp - External Trigger timestamp (in nanoseconds).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_GetExternalTriggerTimeStamp(t_Handle h_FmRtc,
uint8_t triggerId,
uint64_t *p_TimeStamp);
/**************************************************************************//**
@Function FM_RTC_GetCurrentTime
@Description Returns the current RTC time.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[out] p_Ts - returned time stamp (in nanoseconds).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_GetCurrentTime(t_Handle h_FmRtc, uint64_t *p_Ts);
/**************************************************************************//**
@Function FM_RTC_SetCurrentTime
@Description Sets the current RTC time.
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] ts - The new time stamp (in nanoseconds).
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_SetCurrentTime(t_Handle h_FmRtc, uint64_t ts);
/**************************************************************************//**
@Function FM_RTC_GetFreqCompensation
@Description TODO
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[out] p_Compensation - A pointer to the returned value of compensation.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_GetFreqCompensation(t_Handle h_FmRtc, uint32_t *p_Compensation);
/**************************************************************************//**
@Function FM_RTC_SetFreqCompensation
@Description TODO
@Param[in] h_FmRtc - Handle to FM RTC object.
@Param[in] freqCompensation - the new desired compensation value to be set.
@Return E_OK on success; Error code otherwise.
@Cautions h_FmRtc must have been previously initialized using FM_RTC_Init().
*//***************************************************************************/
t_Error FM_RTC_SetFreqCompensation(t_Handle h_FmRtc, uint32_t freqCompensation);
#if (defined(DEBUG_ERRORS) && (DEBUG_ERRORS > 0))
/**************************************************************************//**
@Function FM_RTC_DumpRegs
@Description Dumps all FM registers
@Param[in] h_FmRtc A handle to an FM RTC Module.
@Return E_OK on success;
@Cautions Allowed only FM_Init().
*//***************************************************************************/
t_Error FM_RTC_DumpRegs(t_Handle h_FmRtc);
#endif /* (defined(DEBUG_ERRORS) && ... */
/** @} */ /* end of fm_rtc_control_grp */
/** @} */ /* end of fm_rtc_grp */
/** @} */ /* end of FM_grp group */
#endif /* __FM_RTC_EXT_H__ */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File core_ext.h
@Description Generic interface to basic core operations.
The system integrator must ensure that this interface is
mapped to a specific core implementation, by including the
appropriate header file.
*//***************************************************************************/
#ifndef __CORE_EXT_H
#define __CORE_EXT_H
#ifdef NCSW_PPC_CORE
#include "ppc_ext.h"
#elif defined(NCSW_VXWORKS)
#include "core_vxw_ext.h"
#else
#error "Core is not defined!"
#endif /* NCSW_CORE */
#if (!defined(CORE_IS_LITTLE_ENDIAN) && !defined(CORE_IS_BIG_ENDIAN))
#error "Must define core as little-endian or big-endian!"
#endif /* (!defined(CORE_IS_LITTLE_ENDIAN) && ... */
/**************************************************************************//**
@Function CORE_GetId
@Description Returns the core ID in the system.
@Return Core ID.
*//***************************************************************************/
uint32_t CORE_GetId(void);
/**************************************************************************//**
@Function CORE_MemoryBarrier
@Description This routine will cause the core to stop executing any commands
until all previous memory read/write commands are completely out
of the core's pipeline.
@Return None.
*//***************************************************************************/
void CORE_MemoryBarrier(void);
#endif /* __CORE_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File e500v2_ext.h
@Description E500 external definitions prototypes
This file is not included by the E500
source file as it is an assembly file. It is used
only for prototypes exposure, for inclusion
by user and other modules.
*//***************************************************************************/
#ifndef __E500V2_EXT_H
#define __E500V2_EXT_H
#include "std_ext.h"
/* Layer 1 Cache Manipulations
*==============================
* Should not be called directly by the user.
*/
void L1DCache_Invalidate (void);
void L1ICache_Invalidate(void);
void L1DCache_Enable(void);
void L1ICache_Enable(void);
void L1DCache_Disable(void);
void L1ICache_Disable(void);
void L1DCache_Flush(void);
void L1ICache_Flush(void);
/*
*
*/
uint32_t L1DCache_LineLock(uint32_t addr);
uint32_t L1ICache_LineLock(uint32_t addr);
void L1Cache_BroadCastEnable(void);
void L1Cache_BroadCastDisable(void);
#define CORE_DCacheEnable E500_DCacheEnable
#define CORE_ICacheEnable E500_ICacheEnable
#define CORE_DCacheDisable E500_DCacheDisable
#define CORE_ICacheDisable E500_ICacheDisable
#define CORE_GetId E500_GetId
#define CORE_TestAndSet E500_TestAndSet
#define CORE_MemoryBarrier E500_MemoryBarrier
#define CORE_InstructionSync E500_InstructionSync
#define CORE_SetDozeMode E500_SetDozeMode
#define CORE_SetNapMode E500_SetNapMode
#define CORE_SetSleepMode E500_SetSleepMode
#define CORE_SetJogMode E500_SetJogMode
#define CORE_SetDeepSleepMode E500_SetDeepSleepMode
#define CORE_RecoverDozeMode E500_RecoverDozeMode
#define CORE_RecoverNapMode E500_RecoverNapMode
#define CORE_RecoverSleepMode E500_RecoverSleepMode
#define CORE_RecoverJogMode E500_RecoverJogMode
void E500_SetDozeMode(void);
void E500_SetNapMode(void);
void E500_SetSleepMode(void);
void E500_SetJogMode(void);
t_Error E500_SetDeepSleepMode(uint32_t bptrAddress);
void E500_RecoverDozeMode(void);
void E500_RecoverNapMode(void);
void E500_RecoverSleepMode(void);
void E500_RecoverJogMode(void);
/**************************************************************************//**
@Group E500_id E500 Application Programming Interface
@Description E500 API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Group E500_init_grp E500 Initialization Unit
@Description E500 initialization unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Function E500_DCacheEnable
@Description Enables the data cache for memory pages that are
not cache inhibited.
@Return None.
*//***************************************************************************/
void E500_DCacheEnable(void);
/**************************************************************************//**
@Function E500_ICacheEnable
@Description Enables the instruction cache for memory pages that are
not cache inhibited.
@Return None.
*//***************************************************************************/
void E500_ICacheEnable(void);
/**************************************************************************//**
@Function E500_DCacheDisable
@Description Disables the data cache.
@Return None.
*//***************************************************************************/
void E500_DCacheDisable(void);
/**************************************************************************//**
@Function E500_ICacheDisable
@Description Disables the instruction cache.
@Return None.
*//***************************************************************************/
void E500_ICacheDisable(void);
/**************************************************************************//**
@Function E500_DCacheFlush
@Description Flushes the data cache
@Return None.
*//***************************************************************************/
void E500_DCacheFlush(void);
/**************************************************************************//**
@Function E500_ICacheFlush
@Description Flushes the instruction cache.
@Return None.
*//***************************************************************************/
void E500_ICacheFlush(void);
/**************************************************************************//**
@Function E500_DCacheSetStashId
@Description Set Stash Id for data cache
@Param[in] stashId the stash id to be set.
@Return None.
*//***************************************************************************/
void E500_DCacheSetStashId(uint8_t stashId);
/**************************************************************************//**
@Description E500mc L2 Cache Operation Mode
*//***************************************************************************/
typedef enum e_E500mcL2CacheMode
{
e_L2_CACHE_MODE_DATA_ONLY = 0x00000001, /**< Cache data only */
e_L2_CACHE_MODE_INST_ONLY = 0x00000002, /**< Cache instructions only */
e_L2_CACHE_MODE_DATA_AND_INST = 0x00000003 /**< Cache data and instructions */
} e_E500mcL2CacheMode;
/**************************************************************************//**
@Function E500_L2CacheEnable
@Description Enables the cache for memory pages that are not cache inhibited.
@param[in] mode - L2 cache mode: data only, instruction only or instruction and data.
@Return None.
@Cautions This routine must be call only ONCE for both caches. I.e. it is
not possible to call this routine for i-cache and than to call
again for d-cache; The second call will override the first one.
*//***************************************************************************/
void E500_L2CacheEnable(e_E500mcL2CacheMode mode);
/**************************************************************************//**
@Function E500_L2CacheDisable
@Description Disables the cache (data instruction or both).
@Return None.
*//***************************************************************************/
void E500_L2CacheDisable(void);
/**************************************************************************//**
@Function E500_L2CacheFlush
@Description Flushes the cache.
@Return None.
*//***************************************************************************/
void E500_L2CacheFlush(void);
/**************************************************************************//**
@Function E500_L2SetStashId
@Description Set Stash Id
@Param[in] stashId the stash id to be set.
@Return None.
*//***************************************************************************/
void E500_L2SetStashId(uint8_t stashId);
/**************************************************************************//**
@Function E500_AddressBusStreamingEnable
@Description Enables address bus streaming on the CCB.
This setting, along with the ECM streaming configuration
parameters, enables address bus streaming on the CCB.
@Return None.
*//***************************************************************************/
void E500_AddressBusStreamingEnable(void);
/**************************************************************************//**
@Function E500_AddressBusStreamingDisable
@Description Disables address bus streaming on the CCB.
@Return None.
*//***************************************************************************/
void E500_AddressBusStreamingDisable(void);
/**************************************************************************//**
@Function E500_AddressBroadcastEnable
@Description Enables address broadcast.
The e500 broadcasts cache management instructions (dcbst, dcblc
(CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi)
based on ABE. ABE must be set to allow management of external
L2 caches.
@Return None.
*//***************************************************************************/
void E500_AddressBroadcastEnable(void);
/**************************************************************************//**
@Function E500_AddressBroadcastDisable
@Description Disables address broadcast.
The e500 broadcasts cache management instructions (dcbst, dcblc
(CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi)
based on ABE. ABE must be set to allow management of external
L2 caches.
@Return None.
*//***************************************************************************/
void E500_AddressBroadcastDisable(void);
/**************************************************************************//**
@Function E500_IsTaskletSupported
@Description Checks if tasklets are supported by the e500 interrupt handler.
@Retval TRUE - Tasklets are supported.
@Retval FALSE - Tasklets are not supported.
*//***************************************************************************/
bool E500_IsTaskletSupported(void);
void E500_EnableTimeBase(void);
void E500_DisableTimeBase(void);
uint64_t E500_GetTimeBaseTime(void);
void E500_GenericIntrInit(void);
t_Error E500_SetIntr(int ppcIntrSrc,
void (* Isr)(t_Handle handle),
t_Handle handle);
t_Error E500_ClearIntr(int ppcIntrSrc);
/**************************************************************************//**
@Function E500_GenericIntrHandler
@Description This is the general e500 interrupt handler.
It is called by the main assembly interrupt handler
when an exception occurs and no other function has been
assigned to this exception.
@Param intrEntry - (In) The exception interrupt vector entry.
*//***************************************************************************/
void E500_GenericIntrHandler(uint32_t intrEntry);
/**************************************************************************//**
@Function CriticalIntr
@Description This is the specific critical e500 interrupt handler.
It is called by the main assembly interrupt handler
when an critical interrupt.
@Param intrEntry - (In) The exception interrupt vector entry.
*//***************************************************************************/
void CriticalIntr(uint32_t intrEntry);
/**************************************************************************//**
@Function E500_GetId
@Description Returns the core ID in the system.
@Return Core ID.
*//***************************************************************************/
uint32_t E500_GetId(void);
/**************************************************************************//**
@Function E500_TestAndSet
@Description This routine tries to atomically test-and-set an integer
in memory to a non-zero value.
The memory will be set only if it is tested as zero, in which
case the routine returns the new non-zero value; otherwise the
routine returns zero.
@Param[in] p - pointer to a volatile int in memory, on which test-and-set
operation should be made.
@Retval Zero - Operation failed - memory was already set.
@Retval Non-zero - Operation succeeded - memory has been set.
*//***************************************************************************/
int E500_TestAndSet(volatile int *p);
/**************************************************************************//**
@Function E500_MemoryBarrier
@Description This routine will cause the core to stop executing any commands
until all previous memory read/write commands are completely out
of the core's pipeline.
@Return None.
*//***************************************************************************/
static __inline__ void E500_MemoryBarrier(void)
{
#ifdef CORE_E500MC
__asm__ ("mbar 1");
#else
/**** ERRATA WORK AROUND START ****/
/* ERRATA num: CPU1 */
/* Description: "mbar MO = 1" instruction fails to order caching-inhibited
guarded loads and stores. */
/* "msync" instruction is used instead */
__asm__ ("msync");
/**** ERRATA WORK AROUND END ****/
#endif
}
/**************************************************************************//**
@Function E500_InstructionSync
@Description This routine will cause the core to wait for previous instructions
(including any interrupts they generate) to complete before the
synchronization command executes, which purges all instructions
from the processor's pipeline and refetches the next instruction.
@Return None.
*//***************************************************************************/
static __inline__ void E500_InstructionSync(void)
{
__asm__ ("isync");
}
/** @} */ /* end of E500_init_grp group */
/** @} */ /* end of E500_grp group */
#endif /* __E500V2_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File ppc_ext.h
@Description Core API for PowerPC cores
These routines must be implemented by each specific PowerPC
core driver.
*//***************************************************************************/
#ifndef __PPC_EXT_H
#define __PPC_EXT_H
#include "part_ext.h"
#define CORE_IS_BIG_ENDIAN
/**************************************************************************//**
@Function CORE_TestAndSet
@Description This routine tries to atomically test-and-set an integer
in memory to a non-zero value.
The memory will be set only if it is tested as zero, in which
case the routine returns the new non-zero value; otherwise the
routine returns zero.
@Param[in] p - pointer to a volatile int in memory, on which test-and-set
operation should be made.
@Retval Zero - Operation failed - memory was already set.
@Retval Non-zero - Operation succeeded - memory has been set.
*//***************************************************************************/
int CORE_TestAndSet(volatile int *p);
/**************************************************************************//**
@Function CORE_InstructionSync
@Description This routine will cause the core to wait for previous instructions
(including any interrupts they generate) to complete before the
synchronization command executes, which purges all instructions
from the processor's pipeline and refetches the next instruction.
@Return None.
*//***************************************************************************/
void CORE_InstructionSync(void);
/**************************************************************************//**
@Function CORE_DCacheEnable
@Description Enables the data cache for memory pages that are
not cache inhibited.
@Return None.
*//***************************************************************************/
void CORE_DCacheEnable(void);
/**************************************************************************//**
@Function CORE_ICacheEnable
@Description Enables the instruction cache for memory pages that are
not cache inhibited.
@Return None.
*//***************************************************************************/
void CORE_ICacheEnable(void);
/**************************************************************************//**
@Function CORE_DCacheDisable
@Description Disables the data cache.
@Return None.
*//***************************************************************************/
void CORE_DCacheDisable(void);
/**************************************************************************//**
@Function CORE_ICacheDisable
@Description Disables the instruction cache.
@Return None.
*//***************************************************************************/
void CORE_ICacheDisable(void);
#if defined(CORE_E300)
#include "e300_ext.h"
#elif defined(CORE_E500V2) || defined(CORE_E500MC)
#include "e500v2_ext.h"
#else
#error "Core not defined!"
#endif
#endif /* __PPC_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CTYPE_EXT_H
#define __CTYPE_EXT_H
#if defined(NCSW_LINUX) && defined(__KERNEL__) || defined(NCSW_FREEBSD)
/*
* NOTE! This ctype does not handle EOF like the standard C
* library is required to.
*/
#define _U 0x01 /* upper */
#define _L 0x02 /* lower */
#define _D 0x04 /* digit */
#define _C 0x08 /* cntrl */
#define _P 0x10 /* punct */
#define _S 0x20 /* white space (space/lf/tab) */
#define _X 0x40 /* hex digit */
#define _SP 0x80 /* hard space (0x20) */
extern unsigned char _ctype[];
#define __ismask(x) (_ctype[(int)(unsigned char)(x)])
#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0)
#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0)
#define iscntrl(c) ((__ismask(c)&(_C)) != 0)
#define isdigit(c) ((__ismask(c)&(_D)) != 0)
#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0)
#define islower(c) ((__ismask(c)&(_L)) != 0)
#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0)
#define ispunct(c) ((__ismask(c)&(_P)) != 0)
#define isspace(c) ((__ismask(c)&(_S)) != 0)
#define isupper(c) ((__ismask(c)&(_U)) != 0)
#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0)
#define isascii(c) (((unsigned char)(c))<=0x7f)
#define toascii(c) (((unsigned char)(c))&0x7f)
static __inline__ unsigned char __tolower(unsigned char c)
{
if (isupper(c))
c -= 'A'-'a';
return c;
}
static __inline__ unsigned char __toupper(unsigned char c)
{
if (islower(c))
c -= 'a'-'A';
return c;
}
#define tolower(c) __tolower(c)
#define toupper(c) __toupper(c)
#else
#include <ctype.h>
#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) || defined(NCSW_FREEBSD) */
#endif /* __CTYPE_EXT_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
#ifndef __DDR_SDT_EXT_H
#define __DDR_SDT_EXT_H
/**************************************************************************//**
@Group ddr_Generic_Resources
@Description ddr generic functions, definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description SPD maximum size
*//***************************************************************************/
#define SPD_MAX_SIZE 256
/**************************************************************************//**
@Description DDR types select
*//***************************************************************************/
typedef enum e_DdrType
{
e_DDR_DDR1,
e_DDR_DDR2,
e_DDR_DDR3,
e_DDR_DDR3L
} e_DdrType;
/**************************************************************************//**
@Description DDR Mode.
*//***************************************************************************/
typedef enum e_DdrMode
{
e_DDR_BUS_WIDTH_32BIT,
e_DDR_BUS_WIDTH_64BIT
} e_DdrMode;
/** @} */ /* end of ddr_Generic_Resources group */
#endif /* __DDR_SDT_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File debug_ext.h
@Description Debug mode definitions.
*//***************************************************************************/
#ifndef __DEBUG_EXT_H
#define __DEBUG_EXT_H
#include "std_ext.h"
#include "xx_ext.h"
#include "memcpy_ext.h"
#if (DEBUG_ERRORS > 0)
#include "sprint_ext.h"
#include "string_ext.h"
#endif /* DEBUG_ERRORS > 0 */
#if (DEBUG_ERRORS > 0)
/* Internally used macros */
#define DUMP_Print XX_Print
#define DUMP_MAX_LEVELS 6
#define DUMP_MAX_STR 64
#define _CREATE_DUMP_SUBSTR(phrase) \
dumpTmpLevel = 0; dumpSubStr[0] = '\0'; \
sprintf(dumpTmpStr, "%s", #phrase); \
p_DumpToken = strtok(dumpTmpStr, (dumpIsArr[0] ? "[" : ".")); \
while (p_DumpToken != NULL) \
{ \
strcat(dumpSubStr, p_DumpToken); \
if (dumpIsArr[dumpTmpLevel]) \
{ \
strcat(dumpSubStr, dumpIdxStr[dumpTmpLevel]); \
p_DumpToken = strtok(NULL, "."); \
} \
if ((p_DumpToken = strtok(NULL, (dumpIsArr[++dumpTmpLevel] ? "[" : "."))) != 0) \
strcat(dumpSubStr, "."); \
}\
/**************************************************************************//**
@Group gen_id General Drivers Utilities
@Description External routines.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group dump_id Memory and Registers Dump Mechanism
@Description Macros for dumping memory mapped structures.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Declaration of dump mechanism variables.
This macro must be declared at the beginning of each routine
which uses the dump mechanism macros, before the routine's code
starts.
*//***************************************************************************/
#define DECLARE_DUMP \
char dumpIdxStr[DUMP_MAX_LEVELS + 1][6] = { "", }; \
char dumpSubStr[DUMP_MAX_STR] = ""; \
char dumpTmpStr[DUMP_MAX_STR] = ""; \
char *p_DumpToken = NULL; \
int dumpArrIdx = 0, dumpArrSize = 0, dumpVarSize = 0, dumpLevel = 0, dumpTmpLevel = 0; \
uint8_t dumpIsArr[DUMP_MAX_LEVELS + 1] = { 0 }; \
/* Prevent warnings if not all used */ \
UNUSED(dumpIdxStr[0][0]); \
UNUSED(dumpSubStr[0]); \
UNUSED(dumpTmpStr[0]); \
UNUSED(p_DumpToken); \
UNUSED(dumpArrIdx); \
UNUSED(dumpArrSize); \
UNUSED(dumpVarSize); \
UNUSED(dumpLevel); \
UNUSED(dumpTmpLevel); \
UNUSED(dumpIsArr[0]);
/**************************************************************************//**
@Description Prints a title for a subsequent dumped structure or memory.
The inputs for this macro are the structure/memory title and
its base addresses.
*//***************************************************************************/
#define DUMP_TITLE(addr, msg) \
DUMP_Print("\r\n"); DUMP_Print msg; \
DUMP_Print(" (0x%p)\r\n" \
"---------------------------------------------------------\r\n", \
(addr))
/**************************************************************************//**
@Description Prints a subtitle for a subsequent dumped sub-structure (optional).
The inputs for this macro are the sub-structure subtitle.
A separating line with this subtitle will be printed.
*//***************************************************************************/
#define DUMP_SUBTITLE(subtitle) \
DUMP_Print("----------- "); DUMP_Print subtitle; DUMP_Print("\r\n")
/**************************************************************************//**
@Description Dumps a memory region in 4-bytes aligned format.
The inputs for this macro are the base addresses and size
(in bytes) of the memory region.
*//***************************************************************************/
#define DUMP_MEMORY(addr, size) \
MemDisp((uint8_t *)(addr), (int)(size))
/**************************************************************************//**
@Description Declares a dump loop, for dumping a sub-structure array.
The inputs for this macro are:
- idx: an index variable, for indexing the sub-structure items
inside the loop. This variable must be declared separately
in the beginning of the routine.
- cnt: the number of times to repeat the loop. This number should
equal the number of items in the sub-structures array.
Note, that the body of the loop must be written inside brackets.
*//***************************************************************************/
#define DUMP_SUBSTRUCT_ARRAY(idx, cnt) \
for (idx=0, dumpIsArr[dumpLevel++] = 1; \
(idx < cnt) && sprintf(dumpIdxStr[dumpLevel-1], "[%d]", idx); \
idx++, ((idx < cnt) || ((dumpIsArr[--dumpLevel] = 0) == 0)))
/**************************************************************************//**
@Description Dumps a structure's member variable.
The input for this macro is the full reference for the member
variable, where the structure is referenced using a pointer.
Note, that a members array must be dumped using DUMP_ARR macro,
rather than using this macro.
If the member variable is part of a sub-structure hierarchy,
the full hierarchy (including array indexing) must be specified.
Examples: p_Struct->member
p_Struct->sub.member
p_Struct->sub[i].member
*//***************************************************************************/
#define DUMP_VAR(st, phrase) \
do { \
void *addr = (void *)&((st)->phrase); \
_CREATE_DUMP_SUBSTR(phrase); \
dumpVarSize = sizeof((st)->phrase); \
switch (dumpVarSize) \
{ \
case 1: DUMP_Print("0x%08X: 0x%02x%14s\t%s\r\n", \
addr, GET_UINT8(*(uint8_t*)addr), "", dumpSubStr); break; \
case 2: DUMP_Print("0x%08X: 0x%04x%12s\t%s\r\n", \
addr, GET_UINT16(*(uint16_t*)addr), "", dumpSubStr); break; \
case 4: DUMP_Print("0x%08X: 0x%08x%8s\t%s\r\n", \
addr, GET_UINT32(*(uint32_t*)addr), "", dumpSubStr); break; \
case 8: DUMP_Print("0x%08X: 0x%016llx\t%s\r\n", \
addr, GET_UINT64(*(uint64_t*)addr), dumpSubStr); break; \
default: DUMP_Print("Bad size %d (" #st "->" #phrase ")\r\n", dumpVarSize); \
} \
} while (0)
/**************************************************************************//**
@Description Dumps a structure's members array.
The input for this macro is the full reference for the members
array, where the structure is referenced using a pointer.
If the members array is part of a sub-structure hierarchy,
the full hierarchy (including array indexing) must be specified.
Examples: p_Struct->array
p_Struct->sub.array
p_Struct->sub[i].array
*//***************************************************************************/
#define DUMP_ARR(st, phrase) \
do { \
_CREATE_DUMP_SUBSTR(phrase); \
dumpArrSize = ARRAY_SIZE((st)->phrase); \
dumpVarSize = sizeof((st)->phrase[0]); \
switch (dumpVarSize) \
{ \
case 1: \
for (dumpArrIdx=0; dumpArrIdx < dumpArrSize; dumpArrIdx++) { \
DUMP_Print("0x%08X: 0x%02x%14s\t%s[%d]\r\n", \
&((st)->phrase[dumpArrIdx]), GET_UINT8((st)->phrase[dumpArrIdx]), "", dumpSubStr, dumpArrIdx); \
} break; \
case 2: \
for (dumpArrIdx=0; dumpArrIdx < dumpArrSize; dumpArrIdx++) { \
DUMP_Print("0x%08X: 0x%04x%12s\t%s[%d]\r\n", \
&((st)->phrase[dumpArrIdx]), GET_UINT16((st)->phrase[dumpArrIdx]), "", dumpSubStr, dumpArrIdx); \
} break; \
case 4: \
for (dumpArrIdx=0; dumpArrIdx < dumpArrSize; dumpArrIdx++) { \
DUMP_Print("0x%08X: 0x%08x%8s\t%s[%d]\r\n", \
&((st)->phrase[dumpArrIdx]), GET_UINT32((st)->phrase[dumpArrIdx]), "", dumpSubStr, dumpArrIdx); \
} break; \
case 8: \
for (dumpArrIdx=0; dumpArrIdx < dumpArrSize; dumpArrIdx++) { \
DUMP_Print("0x%08X: 0x%016llx\t%s[%d]\r\n", \
&((st)->phrase[dumpArrIdx]), GET_UINT64((st)->phrase[dumpArrIdx]), dumpSubStr, dumpArrIdx); \
} break; \
default: DUMP_Print("Bad size %d (" #st "->" #phrase "[0])\r\n", dumpVarSize); \
} \
} while (0)
#endif /* DEBUG_ERRORS > 0 */
/** @} */ /* end of dump_id group */
/** @} */ /* end of gen_id group */
#endif /* __DEBUG_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File endian_ext.h
@Description Big/little endian swapping routines.
*//***************************************************************************/
#ifndef __ENDIAN_EXT_H
#define __ENDIAN_EXT_H
#include "std_ext.h"
/**************************************************************************//**
@Group gen_id General Drivers Utilities
@Description General usage API. This API is intended for usage by both the
internal modules and the user's application.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group endian_id Big/Little-Endian Conversion
@Description Routines and macros for Big/Little-Endian conversion and
general byte swapping.
All routines and macros are expecting unsigned values as
parameters, but will generate the correct result also for
signed values. Therefore, signed/unsigned casting is allowed.
@{
*//***************************************************************************/
/**************************************************************************//**
@Collection Byte-Swap Macros
Macros for swapping byte order.
@Cautions The parameters of these macros are evaluated multiple times.
For calculated expressions or expressions that contain function
calls it is recommended to use the byte-swap routines.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Swaps the byte order of a given 16-bit value.
@Param[in] val - The 16-bit value to swap.
@Return The byte-swapped value..
@Cautions The given value is evaluated multiple times by this macro.
For calculated expressions or expressions that contain function
calls it is recommended to use the SwapUint16() routine.
@hideinitializer
*//***************************************************************************/
#define SWAP_UINT16(val) \
((uint16_t)((((val) & 0x00FF) << 8) | (((val) & 0xFF00) >> 8)))
/**************************************************************************//**
@Description Swaps the byte order of a given 32-bit value.
@Param[in] val - The 32-bit value to swap.
@Return The byte-swapped value..
@Cautions The given value is evaluated multiple times by this macro.
For calculated expressions or expressions that contain function
calls it is recommended to use the SwapUint32() routine.
@hideinitializer
*//***************************************************************************/
#define SWAP_UINT32(val) \
((uint32_t)((((val) & 0x000000FF) << 24) | \
(((val) & 0x0000FF00) << 8) | \
(((val) & 0x00FF0000) >> 8) | \
(((val) & 0xFF000000) >> 24)))
/**************************************************************************//**
@Description Swaps the byte order of a given 64-bit value.
@Param[in] val - The 64-bit value to swap.
@Return The byte-swapped value..
@Cautions The given value is evaluated multiple times by this macro.
For calculated expressions or expressions that contain function
calls it is recommended to use the SwapUint64() routine.
@hideinitializer
*//***************************************************************************/
#define SWAP_UINT64(val) \
((uint64_t)((((val) & 0x00000000000000FFULL) << 56) | \
(((val) & 0x000000000000FF00ULL) << 40) | \
(((val) & 0x0000000000FF0000ULL) << 24) | \
(((val) & 0x00000000FF000000ULL) << 8) | \
(((val) & 0x000000FF00000000ULL) >> 8) | \
(((val) & 0x0000FF0000000000ULL) >> 24) | \
(((val) & 0x00FF000000000000ULL) >> 40) | \
(((val) & 0xFF00000000000000ULL) >> 56)))
/* @} */
/**************************************************************************//**
@Collection Byte-Swap Routines
Routines for swapping the byte order of a given parameter and
returning the swapped value.
These inline routines are safer than the byte-swap macros,
because they evaluate the parameter expression only once.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function SwapUint16
@Description Returns the byte-swapped value of a given 16-bit value.
@Param[in] val - The 16-bit value.
@Return The byte-swapped value of the parameter.
*//***************************************************************************/
static __inline__ uint16_t SwapUint16(uint16_t val)
{
return (uint16_t)(((val & 0x00FF) << 8) |
((val & 0xFF00) >> 8));
}
/**************************************************************************//**
@Function SwapUint32
@Description Returns the byte-swapped value of a given 32-bit value.
@Param[in] val - The 32-bit value.
@Return The byte-swapped value of the parameter.
*//***************************************************************************/
static __inline__ uint32_t SwapUint32(uint32_t val)
{
return (uint32_t)(((val & 0x000000FF) << 24) |
((val & 0x0000FF00) << 8) |
((val & 0x00FF0000) >> 8) |
((val & 0xFF000000) >> 24));
}
/**************************************************************************//**
@Function SwapUint64
@Description Returns the byte-swapped value of a given 64-bit value.
@Param[in] val - The 64-bit value.
@Return The byte-swapped value of the parameter.
*//***************************************************************************/
static __inline__ uint64_t SwapUint64(uint64_t val)
{
return (uint64_t)(((val & 0x00000000000000FFULL) << 56) |
((val & 0x000000000000FF00ULL) << 40) |
((val & 0x0000000000FF0000ULL) << 24) |
((val & 0x00000000FF000000ULL) << 8) |
((val & 0x000000FF00000000ULL) >> 8) |
((val & 0x0000FF0000000000ULL) >> 24) |
((val & 0x00FF000000000000ULL) >> 40) |
((val & 0xFF00000000000000ULL) >> 56));
}
/* @} */
/**************************************************************************//**
@Collection In-place Byte-Swap-And-Set Routines
Routines for swapping the byte order of a given variable and
setting the swapped value back to the same variable.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function SwapUint16P
@Description Swaps the byte order of a given 16-bit variable.
@Param[in] p_Val - Pointer to the 16-bit variable.
@Return None.
*//***************************************************************************/
static __inline__ void SwapUint16P(uint16_t *p_Val)
{
*p_Val = SwapUint16(*p_Val);
}
/**************************************************************************//**
@Function SwapUint32P
@Description Swaps the byte order of a given 32-bit variable.
@Param[in] p_Val - Pointer to the 32-bit variable.
@Return None.
*//***************************************************************************/
static __inline__ void SwapUint32P(uint32_t *p_Val)
{
*p_Val = SwapUint32(*p_Val);
}
/**************************************************************************//**
@Function SwapUint64P
@Description Swaps the byte order of a given 64-bit variable.
@Param[in] p_Val - Pointer to the 64-bit variable.
@Return None.
*//***************************************************************************/
static __inline__ void SwapUint64P(uint64_t *p_Val)
{
*p_Val = SwapUint64(*p_Val);
}
/* @} */
/**************************************************************************//**
@Collection Little-Endian Conversion Macros
These macros convert given parameters to or from Little-Endian
format. Use these macros when you want to read or write a specific
Little-Endian value in memory, without a-priori knowing the CPU
byte order.
These macros use the byte-swap routines. For conversion of
constants in initialization structures, you may use the CONST
versions of these macros (see below), which are using the
byte-swap macros instead.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Converts a given 16-bit value from CPU byte order to
Little-Endian byte order.
@Param[in] val - The 16-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define CPU_TO_LE16(val) SwapUint16(val)
/**************************************************************************//**
@Description Converts a given 32-bit value from CPU byte order to
Little-Endian byte order.
@Param[in] val - The 32-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define CPU_TO_LE32(val) SwapUint32(val)
/**************************************************************************//**
@Description Converts a given 64-bit value from CPU byte order to
Little-Endian byte order.
@Param[in] val - The 64-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define CPU_TO_LE64(val) SwapUint64(val)
/**************************************************************************//**
@Description Converts a given 16-bit value from Little-Endian byte order to
CPU byte order.
@Param[in] val - The 16-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define LE16_TO_CPU(val) CPU_TO_LE16(val)
/**************************************************************************//**
@Description Converts a given 32-bit value from Little-Endian byte order to
CPU byte order.
@Param[in] val - The 32-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define LE32_TO_CPU(val) CPU_TO_LE32(val)
/**************************************************************************//**
@Description Converts a given 64-bit value from Little-Endian byte order to
CPU byte order.
@Param[in] val - The 64-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define LE64_TO_CPU(val) CPU_TO_LE64(val)
/* @} */
/**************************************************************************//**
@Collection Little-Endian Constant Conversion Macros
These macros convert given constants to or from Little-Endian
format. Use these macros when you want to read or write a specific
Little-Endian constant in memory, without a-priori knowing the
CPU byte order.
These macros use the byte-swap macros, therefore can be used for
conversion of constants in initialization structures.
@Cautions The parameters of these macros are evaluated multiple times.
For non-constant expressions, use the non-CONST macro versions.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Converts a given 16-bit constant from CPU byte order to
Little-Endian byte order.
@Param[in] val - The 16-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define CONST_CPU_TO_LE16(val) SWAP_UINT16(val)
/**************************************************************************//**
@Description Converts a given 32-bit constant from CPU byte order to
Little-Endian byte order.
@Param[in] val - The 32-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define CONST_CPU_TO_LE32(val) SWAP_UINT32(val)
/**************************************************************************//**
@Description Converts a given 64-bit constant from CPU byte order to
Little-Endian byte order.
@Param[in] val - The 64-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define CONST_CPU_TO_LE64(val) SWAP_UINT64(val)
/**************************************************************************//**
@Description Converts a given 16-bit constant from Little-Endian byte order
to CPU byte order.
@Param[in] val - The 16-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define CONST_LE16_TO_CPU(val) CONST_CPU_TO_LE16(val)
/**************************************************************************//**
@Description Converts a given 32-bit constant from Little-Endian byte order
to CPU byte order.
@Param[in] val - The 32-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define CONST_LE32_TO_CPU(val) CONST_CPU_TO_LE32(val)
/**************************************************************************//**
@Description Converts a given 64-bit constant from Little-Endian byte order
to CPU byte order.
@Param[in] val - The 64-bit value to convert.
@Return The converted value.
@hideinitializer
*//***************************************************************************/
#define CONST_LE64_TO_CPU(val) CONST_CPU_TO_LE64(val)
/* @} */
/** @} */ /* end of endian_id group */
/** @} */ /* end of gen_id group */
#endif /* __ENDIAN_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File enet_ext.h
@Description Ethernet generic definitions and enums.
*//***************************************************************************/
#ifndef __ENET_EXT_H
#define __ENET_EXT_H
#define ENET_NUM_OCTETS_PER_ADDRESS 6 /**< Number of octets (8-bit bytes) in an ethernet address */
#define ENET_GROUP_ADDR 0x01 /**< Group address mask for ethernet addresses */
/**************************************************************************//**
@Description Ethernet Address
*//***************************************************************************/
typedef uint8_t t_EnetAddr[ENET_NUM_OCTETS_PER_ADDRESS];
/**************************************************************************//**
@Description Ethernet Address Type.
*//***************************************************************************/
typedef enum e_EnetAddrType
{
e_ENET_ADDR_TYPE_INDIVIDUAL, /**< Individual (unicast) address */
e_ENET_ADDR_TYPE_GROUP, /**< Group (multicast) address */
e_ENET_ADDR_TYPE_BROADCAST /**< Broadcast address */
} e_EnetAddrType;
/**************************************************************************//**
@Description Ethernet MAC-PHY Interface
*//***************************************************************************/
typedef enum e_EnetInterface
{
e_ENET_IF_MII = 0x00010000, /**< MII interface */
e_ENET_IF_RMII = 0x00020000, /**< RMII interface */
e_ENET_IF_SMII = 0x00030000, /**< SMII interface */
e_ENET_IF_GMII = 0x00040000, /**< GMII interface */
e_ENET_IF_RGMII = 0x00050000, /**< RGMII interface */
e_ENET_IF_TBI = 0x00060000, /**< TBI interface */
e_ENET_IF_RTBI = 0x00070000, /**< RTBI interface */
e_ENET_IF_SGMII = 0x00080000, /**< SGMII interface */
e_ENET_IF_XGMII = 0x00090000, /**< XGMII interface */
e_ENET_IF_QSGMII= 0x000a0000 /**< QSGMII interface */
} e_EnetInterface;
/**************************************************************************//**
@Description Ethernet Duplex Mode
*//***************************************************************************/
typedef enum e_EnetDuplexMode
{
e_ENET_HALF_DUPLEX, /**< Half-Duplex mode */
e_ENET_FULL_DUPLEX /**< Full-Duplex mode */
} e_EnetDuplexMode;
/**************************************************************************//**
@Description Ethernet Speed (nominal data rate)
*//***************************************************************************/
typedef enum e_EnetSpeed
{
e_ENET_SPEED_10 = 10, /**< 10 Mbps */
e_ENET_SPEED_100 = 100, /**< 100 Mbps */
e_ENET_SPEED_1000 = 1000, /**< 1000 Mbps = 1 Gbps */
e_ENET_SPEED_10000 = 10000 /**< 10000 Mbps = 10 Gbps */
} e_EnetSpeed;
/**************************************************************************//**
@Description Ethernet mode (combination of MAC-PHY interface and speed)
*//***************************************************************************/
typedef enum e_EnetMode
{
e_ENET_MODE_INVALID = 0, /**< Invalid Ethernet mode */
e_ENET_MODE_MII_10 = (e_ENET_IF_MII | e_ENET_SPEED_10), /**< 10 Mbps MII */
e_ENET_MODE_MII_100 = (e_ENET_IF_MII | e_ENET_SPEED_100), /**< 100 Mbps MII */
e_ENET_MODE_RMII_10 = (e_ENET_IF_RMII | e_ENET_SPEED_10), /**< 10 Mbps RMII */
e_ENET_MODE_RMII_100 = (e_ENET_IF_RMII | e_ENET_SPEED_100), /**< 100 Mbps RMII */
e_ENET_MODE_SMII_10 = (e_ENET_IF_SMII | e_ENET_SPEED_10), /**< 10 Mbps SMII */
e_ENET_MODE_SMII_100 = (e_ENET_IF_SMII | e_ENET_SPEED_100), /**< 100 Mbps SMII */
e_ENET_MODE_GMII_1000 = (e_ENET_IF_GMII | e_ENET_SPEED_1000), /**< 1000 Mbps GMII */
e_ENET_MODE_RGMII_10 = (e_ENET_IF_RGMII | e_ENET_SPEED_10), /**< 10 Mbps RGMII */
e_ENET_MODE_RGMII_100 = (e_ENET_IF_RGMII | e_ENET_SPEED_100), /**< 100 Mbps RGMII */
e_ENET_MODE_RGMII_1000 = (e_ENET_IF_RGMII | e_ENET_SPEED_1000), /**< 1000 Mbps RGMII */
e_ENET_MODE_TBI_1000 = (e_ENET_IF_TBI | e_ENET_SPEED_1000), /**< 1000 Mbps TBI */
e_ENET_MODE_RTBI_1000 = (e_ENET_IF_RTBI | e_ENET_SPEED_1000), /**< 1000 Mbps RTBI */
e_ENET_MODE_SGMII_10 = (e_ENET_IF_SGMII | e_ENET_SPEED_10), /**< 10 Mbps SGMII */
e_ENET_MODE_SGMII_100 = (e_ENET_IF_SGMII | e_ENET_SPEED_100), /**< 100 Mbps SGMII */
e_ENET_MODE_SGMII_1000 = (e_ENET_IF_SGMII | e_ENET_SPEED_1000), /**< 1000 Mbps SGMII */
e_ENET_MODE_XGMII_10000 = (e_ENET_IF_XGMII | e_ENET_SPEED_10000), /**< 10000 Mbps XGMII */
e_ENET_MODE_QSGMII_1000 = (e_ENET_IF_QSGMII| e_ENET_SPEED_1000) /**< 1000 Mbps QSGMII */
} e_EnetMode;
#define IS_ENET_MODE_VALID(mode) \
(((mode) == e_ENET_MODE_MII_10 ) || \
((mode) == e_ENET_MODE_MII_100 ) || \
((mode) == e_ENET_MODE_RMII_10 ) || \
((mode) == e_ENET_MODE_RMII_100 ) || \
((mode) == e_ENET_MODE_SMII_10 ) || \
((mode) == e_ENET_MODE_SMII_100 ) || \
((mode) == e_ENET_MODE_GMII_1000 ) || \
((mode) == e_ENET_MODE_RGMII_10 ) || \
((mode) == e_ENET_MODE_RGMII_100 ) || \
((mode) == e_ENET_MODE_RGMII_1000 ) || \
((mode) == e_ENET_MODE_TBI_1000 ) || \
((mode) == e_ENET_MODE_RTBI_1000 ) || \
((mode) == e_ENET_MODE_SGMII_10 ) || \
((mode) == e_ENET_MODE_SGMII_100 ) || \
((mode) == e_ENET_MODE_SGMII_1000 ) || \
((mode) == e_ENET_MODE_XGMII_10000) || \
((mode) == e_ENET_MODE_QSGMII_1000))
#define MAKE_ENET_MODE(_interface, _speed) (e_EnetMode)((_interface) | (_speed))
#define ENET_INTERFACE_FROM_MODE(mode) (e_EnetInterface)((mode) & 0xFFFF0000)
#define ENET_SPEED_FROM_MODE(mode) (e_EnetSpeed)((mode) & 0x0000FFFF)
#endif /* __ENET_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
@File error_ext.h
@Description Error definitions.
*//***************************************************************************/
#ifndef __ERROR_EXT_H
#define __ERROR_EXT_H
#include "std_ext.h"
#include "xx_ext.h"
#include "core_ext.h"
/**************************************************************************//**
@Group gen_id General Drivers Utilities
@Description External routines.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group gen_error_id Errors, Events and Debug
@Description External routines.
@{
*//***************************************************************************/
/******************************************************************************
The scheme below provides the bits description for error codes:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
| Reserved (should be zero) | Module ID |
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
| Error Type |
******************************************************************************/
#define ERROR_CODE(_err) ((((uint32_t)_err) & 0x0000FFFF) | __ERR_MODULE__)
#define GET_ERROR_TYPE(_errcode) ((_errcode) & 0x0000FFFF)
/**< Extract module code from error code (#t_Error) */
#define GET_ERROR_MODULE(_errcode) ((_errcode) & 0x00FF0000)
/**< Extract error type (#e_ErrorType) from
error code (#t_Error) */
/**************************************************************************//**
@Description Error Type Enumeration
*//***************************************************************************/
typedef enum e_ErrorType /* Comments / Associated Message Strings */
{ /* ------------------------------------------------------------ */
E_OK = 0 /* Never use "RETURN_ERROR" with E_OK; Use "return E_OK;" */
/* Invalid Function Calls */
,E_INVALID_STATE /**< The operation is not allowed in current module state. */
/* String: none. */
,E_INVALID_OPERATION /**< The operation/command is invalid (unrecognized). */
/* String: none. */
,E_NOT_SUPPORTED /**< The function is not supported or not implemented. */
/* String: none. */
,E_NO_DEVICE /**< The associated device is not initialized. */
/* String: none. */
/* Invalid Parameters */
,E_INVALID_HANDLE /**< Invalid handle of module or object. */
/* String: none, unless the function takes in more than one
handle (in this case add the handle description) */
,E_INVALID_ID /**< Invalid module ID (usually enumeration or index). */
/* String: none, unless the function takes in more than one
ID (in this case add the ID description) */
,E_NULL_POINTER /**< Unexpected NULL pointer. */
/* String: pointer description. */
,E_INVALID_VALUE /**< Invalid value. */
/* Use for non-enumeration parameters, and
only when other error types are not suitable.
String: parameter description + "(should be <attribute>)",
e.g: "Maximum Rx buffer length (should be divisible by 8)",
"Channel number (should be even)". */
,E_INVALID_SELECTION /**< Invalid selection or mode. */
/* Use for enumeration values, only when other error types
are not suitable.
String: parameter description. */
,E_INVALID_COMM_MODE /**< Invalid communication mode. */
/* String: none, unless the function takes in more than one
communication mode indications (in this case add
parameter description). */
,E_INVALID_BYTE_ORDER /**< Invalid byte order. */
/* String: none, unless the function takes in more than one
byte order indications (in this case add parameter
description). */
,E_INVALID_MEMORY_TYPE /**< Invalid memory type. */
/* String: none, unless the function takes in more than one
memory types (in this case add memory description,
e.g: "Data memory", "Buffer descriptors memory"). */
,E_INVALID_INTR_QUEUE /**< Invalid interrupt queue. */
/* String: none, unless the function takes in more than one
interrupt queues (in this case add queue description,
e.g: "Rx interrupt queue", "Tx interrupt queue"). */
,E_INVALID_PRIORITY /**< Invalid priority. */
/* String: none, unless the function takes in more than one
priority (in this case add priority description). */
,E_INVALID_CLOCK /**< Invalid clock. */
/* String: none, unless the function takes in more than one
clocks (in this case add clock description,
e.g: "Rx clock", "Tx clock"). */
,E_INVALID_RATE /**< Invalid rate value. */
/* String: none, unless the function takes in more than one
rate values (in this case add rate description). */
,E_INVALID_ADDRESS /**< Invalid address. */
/* String: description of the specific violation. */
,E_INVALID_BUS /**< Invalid bus type. */
/* String: none, unless the function takes in more than one
bus parameters (in this case add bus description). */
,E_BUS_CONFLICT /**< Bus (or memory) type conflicts with another setting. */
/* String: description of the conflicting buses/memories. */
,E_CONFLICT /**< Some setting conflicts with another setting. */
/* String: description of the conflicting settings. */
,E_NOT_ALIGNED /**< Non-aligned address. */
/* String: parameter description + "(should be %d-bytes aligned)",
e.g: "Rx data buffer (should be 32-bytes aligned)". */
,E_NOT_IN_RANGE /**< Parameter value is out of range. */
/* Don't use this error for enumeration parameters.
String: parameter description + "(should be %d-%d)",
e.g: "Number of pad characters (should be 0-15)". */
/* Frame/Buffer Errors */
,E_INVALID_FRAME /**< Invalid frame object (NULL handle or missing buffers). */
/* String: none. */
,E_EMPTY_FRAME /**< Frame object is empty (has no buffers). */
/* String: none. */
,E_EMPTY_BUFFER /**< Buffer object is empty (no data, or zero data length). */
/* String: none. */
/* Resource Errors */
,E_NO_MEMORY /**< External memory allocation failed. */
/* String: description of item for which allocation failed. */
,E_NOT_FOUND /**< Requested resource or item was not found. */
/* Use only when the resource/item is uniquely identified.
String: none, unless the operation is not the main goal
of the function (in this case add item description). */
,E_NOT_AVAILABLE /**< Resource is unavailable. */
/* String: none, unless the operation is not the main goal
of the function (in this case add resource description). */
,E_ALREADY_EXISTS /**< Requested resource or item already exists. */
/* Use when resource duplication or sharing are not allowed.
String: none, unless the operation is not the main goal
of the function (in this case add item description). */
,E_FULL /**< Resource is full. */
/* String: none, unless the operation is not the main goal
of the function (in this case add resource description). */
,E_EMPTY /**< Resource is empty. */
/* String: none, unless the operation is not the main goal
of the function (in this case add resource description). */
,E_BUSY /**< Resource or module is busy. */
/* String: none, unless the operation is not the main goal
of the function (in this case add resource description). */
,E_ALREADY_FREE /**< Specified resource or item is already free or deleted. */
/* String: none, unless the operation is not the main goal
of the function (in this case add item description). */
/* Read/Write Access Errors */
,E_READ_FAILED /**< Read access failed on memory/device. */
/* String: none, or device name. */
,E_WRITE_FAILED /**< Write access failed on memory/device. */
/* String: none, or device name. */
/* Send/Receive Failures */
,E_SEND_FAILED /**< Send operation failed on device. */
/* String: none, or device name. */
,E_RECEIVE_FAILED /**< Receive operation failed on device. */
/* String: none, or device name. */
/* Operation time-out */
,E_TIMEOUT /**< The operation timed out. */
/* String: none. */
,E_DUMMY_LAST /* NEVER USED */
} e_ErrorType;
/**************************************************************************//**
@Description Event Type Enumeration
*//***************************************************************************/
typedef enum e_Event /* Comments / Associated Flags and Message Strings */
{ /* ------------------------------------------------------------ */
EV_NO_EVENT = 0 /**< No event; Never used. */
,EV_RX_DISCARD /**< Received packet discarded (by the driver, and only for
complete packets);
Flags: error flags in case of error, zero otherwise. */
/* String: reason for discard, e.g: "Error in frame",
"Disordered frame", "Incomplete frame", "No frame object". */
,EV_RX_ERROR /**< Receive error (by hardware/firmware);
Flags: usually status flags from the buffer descriptor. */
/* String: none. */
,EV_TX_ERROR /**< Transmit error (by hardware/firmware);
Flags: usually status flags from the buffer descriptor. */
/* String: none. */
,EV_NO_BUFFERS /**< System ran out of buffer objects;
Flags: zero. */
/* String: none. */
,EV_NO_MB_FRAMES /**< System ran out of multi-buffer frame objects;
Flags: zero. */
/* String: none. */
,EV_NO_SB_FRAMES /**< System ran out of single-buffer frame objects;
Flags: zero. */
/* String: none. */
,EV_TX_QUEUE_FULL /**< Transmit queue is full;
Flags: zero. */
/* String: none. */
,EV_RX_QUEUE_FULL /**< Receive queue is full;
Flags: zero. */
/* String: none. */
,EV_INTR_QUEUE_FULL /**< Interrupt queue overflow;
Flags: zero. */
/* String: none. */
,EV_NO_DATA_BUFFER /**< Data buffer allocation (from higher layer) failed;
Flags: zero. */
/* String: none. */
,EV_OBJ_POOL_EMPTY /**< Objects pool is empty;
Flags: zero. */
/* String: object description (name). */
,EV_BUS_ERROR /**< Illegal access on bus;
Flags: the address (if available) or bus identifier */
/* String: bus/address/module description. */
,EV_PTP_TXTS_QUEUE_FULL /**< PTP Tx timestamps queue is full;
Flags: zero. */
/* String: none. */
,EV_PTP_RXTS_QUEUE_FULL /**< PTP Rx timestamps queue is full;
Flags: zero. */
/* String: none. */
,EV_DUMMY_LAST
} e_Event;
/**************************************************************************//**
@Collection Debug Levels for Errors and Events
The level description refers to errors only.
For events, classification is done by the user.
The TRACE, INFO and WARNING levels are allowed only when using
the DBG macro, and are not allowed when using the error macros
(RETURN_ERROR or REPORT_ERROR).
@{
*//***************************************************************************/
#define REPORT_LEVEL_CRITICAL 1 /**< Crasher: Incorrect flow, NULL pointers/handles. */
#define REPORT_LEVEL_MAJOR 2 /**< Cannot proceed: Invalid operation, parameters or
configuration. */
#define REPORT_LEVEL_MINOR 3 /**< Recoverable problem: a repeating call with the same
parameters may be successful. */
#define REPORT_LEVEL_WARNING 4 /**< Something is not exactly right, yet it is not an error. */
#define REPORT_LEVEL_INFO 5 /**< Messages which may be of interest to user/programmer. */
#define REPORT_LEVEL_TRACE 6 /**< Program flow messages. */
#define EVENT_DISABLED 0xFF /**< Disabled event (not reported at all) */
/* @} */
#define NO_MSG ("")
#ifndef DEBUG_GLOBAL_LEVEL
#define DEBUG_GLOBAL_LEVEL REPORT_LEVEL_WARNING
#endif /* DEBUG_GLOBAL_LEVEL */
#ifndef ERROR_GLOBAL_LEVEL
#define ERROR_GLOBAL_LEVEL DEBUG_GLOBAL_LEVEL
#endif /* ERROR_GLOBAL_LEVEL */
#ifndef EVENT_GLOBAL_LEVEL
#define EVENT_GLOBAL_LEVEL REPORT_LEVEL_MINOR
#endif /* EVENT_GLOBAL_LEVEL */
#ifdef EVENT_LOCAL_LEVEL
#define EVENT_DYNAMIC_LEVEL EVENT_LOCAL_LEVEL
#else
#define EVENT_DYNAMIC_LEVEL EVENT_GLOBAL_LEVEL
#endif /* EVENT_LOCAL_LEVEL */
#ifndef DEBUG_DYNAMIC_LEVEL
#define DEBUG_USING_STATIC_LEVEL
#ifdef DEBUG_STATIC_LEVEL
#define DEBUG_DYNAMIC_LEVEL DEBUG_STATIC_LEVEL
#else
#define DEBUG_DYNAMIC_LEVEL DEBUG_GLOBAL_LEVEL
#endif /* DEBUG_STATIC_LEVEL */
#else /* DEBUG_DYNAMIC_LEVEL */
#ifdef DEBUG_STATIC_LEVEL
#error "Please use either DEBUG_STATIC_LEVEL or DEBUG_DYNAMIC_LEVEL (not both)"
#else
int DEBUG_DYNAMIC_LEVEL = DEBUG_GLOBAL_LEVEL;
#endif /* DEBUG_STATIC_LEVEL */
#endif /* !DEBUG_DYNAMIC_LEVEL */
#ifndef ERROR_DYNAMIC_LEVEL
#ifdef ERROR_STATIC_LEVEL
#define ERROR_DYNAMIC_LEVEL ERROR_STATIC_LEVEL
#else
#define ERROR_DYNAMIC_LEVEL ERROR_GLOBAL_LEVEL
#endif /* ERROR_STATIC_LEVEL */
#else /* ERROR_DYNAMIC_LEVEL */
#ifdef ERROR_STATIC_LEVEL
#error "Please use either ERROR_STATIC_LEVEL or ERROR_DYNAMIC_LEVEL (not both)"
#else
int ERROR_DYNAMIC_LEVEL = ERROR_GLOBAL_LEVEL;
#endif /* ERROR_STATIC_LEVEL */
#endif /* !ERROR_DYNAMIC_LEVEL */
#define PRINT_FORMAT "[CPU%02d, %s:%d %s]"
#define PRINT_FMT_PARAMS CORE_GetId(), __FILE__, __LINE__, __FUNCTION__
#if (!(defined(DEBUG_ERRORS)) || (DEBUG_ERRORS == 0))
/* No debug/error/event messages at all */
#define DBG(_level, _vmsg)
#define REPORT_ERROR(_level, _err, _vmsg)
#define RETURN_ERROR(_level, _err, _vmsg) \
return ERROR_CODE(_err)
#if (REPORT_EVENTS > 0)
#define REPORT_EVENT(_ev, _appId, _flg, _vmsg) \
do { \
if (_ev##_LEVEL <= EVENT_DYNAMIC_LEVEL) { \
XX_EventById((uint32_t)(_ev), (t_Handle)(_appId), (uint16_t)(_flg), NO_MSG); \
} \
} while (0)
#else
#define REPORT_EVENT(_ev, _appId, _flg, _vmsg)
#endif /* (REPORT_EVENTS > 0) */
#else /* DEBUG_ERRORS > 0 */
extern const char *dbgLevelStrings[];
extern const char *errTypeStrings[];
extern const char *moduleStrings[];
#if (REPORT_EVENTS > 0)
extern const char *eventStrings[];
#endif /* (REPORT_EVENTS > 0) */
#if ((defined(DEBUG_USING_STATIC_LEVEL)) && (DEBUG_DYNAMIC_LEVEL < REPORT_LEVEL_WARNING))
/* No need for DBG macro - debug level is higher anyway */
#define DBG(_level, _vmsg)
#else
#define DBG(_level, _vmsg) \
do { \
if (REPORT_LEVEL_##_level <= DEBUG_DYNAMIC_LEVEL) { \
XX_Print("> %s (%s) " PRINT_FORMAT ": ", \
dbgLevelStrings[REPORT_LEVEL_##_level - 1], \
moduleStrings[__ERR_MODULE__ >> 16], \
PRINT_FMT_PARAMS); \
XX_Print _vmsg; \
XX_Print("\r\n"); \
} \
} while (0)
#endif /* (defined(DEBUG_USING_STATIC_LEVEL) && (DEBUG_DYNAMIC_LEVEL < WARNING)) */
#define REPORT_ERROR(_level, _err, _vmsg) \
do { \
if (REPORT_LEVEL_##_level <= ERROR_DYNAMIC_LEVEL) { \
XX_Print("! %s %s Error " PRINT_FORMAT ": %s; ", \
dbgLevelStrings[REPORT_LEVEL_##_level - 1], \
moduleStrings[__ERR_MODULE__ >> 16], \
PRINT_FMT_PARAMS, \
errTypeStrings[(GET_ERROR_TYPE(_err) - E_OK - 1)]); \
XX_Print _vmsg; \
XX_Print("\r\n"); \
} \
} while (0)
#define RETURN_ERROR(_level, _err, _vmsg) \
do { \
REPORT_ERROR(_level, (_err), _vmsg); \
return ERROR_CODE(_err); \
} while (0)
#if (REPORT_EVENTS > 0)
#define REPORT_EVENT(_ev, _appId, _flg, _vmsg) \
do { \
if (_ev##_LEVEL <= EVENT_DYNAMIC_LEVEL) { \
XX_Print("~ %s %s Event " PRINT_FORMAT ": %s (flags: 0x%04x); ", \
dbgLevelStrings[_ev##_LEVEL - 1], \
moduleStrings[__ERR_MODULE__ >> 16], \
PRINT_FMT_PARAMS, \
eventStrings[((_ev) - EV_NO_EVENT - 1)], \
(uint16_t)(_flg)); \
XX_Print _vmsg; \
XX_Print("\r\n"); \
XX_EventById((uint32_t)(_ev), (t_Handle)(_appId), (uint16_t)(_flg), NO_MSG); \
} \
} while (0)
#else /* not REPORT_EVENTS */
#define REPORT_EVENT(_ev, _appId, _flg, _vmsg)
#endif /* (REPORT_EVENTS > 0) */
#endif /* (DEBUG_ERRORS > 0) */
/**************************************************************************//**
@Function ASSERT_COND
@Description Assertion macro.
@Param[in] _cond - The condition being checked, in positive form;
Failure of the condition triggers the assert.
*//***************************************************************************/
#ifdef DISABLE_ASSERTIONS
#define ASSERT_COND(_cond)
#else
#define ASSERT_COND(_cond) \
do { \
if (!(_cond)) { \
XX_Print("*** ASSERT_COND failed " PRINT_FORMAT "\r\n", \
PRINT_FMT_PARAMS); \
XX_Exit(1); \
} \
} while (0)
#endif /* DISABLE_ASSERTIONS */
#ifdef DISABLE_INIT_PARAMETERS_CHECK
#define CHECK_INIT_PARAMETERS(handle, f_check)
#define CHECK_INIT_PARAMETERS_RETURN_VALUE(handle, f_check, retval)
#else
#define CHECK_INIT_PARAMETERS(handle, f_check) \
do { \
t_Error err = f_check(handle); \
if (err != E_OK) { \
RETURN_ERROR(MAJOR, err, NO_MSG); \
} \
} while (0)
#define CHECK_INIT_PARAMETERS_RETURN_VALUE(handle, f_check, retval) \
do { \
t_Error err = f_check(handle); \
if (err != E_OK) { \
REPORT_ERROR(MAJOR, err, NO_MSG); \
return (retval); \
} \
} while (0)
#endif /* DISABLE_INIT_PARAMETERS_CHECK */
#ifdef DISABLE_SANITY_CHECKS
#define SANITY_CHECK_RETURN_ERROR(_cond, _err)
#define SANITY_CHECK_RETURN_VALUE(_cond, _err, retval)
#define SANITY_CHECK_RETURN(_cond, _err)
#define SANITY_CHECK_EXIT(_cond, _err)
#else /* DISABLE_SANITY_CHECKS */
#define SANITY_CHECK_RETURN_ERROR(_cond, _err) \
do { \
if (!(_cond)) { \
RETURN_ERROR(CRITICAL, (_err), NO_MSG); \
} \
} while (0)
#define SANITY_CHECK_RETURN_VALUE(_cond, _err, retval) \
do { \
if (!(_cond)) { \
REPORT_ERROR(CRITICAL, (_err), NO_MSG); \
return (retval); \
} \
} while (0)
#define SANITY_CHECK_RETURN(_cond, _err) \
do { \
if (!(_cond)) { \
REPORT_ERROR(CRITICAL, (_err), NO_MSG); \
return; \
} \
} while (0)
#define SANITY_CHECK_EXIT(_cond, _err) \
do { \
if (!(_cond)) { \
REPORT_ERROR(CRITICAL, (_err), NO_MSG); \
XX_Exit(1); \
} \
} while (0)
#endif /* DISABLE_SANITY_CHECKS */
/** @} */ /* end of Debug/error Utils group */
/** @} */ /* end of General Utils group */
#endif /* __ERROR_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File list_ext.h
@Description External prototypes for list.c
*//***************************************************************************/
#ifndef __LIST_EXT_H
#define __LIST_EXT_H
#include "std_ext.h"
/**************************************************************************//**
@Group etc_id Utility Library Application Programming Interface
@Description External routines.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group list_id List
@Description List module functions,definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Description List structure.
*//***************************************************************************/
typedef struct List
{
struct List *p_Next; /**< A pointer to the next list object */
struct List *p_Prev; /**< A pointer to the previous list object */
} t_List;
/**************************************************************************//**
@Function NCSW_LIST_FIRST/LIST_LAST/NCSW_LIST_NEXT/NCSW_LIST_PREV
@Description Macro to get first/last/next/previous entry in a list.
@Param[in] p_List - A pointer to a list.
*//***************************************************************************/
#define NCSW_LIST_FIRST(p_List) (p_List)->p_Next
#define LIST_LAST(p_List) (p_List)->p_Prev
#define NCSW_LIST_NEXT NCSW_LIST_FIRST
#define NCSW_LIST_PREV LIST_LAST
/**************************************************************************//**
@Function NCSW_LIST_INIT
@Description Macro for initialization of a list struct.
@Param[in] lst - The t_List object to initialize.
*//***************************************************************************/
#define NCSW_LIST_INIT(lst) {&(lst), &(lst)}
/**************************************************************************//**
@Function LIST
@Description Macro to declare of a list.
@Param[in] listName - The list object name.
*//***************************************************************************/
#define LIST(listName) t_List listName = NCSW_LIST_INIT(listName)
/**************************************************************************//**
@Function INIT_LIST
@Description Macro to initialize a list pointer.
@Param[in] p_List - The list pointer.
*//***************************************************************************/
#define INIT_LIST(p_List) NCSW_LIST_FIRST(p_List) = LIST_LAST(p_List) = (p_List)
/**************************************************************************//**
@Function LIST_OBJECT
@Description Macro to get the struct (object) for this entry.
@Param[in] type - The type of the struct (object) this list is embedded in.
@Param[in] member - The name of the t_List object within the struct.
@Return The structure pointer for this entry.
*//***************************************************************************/
#define MEMBER_OFFSET(type, member) (PTR_TO_UINT(&((type *)0)->member))
#define LIST_OBJECT(p_List, type, member) \
((type *)((char *)(p_List)-MEMBER_OFFSET(type, member)))
/**************************************************************************//**
@Function LIST_FOR_EACH
@Description Macro to iterate over a list.
@Param[in] p_Pos - A pointer to a list to use as a loop counter.
@Param[in] p_Head - A pointer to the head for your list pointer.
@Cautions You can't delete items with this routine.
For deletion use LIST_FOR_EACH_SAFE().
*//***************************************************************************/
#define LIST_FOR_EACH(p_Pos, p_Head) \
for (p_Pos = NCSW_LIST_FIRST(p_Head); p_Pos != (p_Head); p_Pos = NCSW_LIST_NEXT(p_Pos))
/**************************************************************************//**
@Function LIST_FOR_EACH_SAFE
@Description Macro to iterate over a list safe against removal of list entry.
@Param[in] p_Pos - A pointer to a list to use as a loop counter.
@Param[in] p_Tmp - Another pointer to a list to use as temporary storage.
@Param[in] p_Head - A pointer to the head for your list pointer.
*//***************************************************************************/
#define LIST_FOR_EACH_SAFE(p_Pos, p_Tmp, p_Head) \
for (p_Pos = NCSW_LIST_FIRST(p_Head), p_Tmp = NCSW_LIST_FIRST(p_Pos); \
p_Pos != (p_Head); \
p_Pos = p_Tmp, p_Tmp = NCSW_LIST_NEXT(p_Pos))
/**************************************************************************//**
@Function LIST_FOR_EACH_OBJECT_SAFE
@Description Macro to iterate over list of given type safely.
@Param[in] p_Pos - A pointer to a list to use as a loop counter.
@Param[in] p_Tmp - Another pointer to a list to use as temporary storage.
@Param[in] type - The type of the struct this is embedded in.
@Param[in] p_Head - A pointer to the head for your list pointer.
@Param[in] member - The name of the list_struct within the struct.
@Cautions You can't delete items with this routine.
For deletion use LIST_FOR_EACH_SAFE().
*//***************************************************************************/
#define LIST_FOR_EACH_OBJECT_SAFE(p_Pos, p_Tmp, p_Head, type, member) \
for (p_Pos = LIST_OBJECT(NCSW_LIST_FIRST(p_Head), type, member), \
p_Tmp = LIST_OBJECT(NCSW_LIST_FIRST(&p_Pos->member), type, member); \
&p_Pos->member != (p_Head); \
p_Pos = p_Tmp, \
p_Tmp = LIST_OBJECT(NCSW_LIST_FIRST(&p_Pos->member), type, member))
/**************************************************************************//**
@Function LIST_FOR_EACH_OBJECT
@Description Macro to iterate over list of given type.
@Param[in] p_Pos - A pointer to a list to use as a loop counter.
@Param[in] type - The type of the struct this is embedded in.
@Param[in] p_Head - A pointer to the head for your list pointer.
@Param[in] member - The name of the list_struct within the struct.
@Cautions You can't delete items with this routine.
For deletion use LIST_FOR_EACH_SAFE().
*//***************************************************************************/
#define LIST_FOR_EACH_OBJECT(p_Pos, type, p_Head, member) \
for (p_Pos = LIST_OBJECT(NCSW_LIST_FIRST(p_Head), type, member); \
&p_Pos->member != (p_Head); \
p_Pos = LIST_OBJECT(NCSW_LIST_FIRST(&(p_Pos->member)), type, member))
/**************************************************************************//**
@Function LIST_Add
@Description Add a new entry to a list.
Insert a new entry after the specified head.
This is good for implementing stacks.
@Param[in] p_New - A pointer to a new list entry to be added.
@Param[in] p_Head - A pointer to a list head to add it after.
@Return none.
*//***************************************************************************/
static __inline__ void LIST_Add(t_List *p_New, t_List *p_Head)
{
NCSW_LIST_PREV(NCSW_LIST_NEXT(p_Head)) = p_New;
NCSW_LIST_NEXT(p_New) = NCSW_LIST_NEXT(p_Head);
NCSW_LIST_PREV(p_New) = p_Head;
NCSW_LIST_NEXT(p_Head) = p_New;
}
/**************************************************************************//**
@Function LIST_AddToTail
@Description Add a new entry to a list.
Insert a new entry before the specified head.
This is useful for implementing queues.
@Param[in] p_New - A pointer to a new list entry to be added.
@Param[in] p_Head - A pointer to a list head to add it after.
@Return none.
*//***************************************************************************/
static __inline__ void LIST_AddToTail(t_List *p_New, t_List *p_Head)
{
NCSW_LIST_NEXT(NCSW_LIST_PREV(p_Head)) = p_New;
NCSW_LIST_PREV(p_New) = NCSW_LIST_PREV(p_Head);
NCSW_LIST_NEXT(p_New) = p_Head;
NCSW_LIST_PREV(p_Head) = p_New;
}
/**************************************************************************//**
@Function LIST_Del
@Description Deletes entry from a list.
@Param[in] p_Entry - A pointer to the element to delete from the list.
@Return none.
@Cautions LIST_IsEmpty() on entry does not return true after this,
the entry is in an undefined state.
*//***************************************************************************/
static __inline__ void LIST_Del(t_List *p_Entry)
{
NCSW_LIST_PREV(NCSW_LIST_NEXT(p_Entry)) = NCSW_LIST_PREV(p_Entry);
NCSW_LIST_NEXT(NCSW_LIST_PREV(p_Entry)) = NCSW_LIST_NEXT(p_Entry);
}
/**************************************************************************//**
@Function LIST_DelAndInit
@Description Deletes entry from list and reinitialize it.
@Param[in] p_Entry - A pointer to the element to delete from the list.
@Return none.
*//***************************************************************************/
static __inline__ void LIST_DelAndInit(t_List *p_Entry)
{
LIST_Del(p_Entry);
INIT_LIST(p_Entry);
}
/**************************************************************************//**
@Function LIST_Move
@Description Delete from one list and add as another's head.
@Param[in] p_Entry - A pointer to the list entry to move.
@Param[in] p_Head - A pointer to the list head that will precede our entry.
@Return none.
*//***************************************************************************/
static __inline__ void LIST_Move(t_List *p_Entry, t_List *p_Head)
{
LIST_Del(p_Entry);
LIST_Add(p_Entry, p_Head);
}
/**************************************************************************//**
@Function LIST_MoveToTail
@Description Delete from one list and add as another's tail.
@Param[in] p_Entry - A pointer to the entry to move.
@Param[in] p_Head - A pointer to the list head that will follow our entry.
@Return none.
*//***************************************************************************/
static __inline__ void LIST_MoveToTail(t_List *p_Entry, t_List *p_Head)
{
LIST_Del(p_Entry);
LIST_AddToTail(p_Entry, p_Head);
}
/**************************************************************************//**
@Function LIST_IsEmpty
@Description Tests whether a list is empty.
@Param[in] p_List - A pointer to the list to test.
@Return 1 if the list is empty, 0 otherwise.
*//***************************************************************************/
static __inline__ int LIST_IsEmpty(t_List *p_List)
{
return (NCSW_LIST_FIRST(p_List) == p_List);
}
/**************************************************************************//**
@Function LIST_Append
@Description Join two lists.
@Param[in] p_NewList - A pointer to the new list to add.
@Param[in] p_Head - A pointer to the place to add it in the first list.
@Return none.
*//***************************************************************************/
void LIST_Append(t_List *p_NewList, t_List *p_Head);
/**************************************************************************//**
@Function LIST_NumOfObjs
@Description Counts number of objects in the list
@Param[in] p_List - A pointer to the list which objects are to be counted.
@Return Number of objects in the list.
*//***************************************************************************/
int LIST_NumOfObjs(t_List *p_List);
/** @} */ /* end of list_id group */
/** @} */ /* end of etc_id group */
#endif /* __LIST_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File mem_ext.h
@Description External prototypes for the memory manager object
*//***************************************************************************/
#ifndef __MEM_EXT_H
#define __MEM_EXT_H
#include "std_ext.h"
#include "part_ext.h"
/**************************************************************************//**
@Group etc_id Utility Library Application Programming Interface
@Description External routines.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group mem_id Slab Memory Manager
@Description Slab Memory Manager module functions, definitions and enums.
@{
*//***************************************************************************/
/* Each block is of the following structure:
*
*
* +-----------+----------+---------------------------+-----------+-----------+
* | Alignment | Prefix | Data | Postfix | Alignment |
* | field | field | field | field | Padding |
* | | | | | |
* +-----------+----------+---------------------------+-----------+-----------+
* and at the beginning of all bytes, an additional optional padding might reside
* to ensure that the first blocks data field is aligned as requested.
*/
#define MEM_MAX_NAME_LENGTH 8
/**************************************************************************//*
@Description Memory Segment structure
*//***************************************************************************/
typedef struct
{
char name[MEM_MAX_NAME_LENGTH];
/* The segment's name */
uint8_t **p_Bases; /* Base addresses of the segments */
uint8_t **p_BlocksStack; /* Array of pointers to blocks */
t_Handle h_Spinlock;
uint16_t dataSize; /* Size of each data block */
uint16_t prefixSize; /* How many bytes to reserve before the data */
uint16_t postfixSize; /* How many bytes to reserve after the data */
uint16_t alignment; /* Requested alignment for the data field */
int allocOwner; /* Memory allocation owner */
uint32_t getFailures; /* Number of times get failed */
uint32_t num; /* Number of blocks in segment */
uint32_t current; /* Current block */
bool consecutiveMem; /* Allocate consecutive data blocks memory */
#ifdef DEBUG_MEM_LEAKS
void *p_MemDbg; /* MEM debug database (MEM leaks detection) */
uint32_t blockOffset;
uint32_t blockSize;
#endif /* DEBUG_MEM_LEAKS */
} t_MemorySegment;
/**************************************************************************//**
@Function MEM_Init
@Description Create a new memory segment.
@Param[in] name - Name of memory partition.
@Param[in] p_Handle - Handle to new segment is returned through here.
@Param[in] num - Number of blocks in new segment.
@Param[in] dataSize - Size of blocks in segment.
@Param[in] prefixSize - How many bytes to allocate before the data.
@Param[in] postfixSize - How many bytes to allocate after the data.
@Param[in] alignment - Requested alignment for data field (in bytes).
@Return E_OK - success, E_NO_MEMORY - out of memory.
*//***************************************************************************/
t_Error MEM_Init(char name[],
t_Handle *p_Handle,
uint32_t num,
uint16_t dataSize,
uint16_t prefixSize,
uint16_t postfixSize,
uint16_t alignment);
/**************************************************************************//**
@Function MEM_InitSmart
@Description Create a new memory segment.
@Param[in] name - Name of memory partition.
@Param[in] p_Handle - Handle to new segment is returned through here.
@Param[in] num - Number of blocks in new segment.
@Param[in] dataSize - Size of blocks in segment.
@Param[in] prefixSize - How many bytes to allocate before the data.
@Param[in] postfixSize - How many bytes to allocate after the data.
@Param[in] alignment - Requested alignment for data field (in bytes).
@Param[in] memPartitionId - Memory partition ID for allocation.
@Param[in] consecutiveMem - Whether to allocate the memory blocks
continuously or not.
@Return E_OK - success, E_NO_MEMORY - out of memory.
*//***************************************************************************/
t_Error MEM_InitSmart(char name[],
t_Handle *p_Handle,
uint32_t num,
uint16_t dataSize,
uint16_t prefixSize,
uint16_t postfixSize,
uint16_t alignment,
uint8_t memPartitionId,
bool consecutiveMem);
/**************************************************************************//**
@Function MEM_InitByAddress
@Description Create a new memory segment with a specified base address.
@Param[in] name - Name of memory partition.
@Param[in] p_Handle - Handle to new segment is returned through here.
@Param[in] num - Number of blocks in new segment.
@Param[in] dataSize - Size of blocks in segment.
@Param[in] prefixSize - How many bytes to allocate before the data.
@Param[in] postfixSize - How many bytes to allocate after the data.
@Param[in] alignment - Requested alignment for data field (in bytes).
@Param[in] address - The required base address.
@Return E_OK - success, E_NO_MEMORY - out of memory.
*//***************************************************************************/
t_Error MEM_InitByAddress(char name[],
t_Handle *p_Handle,
uint32_t num,
uint16_t dataSize,
uint16_t prefixSize,
uint16_t postfixSize,
uint16_t alignment,
uint8_t *address);
/**************************************************************************//**
@Function MEM_Free
@Description Free a specific memory segment.
@Param[in] h_Mem - Handle to memory segment.
@Return None.
*//***************************************************************************/
void MEM_Free(t_Handle h_Mem);
/**************************************************************************//**
@Function MEM_Get
@Description Get a block of memory from a segment.
@Param[in] h_Mem - Handle to memory segment.
@Return Pointer to new memory block on success,0 otherwise.
*//***************************************************************************/
void * MEM_Get(t_Handle h_Mem);
/**************************************************************************//**
@Function MEM_GetN
@Description Get up to N blocks of memory from a segment.
The blocks are assumed to be of a fixed size (one size per segment).
@Param[in] h_Mem - Handle to memory segment.
@Param[in] num - Number of blocks to allocate.
@Param[out] array - Array of at least num pointers to which the addresses
of the allocated blocks are written.
@Return The number of blocks actually allocated.
@Cautions Interrupts are disabled for all of the allocation loop.
Although this loop is very short for each block (several machine
instructions), you should not allocate a very large number
of blocks via this routine.
*//***************************************************************************/
uint16_t MEM_GetN(t_Handle h_Mem, uint32_t num, void *array[]);
/**************************************************************************//**
@Function MEM_Put
@Description Put a block of memory back to a segment.
@Param[in] h_Mem - Handle to memory segment.
@Param[in] p_Block - The block to return.
@Return Pointer to new memory block on success,0 otherwise.
*//***************************************************************************/
t_Error MEM_Put(t_Handle h_Mem, void *p_Block);
/**************************************************************************//**
@Function MEM_ComputePartitionSize
@Description calculate a tight upper boundary of the size of a partition with
given attributes.
The returned value is suitable if one wants to use MEM_InitByAddress().
@Param[in] num - The number of blocks in the segment.
@Param[in] dataSize - Size of block to get.
@Param[in] prefixSize - The prefix size
@Param postfixSize - The postfix size
@Param[in] alignment - The requested alignment value (in bytes)
@Return The memory block size a segment with the given attributes needs.
*//***************************************************************************/
uint32_t MEM_ComputePartitionSize(uint32_t num,
uint16_t dataSize,
uint16_t prefixSize,
uint16_t postfixSize,
uint16_t alignment);
#ifdef DEBUG_MEM_LEAKS
#if !(defined(__MWERKS__) && (__dest_os == __ppc_eabi))
#error "Memory-Leaks-Debug option is supported only for freescale CodeWarrior"
#endif /* !(defined(__MWERKS__) && ... */
/**************************************************************************//**
@Function MEM_CheckLeaks
@Description Report MEM object leaks.
This routine is automatically called by the MEM_Free() routine,
but it can also be invoked while the MEM object is alive.
@Param[in] h_Mem - Handle to memory segment.
@Return None.
*//***************************************************************************/
void MEM_CheckLeaks(t_Handle h_Mem);
#else /* not DEBUG_MEM_LEAKS */
#define MEM_CheckLeaks(h_Mem)
#endif /* not DEBUG_MEM_LEAKS */
/**************************************************************************//**
@Description Get base of MEM
*//***************************************************************************/
#define MEM_GetBase(h_Mem) ((t_MemorySegment *)(h_Mem))->p_Bases[0]
/**************************************************************************//**
@Description Get size of MEM block
*//***************************************************************************/
#define MEM_GetSize(h_Mem) ((t_MemorySegment *)(h_Mem))->dataSize
/**************************************************************************//**
@Description Get prefix size of MEM block
*//***************************************************************************/
#define MEM_GetPrefixSize(h_Mem) ((t_MemorySegment *)(h_Mem))->prefixSize
/**************************************************************************//**
@Description Get postfix size of MEM block
*//***************************************************************************/
#define MEM_GetPostfixSize(h_Mem) ((t_MemorySegment *)(h_Mem))->postfixSize
/**************************************************************************//**
@Description Get alignment of MEM block (in bytes)
*//***************************************************************************/
#define MEM_GetAlignment(h_Mem) ((t_MemorySegment *)(h_Mem))->alignment
/**************************************************************************//**
@Description Get the number of blocks in the segment
*//***************************************************************************/
#define MEM_GetNumOfBlocks(h_Mem) ((t_MemorySegment *)(h_Mem))->num
/** @} */ /* end of MEM group */
/** @} */ /* end of etc_id group */
#endif /* __MEM_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File memcpy_ext.h
@Description Efficient functions for copying and setting blocks of memory.
*//***************************************************************************/
#ifndef __MEMCPY_EXT_H
#define __MEMCPY_EXT_H
#include "std_ext.h"
/**************************************************************************//**
@Group etc_id Utility Library Application Programming Interface
@Description External routines.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group mem_cpy Memory Copy
@Description Memory Copy module functions,definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function MemCpy32
@Description Copies one memory buffer into another one in 4-byte chunks!
Which should be more efficient than byte by byte.
For large buffers (over 60 bytes) this function is about 4 times
more efficient than the trivial memory copy. For short buffers
it is reduced to the trivial copy and may be a bit worse.
@Param[in] pDst - The address of the destination buffer.
@Param[in] pSrc - The address of the source buffer.
@Param[in] size - The number of bytes that will be copied from pSrc to pDst.
@Return pDst (the address of the destination buffer).
@Cautions There is no parameter or boundary checking! It is up to the user
to supply non-null parameters as source & destination and size
that actually fits into the destination buffer.
*//***************************************************************************/
void * MemCpy32(void* pDst,void* pSrc, uint32_t size);
void * IO2IOCpy32(void* pDst,void* pSrc, uint32_t size);
void * IO2MemCpy32(void* pDst,void* pSrc, uint32_t size);
void * Mem2IOCpy32(void* pDst,void* pSrc, uint32_t size);
/**************************************************************************//**
@Function MemCpy64
@Description Copies one memory buffer into another one in 8-byte chunks!
Which should be more efficient than byte by byte.
For large buffers (over 60 bytes) this function is about 8 times
more efficient than the trivial memory copy. For short buffers
it is reduced to the trivial copy and may be a bit worse.
Some testing suggests that MemCpy32() preforms better than
MemCpy64() over small buffers. On average they break even at
100 byte buffers. For buffers larger than that MemCpy64 is
superior.
@Param[in] pDst - The address of the destination buffer.
@Param[in] pSrc - The address of the source buffer.
@Param[in] size - The number of bytes that will be copied from pSrc to pDst.
@Return pDst (the address of the destination buffer).
@Cautions There is no parameter or boundary checking! It is up to the user
to supply non null parameters as source & destination and size
that actually fits into their buffer.
Do not use under Linux.
*//***************************************************************************/
void * MemCpy64(void* pDst,void* pSrc, uint32_t size);
/**************************************************************************//**
@Function MemSet32
@Description Sets all bytes of a memory buffer to a specific value, in
4-byte chunks.
@Param[in] pDst - The address of the destination buffer.
@Param[in] val - Value to set destination bytes to.
@Param[in] size - The number of bytes that will be set to val.
@Return pDst (the address of the destination buffer).
@Cautions There is no parameter or boundary checking! It is up to the user
to supply non null parameter as destination and size
that actually fits into the destination buffer.
*//***************************************************************************/
void * MemSet32(void* pDst, uint8_t val, uint32_t size);
void * IOMemSet32(void* pDst, uint8_t val, uint32_t size);
/**************************************************************************//**
@Function MemSet64
@Description Sets all bytes of a memory buffer to a specific value, in
8-byte chunks.
@Param[in] pDst - The address of the destination buffer.
@Param[in] val - Value to set destination bytes to.
@Param[in] size - The number of bytes that will be set to val.
@Return pDst (the address of the destination buffer).
@Cautions There is no parameter or boundary checking! It is up to the user
to supply non null parameter as destination and size
that actually fits into the destination buffer.
*//***************************************************************************/
void * MemSet64(void* pDst, uint8_t val, uint32_t size);
/**************************************************************************//**
@Function MemDisp
@Description Displays a block of memory in chunks of 32 bits.
@Param[in] addr - The address of the memory to display.
@Param[in] size - The number of bytes that will be displayed.
@Return None.
@Cautions There is no parameter or boundary checking! It is up to the user
to supply non null parameter as destination and size
that actually fits into the destination buffer.
*//***************************************************************************/
void MemDisp(uint8_t *addr, int size);
/** @} */ /* end of mem_cpy group */
/** @} */ /* end of etc_id group */
#endif /* __MEMCPY_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File mm_ext.h
@Description Memory Manager Application Programming Interface
*//***************************************************************************/
#ifndef __MM_EXT
#define __MM_EXT
#include "std_ext.h"
#define MM_MAX_ALIGNMENT 20 /* Alignments from 2 to 128 are available
where maximum alignment defined as
MM_MAX_ALIGNMENT power of 2 */
#define MM_MAX_NAME_LEN 32
/**************************************************************************//**
@Group etc_id Utility Library Application Programming Interface
@Description External routines.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group mm_grp Flexible Memory Manager
@Description Flexible Memory Manager module functions,definitions and enums.
(All of the following functions,definitions and enums can be found in mm_ext.h)
@{
*//***************************************************************************/
/**************************************************************************//**
@Function MM_Init
@Description Initializes a new MM object.
It initializes a new memory block consisting of base address
and size of the available memory by calling to MemBlock_Init
routine. It is also initializes a new free block for each
by calling FreeBlock_Init routine, which is pointed to
the almost all memory started from the required alignment
from the base address and to the end of the memory.
The handle to the new MM object is returned via "MM"
argument (passed by reference).
@Param[in] h_MM - Handle to the MM object.
@Param[in] base - Base address of the MM.
@Param[in] size - Size of the MM.
@Return E_OK is returned on success. E_NOMEMORY is returned if the new MM object or a new free block can not be initialized.
*//***************************************************************************/
t_Error MM_Init(t_Handle *h_MM, uint64_t base, uint64_t size);
/**************************************************************************//**
@Function MM_Get
@Description Allocates a block of memory according to the given size and the alignment.
The Alignment argument tells from which
free list allocate a block of memory. 2^alignment indicates
the alignment that the base address of the allocated block
should have. So, the only values 1, 2, 4, 8, 16, 32 and 64
are available for the alignment argument.
The routine passes through the specific free list of free
blocks and seeks for a first block that have anough memory
that is required (best fit).
After the block is found and data is allocated, it calls
the internal MM_CutFree routine to update all free lists
do not include a just allocated block. Of course, each
free list contains a free blocks with the same alignment.
It is also creates a busy block that holds
information about an allocated block.
@Param[in] h_MM - Handle to the MM object.
@Param[in] size - Size of the MM.
@Param[in] alignment - Index as a power of two defines a required
alignment (in bytes); Should be 1, 2, 4, 8, 16, 32 or 64
@Param[in] name - The name that specifies an allocated block.
@Return base address of an allocated block ILLEGAL_BASE if can't allocate a block
*//***************************************************************************/
uint64_t MM_Get(t_Handle h_MM, uint64_t size, uint64_t alignment, char *name);
/**************************************************************************//**
@Function MM_GetBase
@Description Gets the base address of the required MM objects.
@Param[in] h_MM - Handle to the MM object.
@Return base address of the block.
*//***************************************************************************/
uint64_t MM_GetBase(t_Handle h_MM);
/**************************************************************************//**
@Function MM_GetForce
@Description Force memory allocation.
It means to allocate a block of memory of the given
size from the given base address.
The routine checks if the required block can be allocated
(that is it is free) and then, calls the internal MM_CutFree
routine to update all free lists do not include that block.
@Param[in] h_MM - Handle to the MM object.
@Param[in] base - Base address of the MM.
@Param[in] size - Size of the MM.
@Param[in] name - Name that specifies an allocated block.
@Return base address of an allocated block, ILLEGAL_BASE if can't allocate a block.
*//***************************************************************************/
uint64_t MM_GetForce(t_Handle h_MM, uint64_t base, uint64_t size, char *name);
/**************************************************************************//**
@Function MM_GetForceMin
@Description Allocates a block of memory according to the given size, the alignment and minimum base address.
The Alignment argument tells from which
free list allocate a block of memory. 2^alignment indicates
the alignment that the base address of the allocated block
should have. So, the only values 1, 2, 4, 8, 16, 32 and 64
are available for the alignment argument.
The minimum baser address forces the location of the block
to be from a given address onward.
The routine passes through the specific free list of free
blocks and seeks for the first base address equal or smaller
than the required minimum address and end address larger than
than the required base + its size - i.e. that may contain
the required block.
After the block is found and data is allocated, it calls
the internal MM_CutFree routine to update all free lists
do not include a just allocated block. Of course, each
free list contains a free blocks with the same alignment.
It is also creates a busy block that holds
information about an allocated block.
@Param[in] h_MM - Handle to the MM object.
@Param[in] size - Size of the MM.
@Param[in] alignment - Index as a power of two defines a required
alignment (in bytes); Should be 1, 2, 4, 8, 16, 32 or 64
@Param[in] min - The minimum base address of the block.
@Param[in] name - Name that specifies an allocated block.
@Return base address of an allocated block,ILLEGAL_BASE if can't allocate a block.
*//***************************************************************************/
uint64_t MM_GetForceMin(t_Handle h_MM,
uint64_t size,
uint64_t alignment,
uint64_t min,
char *name);
/**************************************************************************//**
@Function MM_Put
@Description Puts a block of memory of the given base address back to the memory.
It checks if there is a busy block with the
given base address. If not, it returns 0, that
means can't free a block. Otherwise, it gets parameters of
the busy block and after it updates lists of free blocks,
removes that busy block from the list by calling to MM_CutBusy
routine.
After that it calls to MM_AddFree routine to add a new free
block to the free lists.
@Param[in] h_MM - Handle to the MM object.
@Param[in] base - Base address of the MM.
@Return The size of bytes released, 0 if failed.
*//***************************************************************************/
uint64_t MM_Put(t_Handle h_MM, uint64_t base);
/**************************************************************************//**
@Function MM_PutForce
@Description Releases a block of memory of the required size from the required base address.
First, it calls to MM_CutBusy routine
to cut a free block from the busy list. And then, calls to
MM_AddFree routine to add the free block to the free lists.
@Param[in] h_MM - Handle to the MM object.
@Param[in] base - Base address of of a block to free.
@Param[in] size - Size of a block to free.
@Return The number of bytes released, 0 on failure.
*//***************************************************************************/
uint64_t MM_PutForce(t_Handle h_MM, uint64_t base, uint64_t size);
/**************************************************************************//**
@Function MM_Add
@Description Adds a new memory block for memory allocation.
When a new memory block is initialized and added to the
memory list, it calls to MM_AddFree routine to add the
new free block to the free lists.
@Param[in] h_MM - Handle to the MM object.
@Param[in] base - Base address of the memory block.
@Param[in] size - Size of the memory block.
@Return E_OK on success, otherwise returns an error code.
*//***************************************************************************/
t_Error MM_Add(t_Handle h_MM, uint64_t base, uint64_t size);
/**************************************************************************//**
@Function MM_Dump
@Description Prints results of free and busy lists into the file.
@Param[in] h_MM - Handle to the MM object.
@Param[in] buff - A pointer to a buffer
*//***************************************************************************/
void MM_Dump(t_Handle h_MM, void *buff);
/**************************************************************************//**
@Function MM_Free
@Description Releases memory allocated for MM object.
@Param[in] h_MM - Handle of the MM object.
*//***************************************************************************/
void MM_Free(t_Handle h_MM);
/**************************************************************************//**
@Function MM_GetMemBlock
@Description Returns base address of the memory block specified by the index.
If index is 0, returns base address
of the first memory block, 1 - returns base address
of the second memory block, etc.
Note, those memory blocks are allocated by the
application before MM_Init or MM_Add and have to
be released by the application before or after invoking
the MM_Free routine.
@Param[in] h_MM - Handle to the MM object.
@Param[in] index - Index of the memory block.
@Return valid base address or ILLEGAL_BASE if no memory block specified by the index.
*//***************************************************************************/
uint64_t MM_GetMemBlock(t_Handle h_MM, int index);
/**************************************************************************//**
@Function MM_InRange
@Description Checks if a specific address is in the memory range of the passed MM object.
@Param[in] h_MM - Handle to the MM object.
@Param[in] addr - The address to be checked.
@Return TRUE if the address is in the address range of the block, FALSE otherwise.
*//***************************************************************************/
bool MM_InRange(t_Handle h_MM, uint64_t addr);
/** @} */ /* end of mm_grp group */
/** @} */ /* end of etc_id group */
#endif /* __MM_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/******************************************************************************
@File sprint_ext.h
@Description Debug routines (externals).
*//***************************************************************************/
#ifndef __SPRINT_EXT_H
#define __SPRINT_EXT_H
#if defined(NCSW_LINUX) && defined(__KERNEL__)
#include <linux/kernel.h>
#elif defined(NCSW_LINUX_USD)
#include <stdio.h>
#include "stdarg_ext.h"
#include "std_ext.h"
extern int vsscanf(const char *, const char *, va_list);
#elif defined(NCSW_VXWORKS)
#include "private/stdioP.h"
#elif defined(NCSW_FREEBSD)
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/libkern.h>
#else
#include <stdio.h>
#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */
#include "std_ext.h"
/**************************************************************************//**
@Group etc_id Utility Library Application Programming Interface
@Description External routines.
@{
*//***************************************************************************/
/**************************************************************************//**
@Group sprint_id Sprint
@Description Sprint & Sscan module functions,definitions and enums.
@{
*//***************************************************************************/
/**************************************************************************//**
@Function Sprint
@Description Format a string and place it in a buffer.
@Param[in] buff - The buffer to place the result into.
@Param[in] str - The format string to use.
@Param[in] ... - Arguments for the format string.
@Return Number of bytes formatted.
*//***************************************************************************/
int Sprint(char *buff, const char *str, ...);
/**************************************************************************//**
@Function Snprint
@Description Format a string and place it in a buffer.
@Param[in] buf - The buffer to place the result into.
@Param[in] size - The size of the buffer, including the trailing null space.
@Param[in] fmt - The format string to use.
@Param[in] ... - Arguments for the format string.
@Return Number of bytes formatted.
*//***************************************************************************/
int Snprint(char * buf, uint32_t size, const char *fmt, ...);
/**************************************************************************//**
@Function Sscan
@Description Unformat a buffer into a list of arguments.
@Param[in] buf - input buffer.
@Param[in] fmt - formatting of buffer.
@Param[out] ... - resulting arguments.
@Return Number of bytes unformatted.
*//***************************************************************************/
int Sscan(const char * buf, const char * fmt, ...);
/** @} */ /* end of sprint_id group */
/** @} */ /* end of etc_id group */
#endif /* __SPRINT_EXT_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************/
/**
@File dpaa_integration_ext.h
@Description P2041 FM external definitions and structures.
*//***************************************************************************/
#ifndef __DPAA_INTEGRATION_EXT_H
#define __DPAA_INTEGRATION_EXT_H
#include "std_ext.h"
/**************************************************************************//**
@Description DPAA SW Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_SWPORTAL0 = 0,
e_DPAA_SWPORTAL1,
e_DPAA_SWPORTAL2,
e_DPAA_SWPORTAL3,
e_DPAA_SWPORTAL4,
e_DPAA_SWPORTAL5,
e_DPAA_SWPORTAL6,
e_DPAA_SWPORTAL7,
e_DPAA_SWPORTAL8,
e_DPAA_SWPORTAL9,
e_DPAA_SWPORTAL_DUMMY_LAST
} e_DpaaSwPortal;
/**************************************************************************//**
@Description DPAA Direct Connect Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_DCPORTAL0 = 0,
e_DPAA_DCPORTAL1,
e_DPAA_DCPORTAL2,
e_DPAA_DCPORTAL3,
e_DPAA_DCPORTAL4,
e_DPAA_DCPORTAL_DUMMY_LAST
} e_DpaaDcPortal;
#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST
#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST
/*****************************************************************************
QMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */
#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */
#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */
#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE)
/**< FQIDs range - 24 bits */
/**************************************************************************//**
@Description Work Queue Channel assignments in QMan.
*//***************************************************************************/
typedef enum
{
e_QM_FQ_CHANNEL_SWPORTAL0 = 0, /**< Dedicated channels serviced by software portals 0 to 9 */
e_QM_FQ_CHANNEL_SWPORTAL1,
e_QM_FQ_CHANNEL_SWPORTAL2,
e_QM_FQ_CHANNEL_SWPORTAL3,
e_QM_FQ_CHANNEL_SWPORTAL4,
e_QM_FQ_CHANNEL_SWPORTAL5,
e_QM_FQ_CHANNEL_SWPORTAL6,
e_QM_FQ_CHANNEL_SWPORTAL7,
e_QM_FQ_CHANNEL_SWPORTAL8,
e_QM_FQ_CHANNEL_SWPORTAL9,
e_QM_FQ_CHANNEL_POOL1 = 0x21, /**< Pool channels that can be serviced by any of the software portals */
e_QM_FQ_CHANNEL_POOL2,
e_QM_FQ_CHANNEL_POOL3,
e_QM_FQ_CHANNEL_POOL4,
e_QM_FQ_CHANNEL_POOL5,
e_QM_FQ_CHANNEL_POOL6,
e_QM_FQ_CHANNEL_POOL7,
e_QM_FQ_CHANNEL_POOL8,
e_QM_FQ_CHANNEL_POOL9,
e_QM_FQ_CHANNEL_POOL10,
e_QM_FQ_CHANNEL_POOL11,
e_QM_FQ_CHANNEL_POOL12,
e_QM_FQ_CHANNEL_POOL13,
e_QM_FQ_CHANNEL_POOL14,
e_QM_FQ_CHANNEL_POOL15,
e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, /**< Dedicated channels serviced by Direct Connect Portal 0:
connected to FMan 0; assigned in incrementing order to
each sub-portal (SP) in the portal */
e_QM_FQ_CHANNEL_FMAN0_SP1,
e_QM_FQ_CHANNEL_FMAN0_SP2,
e_QM_FQ_CHANNEL_FMAN0_SP3,
e_QM_FQ_CHANNEL_FMAN0_SP4,
e_QM_FQ_CHANNEL_FMAN0_SP5,
e_QM_FQ_CHANNEL_FMAN0_SP6,
e_QM_FQ_CHANNEL_FMAN0_SP7,
e_QM_FQ_CHANNEL_FMAN0_SP8,
e_QM_FQ_CHANNEL_FMAN0_SP9,
e_QM_FQ_CHANNEL_FMAN0_SP10,
e_QM_FQ_CHANNEL_FMAN0_SP11,
e_QM_FQ_CHANNEL_RMAN_SP2 = 0x62, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */
e_QM_FQ_CHANNEL_RMAN_SP3,
e_QM_FQ_CHANNEL_CAAM = 0x80, /**< Dedicated channel serviced by Direct Connect Portal 2:
connected to SEC 4.x */
e_QM_FQ_CHANNEL_PME = 0xA0 /**< Dedicated channel serviced by Direct Connect Portal 3:
connected to PME */
} e_QmFQChannel;
/*****************************************************************************
BMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */
/*****************************************************************************
SEC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define SEC_NUM_OF_DECOS 2
#define SEC_ALL_DECOS_MASK 0x00000003
/*****************************************************************************
FM INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define INTG_MAX_NUM_OF_FM 1
/* Ports defines */
#define FM_MAX_NUM_OF_1G_MACS 5
#define FM_MAX_NUM_OF_10G_MACS 1
#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS)
#define FM_MAX_NUM_OF_OH_PORTS 7
#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS)
#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS)
#define FM_PORT_MAX_NUM_OF_EXT_POOLS 8 /**< Number of external BM pools per Rx port */
#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */
#define FM_MAX_NUM_OF_SUB_PORTALS 12
#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0
/* RAMs defines */
#define FM_MURAM_SIZE (160 * KILOBYTE)
#define FM_IRAM_SIZE ( 64 * KILOBYTE)
/* PCD defines */
#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */
#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */
#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */
/* RTC defines */
#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */
#define FM_RTC_NUM_OF_PERIODIC_PULSES 2 /**< RTC number of periodic pulses */
#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */
/* QMI defines */
#define QMI_MAX_NUM_OF_TNUMS 64
#define MAX_QMI_DEQ_SUBPORTAL 12
#define QMI_DEF_TNUMS_THRESH 48
/* FPM defines */
#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4
/* DMA defines */
#define DMA_THRESH_MAX_COMMQ 31
#define DMA_THRESH_MAX_BUF 127
/* BMI defines */
#define BMI_MAX_NUM_OF_TASKS 128
#define BMI_MAX_NUM_OF_DMAS 32
#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE)
#define PORT_MAX_WEIGHT 16 /**< Port weight in BMI arbitration register */
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmEventModules
{
e_FM_MOD_PRS, /**< Parser event */
e_FM_MOD_KG, /**< Keygen event */
e_FM_MOD_PLCR, /**< Policer event */
e_FM_MOD_10G_MAC, /**< 10G MAC error event */
e_FM_MOD_1G_MAC, /**< 1G MAC error event */
e_FM_MOD_TMR, /**< Timer event */
e_FM_MOD_1G_MAC_TMR, /**< 1G MAC timer event */
e_FM_MOD_FMAN_CTRL, /**< FMAN Controller timer event */
e_FM_MOD_DUMMY_LAST
} e_FmEventModules;
/**************************************************************************//**
@Description Enum for interrupts types
*//***************************************************************************/
typedef enum e_FmIntrType
{
e_FM_INTR_TYPE_ERR,
e_FM_INTR_TYPE_NORMAL
} e_FmIntrType;
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmInterModuleEvent
{
e_FM_EV_PRS, /**< Parser event */
e_FM_EV_ERR_PRS, /**< Parser error event */
e_FM_EV_KG, /**< Keygen event */
e_FM_EV_ERR_KG, /**< Keygen error event */
e_FM_EV_PLCR, /**< Policer event */
e_FM_EV_ERR_PLCR, /**< Policer error event */
e_FM_EV_ERR_10G_MAC0, /**< 10G MAC 0 error event */
e_FM_EV_ERR_1G_MAC0, /**< 1G MAC 0 error event */
e_FM_EV_ERR_1G_MAC1, /**< 1G MAC 1 error event */
e_FM_EV_ERR_1G_MAC2, /**< 1G MAC 2 error event */
e_FM_EV_ERR_1G_MAC3, /**< 1G MAC 3 error event */
e_FM_EV_ERR_1G_MAC4, /**< 1G MAC 4 error event */
e_FM_EV_TMR, /**< Timer event */
e_FM_EV_1G_MAC0_TMR, /**< 1G MAC 0 timer event */
e_FM_EV_1G_MAC1_TMR, /**< 1G MAC 1 timer event */
e_FM_EV_1G_MAC2_TMR, /**< 1G MAC 2 timer event */
e_FM_EV_1G_MAC3_TMR, /**< 1G MAC 3 timer event */
e_FM_EV_1G_MAC4_TMR, /**< 1G MAC 4 timer event */
e_FM_EV_FMAN_CTRL_0, /**< Fman controller event 0 */
e_FM_EV_FMAN_CTRL_1, /**< Fman controller event 1 */
e_FM_EV_FMAN_CTRL_2, /**< Fman controller event 2 */
e_FM_EV_FMAN_CTRL_3, /**< Fman controller event 3 */
e_FM_EV_DUMMY_LAST
} e_FmInterModuleEvent;
#define GET_FM_MODULE_EVENT(mod, id, intrType, event) \
switch(mod){ \
case e_FM_MOD_PRS: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \
break; \
case e_FM_MOD_KG: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_PLCR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \
break; \
case e_FM_MOD_10G_MAC: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_10G_MAC0 : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_1G_MAC: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC0 : e_FM_EV_DUMMY_LAST; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC1 : e_FM_EV_DUMMY_LAST; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC2 : e_FM_EV_DUMMY_LAST; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC3 : e_FM_EV_DUMMY_LAST; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC4 : e_FM_EV_DUMMY_LAST; break; \
} \
break; \
case e_FM_MOD_TMR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \
break; \
case e_FM_MOD_1G_MAC_TMR: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC0_TMR; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC1_TMR; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC2_TMR; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC3_TMR; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC4_TMR; break; \
} \
break; \
case e_FM_MOD_FMAN_CTRL: \
if (intrType == e_FM_INTR_TYPE_ERR) event = e_FM_EV_DUMMY_LAST; \
else switch(id){ \
case(0): event = e_FM_EV_FMAN_CTRL_0; break; \
case(1): event = e_FM_EV_FMAN_CTRL_1; break; \
case(2): event = e_FM_EV_FMAN_CTRL_2; break; \
case(3): event = e_FM_EV_FMAN_CTRL_3; break; \
} \
break; \
default: event = e_FM_EV_DUMMY_LAST; \
break;}
#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE
/* P2041 unique features */
#define FM_QMI_DEQ_OPTIONS_SUPPORT
#define FM_NO_DISPATCH_RAM_ECC
#define FM_FIFO_ALLOCATION_OLD_ALG
#define FM_NO_WATCHDOG
#define FM_NO_TNUM_AGING
#define FM_NO_TGEC_LOOPBACK
#define FM_KG_NO_BYPASS_FQID_GEN
#define FM_KG_NO_BYPASS_PLCR_PROFILE_GEN
#define FM_NO_BACKUP_POOLS
#define FM_NO_OP_OBSERVED_POOLS
#define FM_NO_ADVANCED_RATE_LIMITER
#define FM_NO_OP_OBSERVED_CGS
/* FM erratas */
#define FM_BAD_VLAN_DETECT_ERRATA_10GMAC_A010
#define FM_RX_PREAM_4_ERRATA_DTSEC_A001
#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */
#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173
#define FM_LEN_CHECK_ERRATA_FMAN_SW002
#define FM_PRS_MEM_ERRATA_FMAN_SW003
#endif /* __DPAA_INTEGRATION_EXT_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************/
/**
@File part_integration_ext.h
@Description P2041 external definitions and structures.
*//***************************************************************************/
#ifndef __PART_INTEGRATION_EXT_H
#define __PART_INTEGRATION_EXT_H
#include "std_ext.h"
#include "ddr_std_ext.h"
#include "enet_ext.h"
#include "dpaa_integration_ext.h"
/**************************************************************************//**
@Group P2041_chip_id P2041 Application Programming Interface
@Description P2041 Chip functions,definitions and enums.
@{
*//***************************************************************************/
#define CORE_E500MC
#define INTG_MAX_NUM_OF_CORES 4
/**************************************************************************//**
@Description Module types.
*//***************************************************************************/
typedef enum e_ModuleId
{
e_MODULE_ID_DUART_1 = 0,
e_MODULE_ID_DUART_2,
e_MODULE_ID_DUART_3,
e_MODULE_ID_DUART_4,
e_MODULE_ID_LAW,
e_MODULE_ID_LBC,
e_MODULE_ID_PAMU,
e_MODULE_ID_QM, /**< Queue manager module */
e_MODULE_ID_BM, /**< Buffer manager module */
e_MODULE_ID_QM_CE_PORTAL_0,
e_MODULE_ID_QM_CI_PORTAL_0,
e_MODULE_ID_QM_CE_PORTAL_1,
e_MODULE_ID_QM_CI_PORTAL_1,
e_MODULE_ID_QM_CE_PORTAL_2,
e_MODULE_ID_QM_CI_PORTAL_2,
e_MODULE_ID_QM_CE_PORTAL_3,
e_MODULE_ID_QM_CI_PORTAL_3,
e_MODULE_ID_QM_CE_PORTAL_4,
e_MODULE_ID_QM_CI_PORTAL_4,
e_MODULE_ID_QM_CE_PORTAL_5,
e_MODULE_ID_QM_CI_PORTAL_5,
e_MODULE_ID_QM_CE_PORTAL_6,
e_MODULE_ID_QM_CI_PORTAL_6,
e_MODULE_ID_QM_CE_PORTAL_7,
e_MODULE_ID_QM_CI_PORTAL_7,
e_MODULE_ID_QM_CE_PORTAL_8,
e_MODULE_ID_QM_CI_PORTAL_8,
e_MODULE_ID_QM_CE_PORTAL_9,
e_MODULE_ID_QM_CI_PORTAL_9,
e_MODULE_ID_BM_CE_PORTAL_0,
e_MODULE_ID_BM_CI_PORTAL_0,
e_MODULE_ID_BM_CE_PORTAL_1,
e_MODULE_ID_BM_CI_PORTAL_1,
e_MODULE_ID_BM_CE_PORTAL_2,
e_MODULE_ID_BM_CI_PORTAL_2,
e_MODULE_ID_BM_CE_PORTAL_3,
e_MODULE_ID_BM_CI_PORTAL_3,
e_MODULE_ID_BM_CE_PORTAL_4,
e_MODULE_ID_BM_CI_PORTAL_4,
e_MODULE_ID_BM_CE_PORTAL_5,
e_MODULE_ID_BM_CI_PORTAL_5,
e_MODULE_ID_BM_CE_PORTAL_6,
e_MODULE_ID_BM_CI_PORTAL_6,
e_MODULE_ID_BM_CE_PORTAL_7,
e_MODULE_ID_BM_CI_PORTAL_7,
e_MODULE_ID_BM_CE_PORTAL_8,
e_MODULE_ID_BM_CI_PORTAL_8,
e_MODULE_ID_BM_CE_PORTAL_9,
e_MODULE_ID_BM_CI_PORTAL_9,
e_MODULE_ID_FM, /**< Frame manager module */
e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */
e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */
e_MODULE_ID_FM_BMI, /**< FM BMI block */
e_MODULE_ID_FM_QMI, /**< FM QMI block */
e_MODULE_ID_FM_PARSER, /**< FM parser block */
e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_10GRx, /**< FM Rx 10G MAC port block */
e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_10GTx, /**< FM Tx 10G MAC port block */
e_MODULE_ID_FM_PLCR, /**< FM Policer */
e_MODULE_ID_FM_KG, /**< FM Keygen */
e_MODULE_ID_FM_DMA, /**< FM DMA */
e_MODULE_ID_FM_FPM, /**< FM FPM */
e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */
e_MODULE_ID_FM_1GMDIO1, /**< FM 1G MDIO MAC 1*/
e_MODULE_ID_FM_1GMDIO2, /**< FM 1G MDIO MAC 2*/
e_MODULE_ID_FM_1GMDIO3, /**< FM 1G MDIO MAC 3*/
e_MODULE_ID_FM_1GMDIO4, /**< FM 1G MDIO MAC 4*/
e_MODULE_ID_FM_1GMDIO5, /**< FM 1G MDIO MAC 5*/
e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */
e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */
e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */
e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */
e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */
e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */
e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */
e_MODULE_ID_FM_10GMAC, /**< FM 10G MAC */
e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */
e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */
e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */
e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */
e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */
e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */
e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */
e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */
e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */
e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */
e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */
e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */
e_MODULE_ID_PIC, /**< PIC */
e_MODULE_ID_GPIO, /**< GPIO */
e_MODULE_ID_SERDES, /**< SERDES */
e_MODULE_ID_CPC, /**< CoreNet-Platform-Cache */
e_MODULE_ID_DUMMY_LAST
} e_ModuleId;
#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST
/* Offsets relative to CCSR base */
#define P2041_OFFSET_LAW 0x00000c00
#define P2041_OFFSET_DDR 0x00008000
#define P2041_OFFSET_CPC 0x00010000
#define P2041_OFFSET_CCM 0x00018000
#define P2041_OFFSET_PAMU 0x00020000
#define P2041_OFFSET_PIC 0x00040000
#define P2041_OFFSET_GUTIL 0x000e0000
#define P2041_OFFSET_RCPM 0x000e2000
#define P2041_OFFSET_SERDES 0x000ea000
#define P2041_OFFSET_DMA1 0x00100100
#define P2041_OFFSET_DMA2 0x00101100
#define P2041_OFFSET_ESPI 0x00110000
#define P2041_OFFSET_ESDHC 0x00114000
#define P2041_OFFSET_I2C1 0x00118000
#define P2041_OFFSET_I2C2 0x00118100
#define P2041_OFFSET_I2C3 0x00119000
#define P2041_OFFSET_I2C4 0x00119100
#define P2041_OFFSET_DUART1 0x0011c500
#define P2041_OFFSET_DUART2 0x0011c600
#define P2041_OFFSET_DUART3 0x0011d500
#define P2041_OFFSET_DUART4 0x0011d600
#define P2041_OFFSET_LBC 0x00124000
#define P2041_OFFSET_GPIO 0x00130000
#define P2041_OFFSET_PCIE1 0x00200000
#define P2041_OFFSET_PCIE2 0x00201000
#define P2041_OFFSET_PCIE3 0x00202000
#define P2041_OFFSET_USB1 0x00210000
#define P2041_OFFSET_USB2 0x00211000
#define P2041_OFFSET_USB_PHY 0x00214000
#define P2041_OFFSET_SATA1 0x00220000
#define P2041_OFFSET_SATA2 0x00221000
#define P2041_OFFSET_SEC_GEN 0x00300000
#define P2041_OFFSET_SEC_JQ0 0x00301000
#define P2041_OFFSET_SEC_JQ1 0x00302000
#define P2041_OFFSET_SEC_JQ2 0x00303000
#define P2041_OFFSET_SEC_JQ3 0x00304000
#define P2041_OFFSET_SEC_RESERVED 0x00305000
#define P2041_OFFSET_SEC_RTIC 0x00306000
#define P2041_OFFSET_SEC_QI 0x00307000
#define P2041_OFFSET_SEC_DECO0_CCB0 0x00308000
#define P2041_OFFSET_SEC_DECO1_CCB1 0x00309000
#define P2041_OFFSET_PME 0x00316000
#define P2041_OFFSET_QM 0x00318000
#define P2041_OFFSET_BM 0x0031a000
#define P2041_OFFSET_FM 0x00400000
#define P2041_OFFSET_FM_MURAM P2041_OFFSET_FM
#define P2041_OFFSET_FM_BMI (P2041_OFFSET_FM + 0x00080000)
#define P2041_OFFSET_FM_QMI (P2041_OFFSET_FM + 0x00080400)
#define P2041_OFFSET_FM_PARSER (P2041_OFFSET_FM + 0x00080800)
#define P2041_OFFSET_FM_PORT_HO1 (P2041_OFFSET_FM + 0x00081000) /* host command/offline parser */
#define P2041_OFFSET_FM_PORT_HO2 (P2041_OFFSET_FM + 0x00082000)
#define P2041_OFFSET_FM_PORT_HO3 (P2041_OFFSET_FM + 0x00083000)
#define P2041_OFFSET_FM_PORT_HO4 (P2041_OFFSET_FM + 0x00084000)
#define P2041_OFFSET_FM_PORT_HO5 (P2041_OFFSET_FM + 0x00085000)
#define P2041_OFFSET_FM_PORT_HO6 (P2041_OFFSET_FM + 0x00086000)
#define P2041_OFFSET_FM_PORT_HO7 (P2041_OFFSET_FM + 0x00087000)
#define P2041_OFFSET_FM_PORT_1GRX1 (P2041_OFFSET_FM + 0x00088000)
#define P2041_OFFSET_FM_PORT_1GRX2 (P2041_OFFSET_FM + 0x00089000)
#define P2041_OFFSET_FM_PORT_1GRX3 (P2041_OFFSET_FM + 0x0008a000)
#define P2041_OFFSET_FM_PORT_1GRX4 (P2041_OFFSET_FM + 0x0008b000)
#define P2041_OFFSET_FM_PORT_1GRX5 (P2041_OFFSET_FM + 0x0008c000)
#define P2041_OFFSET_FM_PORT_10GRX (P2041_OFFSET_FM + 0x00090000)
#define P2041_OFFSET_FM_PORT_1GTX1 (P2041_OFFSET_FM + 0x000a8000)
#define P2041_OFFSET_FM_PORT_1GTX2 (P2041_OFFSET_FM + 0x000a9000)
#define P2041_OFFSET_FM_PORT_1GTX3 (P2041_OFFSET_FM + 0x000aa000)
#define P2041_OFFSET_FM_PORT_1GTX4 (P2041_OFFSET_FM + 0x000ab000)
#define P2041_OFFSET_FM_PORT_1GTX5 (P2041_OFFSET_FM + 0x000ac000)
#define P2041_OFFSET_FM_PORT_10GTX (P2041_OFFSET_FM + 0x000b0000)
#define P2041_OFFSET_FM_PLCR (P2041_OFFSET_FM + 0x000c0000)
#define P2041_OFFSET_FM_KG (P2041_OFFSET_FM + 0x000c1000)
#define P2041_OFFSET_FM_DMA (P2041_OFFSET_FM + 0x000c2000)
#define P2041_OFFSET_FM_FPM (P2041_OFFSET_FM + 0x000c3000)
#define P2041_OFFSET_FM_IRAM (P2041_OFFSET_FM + 0x000c4000)
#define P2041_OFFSET_FM_PARSER_IRAM (P2041_OFFSET_FM + 0x000c7000)
#define P2041_OFFSET_FM_1GMAC1 (P2041_OFFSET_FM + 0x000e0000)
#define P2041_OFFSET_FM_1GMDIO (P2041_OFFSET_FM + 0x000e1000 + 0x120)
#define P2041_OFFSET_FM_1GMAC2 (P2041_OFFSET_FM + 0x000e2000)
#define P2041_OFFSET_FM_1GMAC3 (P2041_OFFSET_FM + 0x000e4000)
#define P2041_OFFSET_FM_1GMAC4 (P2041_OFFSET_FM + 0x000e6000)
#define P2041_OFFSET_FM_1GMAC5 (P2041_OFFSET_FM + 0x000e8000)
#define P2041_OFFSET_FM_10GMAC (P2041_OFFSET_FM + 0x000f0000)
#define P2041_OFFSET_FM_10GMDIO (P2041_OFFSET_FM + 0x000f1000 + 0x030)
#define P2041_OFFSET_FM_RTC (P2041_OFFSET_FM + 0x000fe000)
/* Offsets relative to QM or BM portals base */
#define P2041_OFFSET_PORTALS_CE_AREA 0x000000 /* cache enabled area */
#define P2041_OFFSET_PORTALS_CI_AREA 0x100000 /* cache inhibited area */
#define P2041_CE_PORTAL_SIZE 0x4000
#define P2041_CI_PORTAL_SIZE 0x1000
#define P2041_OFFSET_PORTALS_CE(portal) \
(P2041_OFFSET_PORTALS_CE_AREA + P2041_CE_PORTAL_SIZE * (portal))
#define P2041_OFFSET_PORTALS_CI(portal) \
(P2041_OFFSET_PORTALS_CI_AREA + P2041_CI_PORTAL_SIZE * (portal))
/**************************************************************************//**
@Description Transaction source ID (for memory conrollers error reporting).
*//***************************************************************************/
typedef enum e_TransSrc
{
e_TRANS_SRC_PCIE_1 = 0x0, /**< PCI Express 1 */
e_TRANS_SRC_PCIE_2 = 0x1, /**< PCI Express 2 */
e_TRANS_SRC_PCIE_3 = 0x2, /**< PCI Express 3 */
e_TRANS_SRC_SRIO_1 = 0x8, /**< SRIO 1 */
e_TRANS_SRC_SRIO_2 = 0x9, /**< SRIO 2 */
e_TRANS_SRC_BMAN = 0x18, /**< BMan */
e_TRANS_SRC_PAMU = 0x1C, /**< PAMU */
e_TRANS_SRC_PME = 0x20, /**< PME */
e_TRANS_SRC_SEC = 0x21, /**< Security engine */
e_TRANS_SRC_QMAN = 0x3C, /**< QMan */
e_TRANS_SRC_USB_1 = 0x40, /**< USB 1 */
e_TRANS_SRC_USB_2 = 0x41, /**< USB 2 */
e_TRANS_SRC_ESDHC = 0x44, /**< eSDHC */
e_TRANS_SRC_PBL = 0x48, /**< Pre-boot loader */
e_TRANS_SRC_NPC = 0x4B, /**< Nexus port controller */
e_TRANS_SRC_RMAN = 0x5D, /**< RIO message manager */
e_TRANS_SRC_SATA_1 = 0x60, /**< SATA 1 */
e_TRANS_SRC_SATA_2 = 0x61, /**< SATA 2 */
e_TRANS_SRC_DMA_1 = 0x70, /**< DMA 1 */
e_TRANS_SRC_DMA_2 = 0x71, /**< DMA 2 */
e_TRANS_SRC_CORE_0_INST = 0x80, /**< Processor 0 (instruction) */
e_TRANS_SRC_CORE_0_DATA = 0x81, /**< Processor 0 (data) */
e_TRANS_SRC_CORE_1_INST = 0x82, /**< Processor 1 (instruction) */
e_TRANS_SRC_CORE_1_DATA = 0x83, /**< Processor 1 (data) */
e_TRANS_SRC_CORE_2_INST = 0x84, /**< Processor 2 (instruction) */
e_TRANS_SRC_CORE_2_DATA = 0x85, /**< Processor 2 (data) */
e_TRANS_SRC_CORE_3_INST = 0x86, /**< Processor 3 (instruction) */
e_TRANS_SRC_CORE_3_DATA = 0x87, /**< Processor 3 (data) */
e_TRANS_SRC_FM_10G = 0xC0, /**< FM XAUI */
e_TRANS_SRC_FM_HO_1 = 0xC1, /**< FM offline, host 1 */
e_TRANS_SRC_FM_HO_2 = 0xC2, /**< FM offline, host 2 */
e_TRANS_SRC_FM_HO_3 = 0xC3, /**< FM offline, host 3 */
e_TRANS_SRC_FM_HO_4 = 0xC4, /**< FM offline, host 4 */
e_TRANS_SRC_FM_HO_5 = 0xC5, /**< FM offline, host 5 */
e_TRANS_SRC_FM_HO_6 = 0xC6, /**< FM offline, host 6 */
e_TRANS_SRC_FM_HO_7 = 0xC7, /**< FM offline, host 7 */
e_TRANS_SRC_FM_GETH_1 = 0xC8, /**< FM GETH 1 */
e_TRANS_SRC_FM_GETH_2 = 0xC9, /**< FM GETH 2 */
e_TRANS_SRC_FM_GETH_3 = 0xCA, /**< FM GETH 3 */
e_TRANS_SRC_FM_GETH_4 = 0xCB, /**< FM GETH 4 */
e_TRANS_SRC_FM_GETH_5 = 0xCC /**< FM GETH 5 */
} e_TransSrc;
/**************************************************************************//**
@Description Local Access Window Target interface ID
*//***************************************************************************/
typedef enum e_P2041LawTargetId
{
e_P2041_LAW_TARGET_PCIE_1 = 0x0, /**< PCI Express 1 */
e_P2041_LAW_TARGET_PCIE_2 = 0x1, /**< PCI Express 2 */
e_P2041_LAW_TARGET_PCIE_3 = 0x2, /**< PCI Express 3 */
e_P2041_LAW_TARGET_SRIO_1 = 0x8, /**< SRIO 1 */
e_P2041_LAW_TARGET_SRIO_2 = 0x9, /**< SRIO 2 */
e_P2041_LAW_TARGET_DDR_CPC = 0x10, /**< DDR controller or CPC SRAM */
e_P2041_LAW_TARGET_BMAN = 0x18, /**< BMAN target interface ID */
e_P2041_LAW_TARGET_DCSR = 0x1D, /**< DCSR */
e_P2041_LAW_TARGET_LBC = 0x1F, /**< Local Bus target interface ID */
e_P2041_LAW_TARGET_QMAN = 0x3C, /**< QMAN target interface ID */
e_P2041_LAW_TARGET_NONE = 0xFF /**< None */
} e_P2041LawTargetId;
/***************************************************************
P2041 general routines
****************************************************************/
/**************************************************************************//**
@Group P2041_init_grp P2041 Initialization Unit
@Description P2041 initialization unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Part ID and revision number
*//***************************************************************************/
typedef enum e_P2041DeviceName
{
e_P2041_REV_INVALID = 0x00000000, /**< Invalid revision */
e_P2040_REV_1_0 = (int)0x82180010, /**< P2040 with security, revision 1.0 */
e_P2040_REV_1_0_NO_SEC = (int)0x82100010, /**< P2040 without security, revision 1.0 */
e_P2041_REV_1_0 = (int)0x82180110, /**< P2041 with security, revision 1.0 */
e_P2041_REV_1_0_NO_SEC = (int)0x82100110 /**< P2041 without security, revision 1.0 */
} e_P2041DeviceName;
/**************************************************************************//**
@Description Device Disable Register
*//***************************************************************************/
typedef enum e_P2041DeviceDisable
{
e_P2041_DEV_DISABLE_PCIE_1 = 0, /**< PCI Express controller 1 disable */
e_P2041_DEV_DISABLE_PCIE_2, /**< PCI Express controller 2 disable */
e_P2041_DEV_DISABLE_PCIE_3, /**< PCI Express controller 3 disable */
e_P2041_DEV_DISABLE_RMAN = 4, /**< RapidIO message manager disable */
e_P2041_DEV_DISABLE_SRIO_1, /**< Serial RapidIO controller 1 disable */
e_P2041_DEV_DISABLE_SRIO_2, /**< Serial RapidIO controller 2 disable */
e_P2041_DEV_DISABLE_DMA_1 = 9, /**< DMA controller 1 disable */
e_P2041_DEV_DISABLE_DMA_2, /**< DMA controller 2 disable */
e_P2041_DEV_DISABLE_DDR, /**< DDR controller disable */
e_P2041_DEV_DISABLE_SATA_1 = 17, /**< SATA controller 1 disable */
e_P2041_DEV_DISABLE_SATA_2, /**< SATA controller 2 disable */
e_P2041_DEV_DISABLE_LBC, /**< eLBC controller disable */
e_P2041_DEV_DISABLE_USB_1, /**< USB controller 1 disable */
e_P2041_DEV_DISABLE_USB_2, /**< USB controller 2 disable */
e_P2041_DEV_DISABLE_ESDHC = 23, /**< eSDHC controller disable */
e_P2041_DEV_DISABLE_GPIO, /**< GPIO controller disable */
e_P2041_DEV_DISABLE_ESPI, /**< eSPI controller disable */
e_P2041_DEV_DISABLE_I2C_1, /**< I2C module 1 (controllers 1 and 2) disable */
e_P2041_DEV_DISABLE_I2C_2, /**< I2C module 2 (controllers 3 and 4) disable */
e_P2041_DEV_DISABLE_DUART_1 = 30, /**< DUART controller 1 disable */
e_P2041_DEV_DISABLE_DUART_2, /**< DUART controller 2 disable */
e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST = 32,
/**< Dummy entry signing end of DEVDISR1 register controllers */
e_P2041_DEV_DISABLE_PME = e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST,
/**< Pattern match engine disable */
e_P2041_DEV_DISABLE_SEC, /**< Security disable */
e_P2041_DEV_DISABLE_QM_BM = e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST + 4,
/**< Queue manager/buffer manager disable */
e_P2041_DEV_DISABLE_FM = e_P2041_DEV_DISABLE_DISR1_DUMMY_LAST + 6,
/**< Frame manager disable */
e_P2041_DEV_DISABLE_10G, /**< 10G Ethernet controller disable */
e_P2041_DEV_DISABLE_DTSEC_1,
/**< dTSEC controller 1 disable */
e_P2041_DEV_DISABLE_DTSEC_2, /**< dTSEC controller 2 disable */
e_P2041_DEV_DISABLE_DTSEC_3, /**< dTSEC controller 3 disable */
e_P2041_DEV_DISABLE_DTSEC_4, /**< dTSEC controller 4 disable */
e_P2041_DEV_DISABLE_DTSEC_5 /**< dTSEC controller 5 disable */
} e_P2041DeviceDisable;
/**************************************************************************//*
@Description structure representing P2041 devices configuration
*//***************************************************************************/
typedef struct t_P2041Devices
{
struct
{
struct
{
bool enabled;
uint8_t serdesBank;
uint16_t serdesLane; /**< Most significant bits represent lanes used by this bank,
one bit for lane, lane A is the first and so on, e.g.,
set 0xF000 for ABCD lanes */
e_EnetInterface ethIf;
uint8_t ratio;
bool divByTwo;
bool isTwoHalfSgmii;
} dtsecs[FM_MAX_NUM_OF_1G_MACS];
struct
{
bool enabled;
uint8_t serdesBank;
uint16_t serdesLane;
} tgec;
} fm;
} t_P2041Devices;
/**************************************************************************//**
@Function P2041_GetRevInfo
@Description Obtain revision information.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return Part ID and revision.
*//***************************************************************************/
e_P2041DeviceName P2041_GetRevInfo(uintptr_t gutilBase);
/**************************************************************************//**
@Function P2041_GetE500Factor
@Description Obtain core's multiplication factors.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Param[in] coreIndex - Core index.
@Param[out] p_E500MulFactor - E500 to CCB multification factor.
@Param[out] p_E500DivFactor - E500 to CCB division factor.
*//***************************************************************************/
void P2041_GetE500Factor(uintptr_t gutilBase,
uint8_t coreIndex,
uint32_t *p_E500MulFactor,
uint32_t *p_E500DivFactor);
/**************************************************************************//**
@Function P2041_GetCcbFactor
@Description Obtain system multiplication factor.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return System multiplication factor.
*//***************************************************************************/
uint32_t P2041_GetCcbFactor(uintptr_t gutilBase);
/**************************************************************************//**
@Function P2041_GetDdrFactor
@Description Obtain DDR clock multiplication factor.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return DDR clock multiplication factor.
*//***************************************************************************/
uint32_t P2041_GetDdrFactor(uintptr_t gutilBase);
/**************************************************************************//**
@Function P2041_GetDdrType
@Description Obtain DDR memory type.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return DDR type.
*//***************************************************************************/
e_DdrType P2041_GetDdrType(uintptr_t gutilBase);
/**************************************************************************//**
@Function P2041_GetFmFactor
@Description returns FM multiplication factors. (This value is returned using
two parameters to avoid using float parameter).
@Param[in] gutilBase - Gutil memory map virtual base address.
@Param[out] p_FmMulFactor - FM to CCB multification factor.
@Param[out] p_FmDivFactor - FM to CCB division factor.
*//***************************************************************************/
void P2041_GetFmFactor(uintptr_t gutilBase,
uint32_t *p_FmMulFactor,
uint32_t *p_FmDivFactor);
void P2041_CoreTimeBaseEnable(uintptr_t rcpmBase);
void P2041_CoreTimeBaseDisable(uintptr_t rcpmBase);
typedef enum e_SerdesProtocol
{
SRDS_PROTOCOL_NONE = 0,
SRDS_PROTOCOL_PCIE1,
SRDS_PROTOCOL_PCIE2,
SRDS_PROTOCOL_PCIE3,
SRDS_PROTOCOL_SRIO1,
SRDS_PROTOCOL_SRIO2,
SRDS_PROTOCOL_SGMII_FM,
SRDS_PROTOCOL_XAUI_FM,
SRDS_PROTOCOL_SATA1,
SRDS_PROTOCOL_SATA2,
SRDS_PROTOCOL_AURORA
} e_SerdesProtocol;
t_Error P2041_DeviceDisable(uintptr_t gutilBase, e_P2041DeviceDisable device, bool disable);
void P2041_GetDevicesConfiguration(uintptr_t gutilBase, t_P2041Devices *p_Devices);
t_Error P2041_PamuDisableBypass(uintptr_t gutilBase, uint8_t pamuId, bool disable);
void P2041_SetDmaLiodn(uintptr_t gutilBase, uint8_t dmaId, uint16_t liodn);
uint32_t P2041_SerdesRcwGetProtocol(uintptr_t gutilBase);
bool P2041_SerdesRcwIsDeviceConfigured(uintptr_t gutilBase, e_SerdesProtocol device);
bool P2041_SerdesRcwIsLaneEnabled(uintptr_t gutilBase, uint32_t lane);
/** @} */ /* end of P2041_init_grp group */
/** @} */ /* end of P2041_grp group */
/*****************************************************************************
INTEGRATION-SPECIFIC MODULE CODES
******************************************************************************/
#define MODULE_UNKNOWN 0x00000000
#define MODULE_MEM 0x00010000
#define MODULE_MM 0x00020000
#define MODULE_CORE 0x00030000
#define MODULE_P2041 0x00040000
#define MODULE_P2041_PLATFORM 0x00050000
#define MODULE_PM 0x00060000
#define MODULE_MMU 0x00070000
#define MODULE_PIC 0x00080000
#define MODULE_CPC 0x00090000
#define MODULE_DUART 0x000a0000
#define MODULE_SERDES 0x000b0000
#define MODULE_PIO 0x000c0000
#define MODULE_QM 0x000d0000
#define MODULE_BM 0x000e0000
#define MODULE_SEC 0x000f0000
#define MODULE_LAW 0x00100000
#define MODULE_LBC 0x00110000
#define MODULE_PAMU 0x00120000
#define MODULE_FM 0x00130000
#define MODULE_FM_MURAM 0x00140000
#define MODULE_FM_PCD 0x00150000
#define MODULE_FM_RTC 0x00160000
#define MODULE_FM_MAC 0x00170000
#define MODULE_FM_PORT 0x00180000
#define MODULE_DPA_PORT 0x00190000
#define MODULE_MII 0x001a0000
#define MODULE_I2C 0x001b0000
#define MODULE_DMA 0x001c0000
#define MODULE_DDR 0x001d0000
#define MODULE_ESPI 0x001e0000
/*****************************************************************************
PAMU INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define PAMU_NUM_OF_PARTITIONS 4
/*****************************************************************************
LAW INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define LAW_NUM_OF_WINDOWS 32
#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */
#define LAW_MAX_WINDOW_SIZE 0x0000002000000000LL /**< 64GB */
/*****************************************************************************
LBC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
/**************************************************************************//**
@Group lbc_exception_grp LBC Exception Unit
@Description LBC Exception unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Anchor lbc_exbm
@Collection LBC Errors Bit Mask
These errors are reported through the exceptions callback..
The values can be or'ed in any combination in the errors mask
parameter of the errors report structure.
These errors can also be passed as a bit-mask to
LBC_EnableErrorChecking() or LBC_DisableErrorChecking(),
for enabling or disabling error checking.
@{
*//***************************************************************************/
#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */
#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */
#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */
#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */
#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \
LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT)
/**< All possible errors */
/* @} */
/** @} */ /* end of lbc_exception_grp group */
#define LBC_INCORRECT_ERROR_REPORT_ERRATA
#define LBC_NUM_OF_BANKS 4
#define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */
#define LBC_PARITY_SUPPORT
#define LBC_ADDRESS_HOLD_TIME_CTRL
#define LBC_HIGH_CLK_DIVIDERS
#define LBC_FCM_AVAILABLE
/*****************************************************************************
GPIO INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define GPIO_NUM_OF_PORTS 1 /**< Number of ports in GPIO module;
Each port contains up to 32 I/O pins. */
#define GPIO_VALID_PIN_MASKS \
{ /* Port A */ 0xFFFFFFFF }
#define GPIO_VALID_INTR_MASKS \
{ /* Port A */ 0xFFFFFFFF }
/*****************************************************************************
SERDES INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define SRDS_MAX_LANES 10 /* Lanes C - H on bank 1, lanes A - D on bank 2 */
#define SRDS_MAX_BANK 2
/* Serdes lanes general information provided in the following form:
1) Lane index in Serdes Control Registers Map
2) Lane enable/disable bit number in RCW
3) Lane bank index */
#define SRDS_LANES \
{ \
{ 2, 154, 0 }, \
{ 3, 155, 0 }, \
{ 4, 156, 0 }, \
{ 5, 157, 0 }, \
{ 6, 158, 0 }, \
{ 7, 159, 0 }, \
{ 16, 162, 1 }, \
{ 17, 163, 1 }, \
{ 18, 164, 1 }, \
{ 19, 165, 1 } \
}
#define SRDS_PROTOCOL_OPTIONS \
/* Protocol Lane assignment */ \
{ \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x02 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x05 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x08 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x09 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x0A */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x0F */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x14 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x16 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x17 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x19 */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x1A */ {SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
/* 0x1C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_SGMII_FM, 0, 0} \
}
/*****************************************************************************
DDR INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define DDR_NUM_OF_VALID_CS 4
/*****************************************************************************
DMA INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define DMA_NUM_OF_CONTROLLERS 2
/*****************************************************************************
CPC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define CPC_MAX_SIZE_SRAM_ERRATA_CPC4
#define CPC_HARDWARE_FLUSH_ERRATA_CPC10
#endif /* __PART_INTEGRATION_EXT_H */

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sys/contrib/ncsw/inc/integrations/P3041/dpaa_integration_ext.h Normal file
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@ -0,0 +1,371 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************/
/**
@File dpaa_integration_ext.h
@Description P3041 FM external definitions and structures.
*//***************************************************************************/
#ifndef __DPAA_INTEGRATION_EXT_H
#define __DPAA_INTEGRATION_EXT_H
#include "std_ext.h"
/**************************************************************************//**
@Description DPAA SW Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_SWPORTAL0 = 0,
e_DPAA_SWPORTAL1,
e_DPAA_SWPORTAL2,
e_DPAA_SWPORTAL3,
e_DPAA_SWPORTAL4,
e_DPAA_SWPORTAL5,
e_DPAA_SWPORTAL6,
e_DPAA_SWPORTAL7,
e_DPAA_SWPORTAL8,
e_DPAA_SWPORTAL9,
e_DPAA_SWPORTAL_DUMMY_LAST
} e_DpaaSwPortal;
/**************************************************************************//**
@Description DPAA Direct Connect Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_DCPORTAL0 = 0,
e_DPAA_DCPORTAL1,
e_DPAA_DCPORTAL2,
e_DPAA_DCPORTAL3,
e_DPAA_DCPORTAL4,
e_DPAA_DCPORTAL_DUMMY_LAST
} e_DpaaDcPortal;
#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST
#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST
/*****************************************************************************
QMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */
#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */
#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */
#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE)
/**< FQIDs range - 24 bits */
/**************************************************************************//**
@Description Work Queue Channel assignments in QMan.
*//***************************************************************************/
typedef enum
{
e_QM_FQ_CHANNEL_SWPORTAL0 = 0, /**< Dedicated channels serviced by software portals 0 to 9 */
e_QM_FQ_CHANNEL_SWPORTAL1,
e_QM_FQ_CHANNEL_SWPORTAL2,
e_QM_FQ_CHANNEL_SWPORTAL3,
e_QM_FQ_CHANNEL_SWPORTAL4,
e_QM_FQ_CHANNEL_SWPORTAL5,
e_QM_FQ_CHANNEL_SWPORTAL6,
e_QM_FQ_CHANNEL_SWPORTAL7,
e_QM_FQ_CHANNEL_SWPORTAL8,
e_QM_FQ_CHANNEL_SWPORTAL9,
e_QM_FQ_CHANNEL_POOL1 = 0x21, /**< Pool channels that can be serviced by any of the software portals */
e_QM_FQ_CHANNEL_POOL2,
e_QM_FQ_CHANNEL_POOL3,
e_QM_FQ_CHANNEL_POOL4,
e_QM_FQ_CHANNEL_POOL5,
e_QM_FQ_CHANNEL_POOL6,
e_QM_FQ_CHANNEL_POOL7,
e_QM_FQ_CHANNEL_POOL8,
e_QM_FQ_CHANNEL_POOL9,
e_QM_FQ_CHANNEL_POOL10,
e_QM_FQ_CHANNEL_POOL11,
e_QM_FQ_CHANNEL_POOL12,
e_QM_FQ_CHANNEL_POOL13,
e_QM_FQ_CHANNEL_POOL14,
e_QM_FQ_CHANNEL_POOL15,
e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, /**< Dedicated channels serviced by Direct Connect Portal 0:
connected to FMan 0; assigned in incrementing order to
each sub-portal (SP) in the portal */
e_QM_FQ_CHANNEL_FMAN0_SP1,
e_QM_FQ_CHANNEL_FMAN0_SP2,
e_QM_FQ_CHANNEL_FMAN0_SP3,
e_QM_FQ_CHANNEL_FMAN0_SP4,
e_QM_FQ_CHANNEL_FMAN0_SP5,
e_QM_FQ_CHANNEL_FMAN0_SP6,
e_QM_FQ_CHANNEL_FMAN0_SP7,
e_QM_FQ_CHANNEL_FMAN0_SP8,
e_QM_FQ_CHANNEL_FMAN0_SP9,
e_QM_FQ_CHANNEL_FMAN0_SP10,
e_QM_FQ_CHANNEL_FMAN0_SP11,
e_QM_FQ_CHANNEL_RMAN_SP2 = 0x62, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */
e_QM_FQ_CHANNEL_RMAN_SP3,
e_QM_FQ_CHANNEL_CAAM = 0x80, /**< Dedicated channel serviced by Direct Connect Portal 2:
connected to SEC 4.x */
e_QM_FQ_CHANNEL_PME = 0xA0 /**< Dedicated channel serviced by Direct Connect Portal 3:
connected to PME */
} e_QmFQChannel;
/*****************************************************************************
BMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */
/*****************************************************************************
FM INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define INTG_MAX_NUM_OF_FM 1
/* Ports defines */
#define FM_MAX_NUM_OF_1G_MACS 5
#define FM_MAX_NUM_OF_10G_MACS 1
#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS)
#define FM_MAX_NUM_OF_OH_PORTS 7
#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS)
#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS)
#define FM_PORT_MAX_NUM_OF_EXT_POOLS 8 /**< Number of external BM pools per Rx port */
#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */
#define FM_MAX_NUM_OF_SUB_PORTALS 12
#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0
/* RAMs defines */
#define FM_MURAM_SIZE (160 * KILOBYTE)
#define FM_IRAM_SIZE ( 64 * KILOBYTE)
/* PCD defines */
#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */
#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */
#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */
/* RTC defines */
#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */
#define FM_RTC_NUM_OF_PERIODIC_PULSES 2 /**< RTC number of periodic pulses */
#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */
/* QMI defines */
#define QMI_MAX_NUM_OF_TNUMS 64
#define MAX_QMI_DEQ_SUBPORTAL 12
#define QMI_DEF_TNUMS_THRESH 48
/* FPM defines */
#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4
/* DMA defines */
#define DMA_THRESH_MAX_COMMQ 31
#define DMA_THRESH_MAX_BUF 127
/* BMI defines */
#define BMI_MAX_NUM_OF_TASKS 128
#define BMI_MAX_NUM_OF_DMAS 32
#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE)
#define PORT_MAX_WEIGHT 16
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmEventModules
{
e_FM_MOD_PRS, /**< Parser event */
e_FM_MOD_KG, /**< Keygen event */
e_FM_MOD_PLCR, /**< Policer event */
e_FM_MOD_10G_MAC, /**< 10G MAC error event */
e_FM_MOD_1G_MAC, /**< 1G MAC error event */
e_FM_MOD_TMR, /**< Timer event */
e_FM_MOD_1G_MAC_TMR, /**< 1G MAC timer event */
e_FM_MOD_FMAN_CTRL, /**< FMAN Controller timer event */
e_FM_MOD_DUMMY_LAST
} e_FmEventModules;
/**************************************************************************//**
@Description Enum for interrupts types
*//***************************************************************************/
typedef enum e_FmIntrType
{
e_FM_INTR_TYPE_ERR,
e_FM_INTR_TYPE_NORMAL
} e_FmIntrType;
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmInterModuleEvent
{
e_FM_EV_PRS, /**< Parser event */
e_FM_EV_ERR_PRS, /**< Parser error event */
e_FM_EV_KG, /**< Keygen event */
e_FM_EV_ERR_KG, /**< Keygen error event */
e_FM_EV_PLCR, /**< Policer event */
e_FM_EV_ERR_PLCR, /**< Policer error event */
e_FM_EV_ERR_10G_MAC0, /**< 10G MAC 0 error event */
e_FM_EV_ERR_1G_MAC0, /**< 1G MAC 0 error event */
e_FM_EV_ERR_1G_MAC1, /**< 1G MAC 1 error event */
e_FM_EV_ERR_1G_MAC2, /**< 1G MAC 2 error event */
e_FM_EV_ERR_1G_MAC3, /**< 1G MAC 3 error event */
e_FM_EV_ERR_1G_MAC4, /**< 1G MAC 4 error event */
e_FM_EV_TMR, /**< Timer event */
e_FM_EV_1G_MAC0_TMR, /**< 1G MAC 0 timer event */
e_FM_EV_1G_MAC1_TMR, /**< 1G MAC 1 timer event */
e_FM_EV_1G_MAC2_TMR, /**< 1G MAC 2 timer event */
e_FM_EV_1G_MAC3_TMR, /**< 1G MAC 3 timer event */
e_FM_EV_1G_MAC4_TMR, /**< 1G MAC 4 timer event */
e_FM_EV_FMAN_CTRL_0, /**< Fman controller event 0 */
e_FM_EV_FMAN_CTRL_1, /**< Fman controller event 1 */
e_FM_EV_FMAN_CTRL_2, /**< Fman controller event 2 */
e_FM_EV_FMAN_CTRL_3, /**< Fman controller event 3 */
e_FM_EV_DUMMY_LAST
} e_FmInterModuleEvent;
#define GET_FM_MODULE_EVENT(mod, id, intrType, event) \
switch(mod){ \
case e_FM_MOD_PRS: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \
break; \
case e_FM_MOD_KG: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_PLCR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \
break; \
case e_FM_MOD_10G_MAC: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_10G_MAC0 : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_1G_MAC: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC0 : e_FM_EV_DUMMY_LAST; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC1 : e_FM_EV_DUMMY_LAST; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC2 : e_FM_EV_DUMMY_LAST; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC3 : e_FM_EV_DUMMY_LAST; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC4 : e_FM_EV_DUMMY_LAST; break; \
} \
break; \
case e_FM_MOD_TMR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \
break; \
case e_FM_MOD_1G_MAC_TMR: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC0_TMR; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC1_TMR; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC2_TMR; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC3_TMR; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC4_TMR; break; \
} \
break; \
case e_FM_MOD_FMAN_CTRL: \
if (intrType == e_FM_INTR_TYPE_ERR) event = e_FM_EV_DUMMY_LAST; \
else switch(id){ \
case(0): event = e_FM_EV_FMAN_CTRL_0; break; \
case(1): event = e_FM_EV_FMAN_CTRL_1; break; \
case(2): event = e_FM_EV_FMAN_CTRL_2; break; \
case(3): event = e_FM_EV_FMAN_CTRL_3; break; \
} \
break; \
default: event = e_FM_EV_DUMMY_LAST; \
break;}
#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE
/* P3041 unique features */
#define FM_QMI_DEQ_OPTIONS_SUPPORT
#define FM_NO_DISPATCH_RAM_ECC
#define FM_FIFO_ALLOCATION_OLD_ALG
#define FM_NO_WATCHDOG
#define FM_NO_TNUM_AGING
#define FM_NO_TGEC_LOOPBACK
#define FM_KG_NO_BYPASS_FQID_GEN
#define FM_KG_NO_BYPASS_PLCR_PROFILE_GEN
#define FM_NO_BACKUP_POOLS
#define FM_NO_OP_OBSERVED_POOLS
#define FM_NO_ADVANCED_RATE_LIMITER
#define FM_NO_OP_OBSERVED_CGS
/* FM erratas */
#define FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
#define FM_TX_SHORT_FRAME_BAD_TS_ERRATA_10GMAC_A006 /* No implementation, Out of LLD scope */
#define FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007
#define FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008
#define FM_NO_RX_PREAM_ERRATA_DTSECx1
#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 FM_NO_RX_PREAM_ERRATA_DTSECx1
#define FM_GRS_ERRATA_DTSEC_A002
#define FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003
#define FM_GTS_ERRATA_DTSEC_A004
#define FM_PAUSE_BLOCK_ERRATA_DTSEC_A006 /* do nothing */
#define FM_RESERVED_ACCESS_TO_DISABLED_DEV_ERRATA_DTSEC_A0011 /* do nothing */
#define FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012 FM_GTS_ERRATA_DTSEC_A004
#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */
#define FM_10_100_SGMII_NO_TS_ERRATA_DTSEC3
#define FM_TX_LOCKUP_ERRATA_DTSEC6
#define FM_IM_TX_SYNC_SKIP_TNUM_ERRATA_FMAN_A001 /* Implemented by ucode */
#define FM_HC_DEF_FQID_ONLY_ERRATA_FMAN_A003 /* Implemented by ucode */
#define FM_IM_TX_SHARED_TNUM_ERRATA_FMAN4 /* Implemented by ucode */
#define FM_IM_GS_DEADLOCK_ERRATA_FMAN5 /* Implemented by ucode */
#define FM_IM_DEQ_PIPELINE_DEPTH_ERRATA_FMAN10 /* Implemented by ucode */
#define FM_CC_GEN6_MISSMATCH_ERRATA_FMAN12 /* Implemented by ucode */
#define FM_CC_CHANGE_SHARED_TNUM_ERRATA_FMAN13 /* Implemented by ucode */
#define FM_IM_LARGE_MRBLR_ERRATA_FMAN15 /* Implemented by ucode */
#define FM_BMI_TO_RISC_ENQ_ERRATA_FMANc /* No implementation, Out of LLD scope */
#define FM_INVALID_SWPRS_DATA_ERRATA_FMANd
/* #define FM_PRS_MPLS_SSA_ERRATA_FMANj */ /* No implementation, No patch yet */
/* #define FM_PRS_INITIAL_PLANID_ERRATA_FMANk */ /* No implementation, No patch yet */
#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173
#define FM_NO_COPY_CTXA_CTXB_ERRATA_FMAN_SW001
#define FM_PRS_MEM_ERRATA_FMAN_SW003
#define FM_LEN_CHECK_ERRATA_FMAN_SW002
#define FM_10G_REM_N_LCL_FLT_EX_ERRATA_10GMAC001
#endif /* __DPAA_INTEGRATION_EXT_H */

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/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************/
/**
@File part_integration_ext.h
@Description P3041 external definitions and structures.
*//***************************************************************************/
#ifndef __PART_INTEGRATION_EXT_H
#define __PART_INTEGRATION_EXT_H
#include "std_ext.h"
#include "ddr_std_ext.h"
#include "enet_ext.h"
#include "dpaa_integration_ext.h"
/**************************************************************************//**
@Group P3041_chip_id P3041 Application Programming Interface
@Description P3041 Chip functions,definitions and enums.
@{
*//***************************************************************************/
#define CORE_E500MC
#define INTG_MAX_NUM_OF_CORES 4
/**************************************************************************//**
@Description Module types.
*//***************************************************************************/
typedef enum e_ModuleId
{
e_MODULE_ID_DUART_1 = 0,
e_MODULE_ID_DUART_2,
e_MODULE_ID_DUART_3,
e_MODULE_ID_DUART_4,
e_MODULE_ID_LAW,
e_MODULE_ID_LBC,
e_MODULE_ID_PAMU,
e_MODULE_ID_QM, /**< Queue manager module */
e_MODULE_ID_BM, /**< Buffer manager module */
e_MODULE_ID_QM_CE_PORTAL_0,
e_MODULE_ID_QM_CI_PORTAL_0,
e_MODULE_ID_QM_CE_PORTAL_1,
e_MODULE_ID_QM_CI_PORTAL_1,
e_MODULE_ID_QM_CE_PORTAL_2,
e_MODULE_ID_QM_CI_PORTAL_2,
e_MODULE_ID_QM_CE_PORTAL_3,
e_MODULE_ID_QM_CI_PORTAL_3,
e_MODULE_ID_QM_CE_PORTAL_4,
e_MODULE_ID_QM_CI_PORTAL_4,
e_MODULE_ID_QM_CE_PORTAL_5,
e_MODULE_ID_QM_CI_PORTAL_5,
e_MODULE_ID_QM_CE_PORTAL_6,
e_MODULE_ID_QM_CI_PORTAL_6,
e_MODULE_ID_QM_CE_PORTAL_7,
e_MODULE_ID_QM_CI_PORTAL_7,
e_MODULE_ID_QM_CE_PORTAL_8,
e_MODULE_ID_QM_CI_PORTAL_8,
e_MODULE_ID_QM_CE_PORTAL_9,
e_MODULE_ID_QM_CI_PORTAL_9,
e_MODULE_ID_BM_CE_PORTAL_0,
e_MODULE_ID_BM_CI_PORTAL_0,
e_MODULE_ID_BM_CE_PORTAL_1,
e_MODULE_ID_BM_CI_PORTAL_1,
e_MODULE_ID_BM_CE_PORTAL_2,
e_MODULE_ID_BM_CI_PORTAL_2,
e_MODULE_ID_BM_CE_PORTAL_3,
e_MODULE_ID_BM_CI_PORTAL_3,
e_MODULE_ID_BM_CE_PORTAL_4,
e_MODULE_ID_BM_CI_PORTAL_4,
e_MODULE_ID_BM_CE_PORTAL_5,
e_MODULE_ID_BM_CI_PORTAL_5,
e_MODULE_ID_BM_CE_PORTAL_6,
e_MODULE_ID_BM_CI_PORTAL_6,
e_MODULE_ID_BM_CE_PORTAL_7,
e_MODULE_ID_BM_CI_PORTAL_7,
e_MODULE_ID_BM_CE_PORTAL_8,
e_MODULE_ID_BM_CI_PORTAL_8,
e_MODULE_ID_BM_CE_PORTAL_9,
e_MODULE_ID_BM_CI_PORTAL_9,
e_MODULE_ID_FM, /**< Frame manager module */
e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */
e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */
e_MODULE_ID_FM_BMI, /**< FM BMI block */
e_MODULE_ID_FM_QMI, /**< FM QMI block */
e_MODULE_ID_FM_PARSER, /**< FM parser block */
e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */
e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */
e_MODULE_ID_FM_PORT_10GRx, /**< FM Rx 10G MAC port block */
e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */
e_MODULE_ID_FM_PORT_10GTx, /**< FM Tx 10G MAC port block */
e_MODULE_ID_FM_PLCR, /**< FM Policer */
e_MODULE_ID_FM_KG, /**< FM Keygen */
e_MODULE_ID_FM_DMA, /**< FM DMA */
e_MODULE_ID_FM_FPM, /**< FM FPM */
e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */
e_MODULE_ID_FM_1GMDIO1, /**< FM 1G MDIO MAC 1*/
e_MODULE_ID_FM_1GMDIO2, /**< FM 1G MDIO MAC 2*/
e_MODULE_ID_FM_1GMDIO3, /**< FM 1G MDIO MAC 3*/
e_MODULE_ID_FM_1GMDIO4, /**< FM 1G MDIO MAC 4*/
e_MODULE_ID_FM_1GMDIO5, /**< FM 1G MDIO MAC 5*/
e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */
e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */
e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */
e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */
e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */
e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */
e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */
e_MODULE_ID_FM_10GMAC, /**< FM 10G MAC */
e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */
e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */
e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */
e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */
e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */
e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */
e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */
e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */
e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */
e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */
e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */
e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */
e_MODULE_ID_PIC, /**< PIC */
e_MODULE_ID_GPIO, /**< GPIO */
e_MODULE_ID_SERDES, /**< SERDES */
e_MODULE_ID_CPC, /**< CoreNet-Platform-Cache */
e_MODULE_ID_DUMMY_LAST
} e_ModuleId;
#define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST
/* Offsets relative to CCSR base */
#define P3041_OFFSET_LAW 0x00000c00
#define P3041_OFFSET_DDR 0x00008000
#define P3041_OFFSET_CPC 0x00010000
#define P3041_OFFSET_CCM 0x00018000
#define P3041_OFFSET_PAMU 0x00020000
#define P3041_OFFSET_PIC 0x00040000
#define P3041_OFFSET_GUTIL 0x000e0000
#define P3041_OFFSET_RCPM 0x000e2000
#define P3041_OFFSET_SERDES 0x000ea000
#define P3041_OFFSET_DMA1 0x00100100
#define P3041_OFFSET_DMA2 0x00101100
#define P3041_OFFSET_ESPI 0x00110000
#define P3041_OFFSET_ESDHC 0x00114000
#define P3041_OFFSET_I2C1 0x00118000
#define P3041_OFFSET_I2C2 0x00118100
#define P3041_OFFSET_I2C3 0x00119000
#define P3041_OFFSET_I2C4 0x00119100
#define P3041_OFFSET_DUART1 0x0011c500
#define P3041_OFFSET_DUART2 0x0011c600
#define P3041_OFFSET_DUART3 0x0011d500
#define P3041_OFFSET_DUART4 0x0011d600
#define P3041_OFFSET_LBC 0x00124000
#define P3041_OFFSET_GPIO 0x00130000
#define P3041_OFFSET_PCIE1 0x00200000
#define P3041_OFFSET_PCIE2 0x00201000
#define P3041_OFFSET_PCIE3 0x00202000
#define P3041_OFFSET_PCIE4 0x00203000
#define P3041_OFFSET_USB1 0x00210000
#define P3041_OFFSET_USB2 0x00211000
#define P3041_OFFSET_USB_PHY 0x00214000
#define P3041_OFFSET_SATA1 0x00220000
#define P3041_OFFSET_SATA2 0x00221000
#define P3041_OFFSET_SEC_GEN 0x00300000
#define P3041_OFFSET_SEC_JQ0 0x00301000
#define P3041_OFFSET_SEC_JQ1 0x00302000
#define P3041_OFFSET_SEC_JQ2 0x00303000
#define P3041_OFFSET_SEC_JQ3 0x00304000
#define P3041_OFFSET_SEC_RESERVED 0x00305000
#define P3041_OFFSET_SEC_RTIC 0x00306000
#define P3041_OFFSET_SEC_QI 0x00307000
#define P3041_OFFSET_SEC_DECO0_CCB0 0x00308000
#define P3041_OFFSET_SEC_DECO1_CCB1 0x00309000
#define P3041_OFFSET_PME 0x00316000
#define P3041_OFFSET_QM 0x00318000
#define P3041_OFFSET_BM 0x0031a000
#define P3041_OFFSET_FM 0x00400000
#define P3041_OFFSET_FM_MURAM P3041_OFFSET_FM
#define P3041_OFFSET_FM_BMI (P3041_OFFSET_FM + 0x00080000)
#define P3041_OFFSET_FM_QMI (P3041_OFFSET_FM + 0x00080400)
#define P3041_OFFSET_FM_PARSER (P3041_OFFSET_FM + 0x00080800)
#define P3041_OFFSET_FM_PORT_HO1 (P3041_OFFSET_FM + 0x00081000) /* host command/offline parser */
#define P3041_OFFSET_FM_PORT_HO2 (P3041_OFFSET_FM + 0x00082000)
#define P3041_OFFSET_FM_PORT_HO3 (P3041_OFFSET_FM + 0x00083000)
#define P3041_OFFSET_FM_PORT_HO4 (P3041_OFFSET_FM + 0x00084000)
#define P3041_OFFSET_FM_PORT_HO5 (P3041_OFFSET_FM + 0x00085000)
#define P3041_OFFSET_FM_PORT_HO6 (P3041_OFFSET_FM + 0x00086000)
#define P3041_OFFSET_FM_PORT_HO7 (P3041_OFFSET_FM + 0x00087000)
#define P3041_OFFSET_FM_PORT_1GRX1 (P3041_OFFSET_FM + 0x00088000)
#define P3041_OFFSET_FM_PORT_1GRX2 (P3041_OFFSET_FM + 0x00089000)
#define P3041_OFFSET_FM_PORT_1GRX3 (P3041_OFFSET_FM + 0x0008a000)
#define P3041_OFFSET_FM_PORT_1GRX4 (P3041_OFFSET_FM + 0x0008b000)
#define P3041_OFFSET_FM_PORT_1GRX5 (P3041_OFFSET_FM + 0x0008c000)
#define P3041_OFFSET_FM_PORT_10GRX (P3041_OFFSET_FM + 0x00090000)
#define P3041_OFFSET_FM_PORT_1GTX1 (P3041_OFFSET_FM + 0x000a8000)
#define P3041_OFFSET_FM_PORT_1GTX2 (P3041_OFFSET_FM + 0x000a9000)
#define P3041_OFFSET_FM_PORT_1GTX3 (P3041_OFFSET_FM + 0x000aa000)
#define P3041_OFFSET_FM_PORT_1GTX4 (P3041_OFFSET_FM + 0x000ab000)
#define P3041_OFFSET_FM_PORT_1GTX5 (P3041_OFFSET_FM + 0x000ac000)
#define P3041_OFFSET_FM_PORT_10GTX (P3041_OFFSET_FM + 0x000b0000)
#define P3041_OFFSET_FM_PLCR (P3041_OFFSET_FM + 0x000c0000)
#define P3041_OFFSET_FM_KG (P3041_OFFSET_FM + 0x000c1000)
#define P3041_OFFSET_FM_DMA (P3041_OFFSET_FM + 0x000c2000)
#define P3041_OFFSET_FM_FPM (P3041_OFFSET_FM + 0x000c3000)
#define P3041_OFFSET_FM_IRAM (P3041_OFFSET_FM + 0x000c4000)
#define P3041_OFFSET_FM_PARSER_IRAM (P3041_OFFSET_FM + 0x000c7000)
#define P3041_OFFSET_FM_1GMAC1 (P3041_OFFSET_FM + 0x000e0000)
#define P3041_OFFSET_FM_1GMDIO (P3041_OFFSET_FM + 0x000e1000 + 0x120)
#define P3041_OFFSET_FM_1GMAC2 (P3041_OFFSET_FM + 0x000e2000)
#define P3041_OFFSET_FM_1GMAC3 (P3041_OFFSET_FM + 0x000e4000)
#define P3041_OFFSET_FM_1GMAC4 (P3041_OFFSET_FM + 0x000e6000)
#define P3041_OFFSET_FM_1GMAC5 (P3041_OFFSET_FM + 0x000e8000)
#define P3041_OFFSET_FM_10GMAC (P3041_OFFSET_FM + 0x000f0000)
#define P3041_OFFSET_FM_10GMDIO (P3041_OFFSET_FM + 0x000f1000 + 0x030)
#define P3041_OFFSET_FM_RTC (P3041_OFFSET_FM + 0x000fe000)
/* Offsets relative to QM or BM portals base */
#define P3041_OFFSET_PORTALS_CE_AREA 0x000000 /* cache enabled area */
#define P3041_OFFSET_PORTALS_CI_AREA 0x100000 /* cache inhibited area */
#define P3041_CE_PORTAL_SIZE 0x4000
#define P3041_CI_PORTAL_SIZE 0x1000
#define P3041_OFFSET_PORTALS_CE(portal) \
(P3041_OFFSET_PORTALS_CE_AREA + P3041_CE_PORTAL_SIZE * (portal))
#define P3041_OFFSET_PORTALS_CI(portal) \
(P3041_OFFSET_PORTALS_CI_AREA + P3041_CI_PORTAL_SIZE * (portal))
/**************************************************************************//**
@Description Transaction source ID (for memory controllers error reporting).
*//***************************************************************************/
typedef enum e_TransSrc
{
e_TRANS_SRC_PCIE_1 = 0x0, /**< PCI Express 1 */
e_TRANS_SRC_PCIE_2 = 0x1, /**< PCI Express 2 */
e_TRANS_SRC_PCIE_3 = 0x2, /**< PCI Express 3 */
e_TRANS_SRC_PCIE_4 = 0x3, /**< PCI Express 4 */
e_TRANS_SRC_SRIO_1 = 0x8, /**< SRIO 1 */
e_TRANS_SRC_SRIO_2 = 0x9, /**< SRIO 2 */
e_TRANS_SRC_BMAN = 0x18, /**< BMan */
e_TRANS_SRC_PAMU = 0x1C, /**< PAMU */
e_TRANS_SRC_PME = 0x20, /**< PME */
e_TRANS_SRC_SEC = 0x21, /**< Security engine */
e_TRANS_SRC_QMAN = 0x3C, /**< QMan */
e_TRANS_SRC_USB_1 = 0x40, /**< USB 1 */
e_TRANS_SRC_USB_2 = 0x41, /**< USB 2 */
e_TRANS_SRC_ESDHC = 0x44, /**< eSDHC */
e_TRANS_SRC_PBL = 0x48, /**< Pre-boot loader */
e_TRANS_SRC_NPC = 0x4B, /**< Nexus port controller */
e_TRANS_SRC_RMAN = 0x5D, /**< RIO message manager */
e_TRANS_SRC_SATA_1 = 0x60, /**< SATA 1 */
e_TRANS_SRC_SATA_2 = 0x61, /**< SATA 2 */
e_TRANS_SRC_DMA_1 = 0x70, /**< DMA 1 */
e_TRANS_SRC_DMA_2 = 0x71, /**< DMA 2 */
e_TRANS_SRC_CORE_0_INST = 0x80, /**< Processor 0 (instruction) */
e_TRANS_SRC_CORE_0_DATA = 0x81, /**< Processor 0 (data) */
e_TRANS_SRC_CORE_1_INST = 0x82, /**< Processor 1 (instruction) */
e_TRANS_SRC_CORE_1_DATA = 0x83, /**< Processor 1 (data) */
e_TRANS_SRC_CORE_2_INST = 0x84, /**< Processor 2 (instruction) */
e_TRANS_SRC_CORE_2_DATA = 0x85, /**< Processor 2 (data) */
e_TRANS_SRC_CORE_3_INST = 0x86, /**< Processor 3 (instruction) */
e_TRANS_SRC_CORE_3_DATA = 0x87, /**< Processor 3 (data) */
e_TRANS_SRC_FM_10G = 0xC0, /**< FM XAUI */
e_TRANS_SRC_FM_HO_1 = 0xC1, /**< FM offline, host 1 */
e_TRANS_SRC_FM_HO_2 = 0xC2, /**< FM offline, host 2 */
e_TRANS_SRC_FM_HO_3 = 0xC3, /**< FM offline, host 3 */
e_TRANS_SRC_FM_HO_4 = 0xC4, /**< FM offline, host 4 */
e_TRANS_SRC_FM_HO_5 = 0xC5, /**< FM offline, host 5 */
e_TRANS_SRC_FM_HO_6 = 0xC6, /**< FM offline, host 6 */
e_TRANS_SRC_FM_HO_7 = 0xC7, /**< FM offline, host 7 */
e_TRANS_SRC_FM_GETH_1 = 0xC8, /**< FM GETH 1 */
e_TRANS_SRC_FM_GETH_2 = 0xC9, /**< FM GETH 2 */
e_TRANS_SRC_FM_GETH_3 = 0xCA, /**< FM GETH 3 */
e_TRANS_SRC_FM_GETH_4 = 0xCB, /**< FM GETH 4 */
e_TRANS_SRC_FM_GETH_5 = 0xCC /**< FM GETH 5 */
} e_TransSrc;
/**************************************************************************//**
@Description Local Access Window Target interface ID
*//***************************************************************************/
typedef enum e_P3041LawTargetId
{
e_P3041_LAW_TARGET_PCIE_1 = 0x0, /**< PCI Express 1 */
e_P3041_LAW_TARGET_PCIE_2 = 0x1, /**< PCI Express 2 */
e_P3041_LAW_TARGET_PCIE_3 = 0x2, /**< PCI Express 3 */
e_P3041_LAW_TARGET_PCIE_4 = 0x3, /**< PCI Express 4 */
e_P3041_LAW_TARGET_SRIO_1 = 0x8, /**< SRIO 1 */
e_P3041_LAW_TARGET_SRIO_2 = 0x9, /**< SRIO 2 */
e_P3041_LAW_TARGET_DDR_CPC = 0x10, /**< DDR controller or CPC SRAM */
e_P3041_LAW_TARGET_BMAN = 0x18, /**< BMAN target interface ID */
e_P3041_LAW_TARGET_DCSR = 0x1D, /**< DCSR */
e_P3041_LAW_TARGET_LBC = 0x1F, /**< Local Bus target interface ID */
e_P3041_LAW_TARGET_QMAN = 0x3C, /**< QMAN target interface ID */
e_P3041_LAW_TARGET_NONE = 0xFF /**< None */
} e_P3041LawTargetId;
/***************************************************************
P3041 general routines
****************************************************************/
/**************************************************************************//**
@Group P3041_init_grp P3041 Initialization Unit
@Description P3041 initialization unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Description Part ID and revision number
*//***************************************************************************/
typedef enum e_P3041DeviceName
{
e_P3041_REV_INVALID = 0x00000000, /**< Invalid revision */
e_P3041_REV_1_0 = (int)0x82190310, /**< P3041 with security, revision 1.0 */
e_P3041_REV_1_0_NO_SEC = (int)0x82110310 /**< P3041 without security, revision 1.0 */
} e_P3041DeviceName;
/**************************************************************************//**
@Description Device Disable Register
*//***************************************************************************/
typedef enum e_P3041DeviceDisable
{
e_P3041_DEV_DISABLE_PCIE_1 = 0, /**< PCI Express controller 1 disable */
e_P3041_DEV_DISABLE_PCIE_2, /**< PCI Express controller 2 disable */
e_P3041_DEV_DISABLE_PCIE_3, /**< PCI Express controller 3 disable */
e_P3041_DEV_DISABLE_PCIE_4, /**< PCI Express controller 4 disable */
e_P3041_DEV_DISABLE_RMAN, /**< RapidIO message manager disable */
e_P3041_DEV_DISABLE_SRIO_1, /**< Serial RapidIO controller 1 disable */
e_P3041_DEV_DISABLE_SRIO_2, /**< Serial RapidIO controller 2 disable */
e_P3041_DEV_DISABLE_DMA_1 = 9, /**< DMA controller 1 disable */
e_P3041_DEV_DISABLE_DMA_2, /**< DMA controller 2 disable */
e_P3041_DEV_DISABLE_DDR, /**< DDR controller disable */
e_P3041_DEV_DISABLE_SATA_1 = 17, /**< SATA controller 1 disable */
e_P3041_DEV_DISABLE_SATA_2, /**< SATA controller 2 disable */
e_P3041_DEV_DISABLE_LBC, /**< eLBC controller disable */
e_P3041_DEV_DISABLE_USB_1, /**< USB controller 1 disable */
e_P3041_DEV_DISABLE_USB_2, /**< USB controller 2 disable */
e_P3041_DEV_DISABLE_ESDHC = 23, /**< eSDHC controller disable */
e_P3041_DEV_DISABLE_GPIO, /**< GPIO controller disable */
e_P3041_DEV_DISABLE_ESPI, /**< eSPI controller disable */
e_P3041_DEV_DISABLE_I2C_1, /**< I2C module 1 (controllers 1 and 2) disable */
e_P3041_DEV_DISABLE_I2C_2, /**< I2C module 2 (controllers 3 and 4) disable */
e_P3041_DEV_DISABLE_DUART_1 = 30, /**< DUART controller 1 disable */
e_P3041_DEV_DISABLE_DUART_2, /**< DUART controller 2 disable */
e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST = 32,
/**< Dummy entry signing end of DEVDISR1 register controllers */
e_P3041_DEV_DISABLE_PME = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST,
/**< Pattern match engine disable */
e_P3041_DEV_DISABLE_SEC, /**< Security disable */
e_P3041_DEV_DISABLE_QM_BM = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST + 4,
/**< Queue manager/buffer manager disable */
e_P3041_DEV_DISABLE_FM = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST + 6,
/**< Frame manager disable */
e_P3041_DEV_DISABLE_10G, /**< 10G Ethernet controller disable */
e_P3041_DEV_DISABLE_DTSEC_1, /**< dTSEC controller 1 disable */
e_P3041_DEV_DISABLE_DTSEC_2, /**< dTSEC controller 2 disable */
e_P3041_DEV_DISABLE_DTSEC_3, /**< dTSEC controller 3 disable */
e_P3041_DEV_DISABLE_DTSEC_4, /**< dTSEC controller 4 disable */
e_P3041_DEV_DISABLE_DTSEC_5 /**< dTSEC controller 5 disable */
} e_P3041DeviceDisable;
/**************************************************************************//*
@Description structure representing P3041 devices configuration
*//***************************************************************************/
typedef struct t_P3041Devices
{
struct
{
struct
{
bool enabled;
uint8_t serdesBank;
uint16_t serdesLane; /**< Most significant bits represent lanes used by this bank,
one bit for lane, lane A is the first and so on, e.g.,
set 0xF000 for ABCD lanes */
e_EnetInterface ethIf;
uint8_t ratio;
bool divByTwo;
bool isTwoHalfSgmii;
} dtsecs[FM_MAX_NUM_OF_1G_MACS];
struct
{
bool enabled;
uint8_t serdesBank;
uint16_t serdesLane;
} tgec;
} fm;
} t_P3041Devices;
/**************************************************************************//**
@Function P3041_GetRevInfo
@Description Obtain revision information.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return Part ID and revision.
*//***************************************************************************/
e_P3041DeviceName P3041_GetRevInfo(uintptr_t gutilBase);
/**************************************************************************//**
@Function P3041_GetE500Factor
@Description Obtain core's multiplication factors.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Param[in] coreIndex - Core index.
@Param[out] p_E500MulFactor - E500 to CCB multification factor.
@Param[out] p_E500DivFactor - E500 to CCB division factor.
*//***************************************************************************/
void P3041_GetE500Factor(uintptr_t gutilBase,
uint8_t coreIndex,
uint32_t *p_E500MulFactor,
uint32_t *p_E500DivFactor);
/**************************************************************************//**
@Function P3041_GetCcbFactor
@Description Obtain system multiplication factor.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return System multiplication factor.
*//***************************************************************************/
uint32_t P3041_GetCcbFactor(uintptr_t gutilBase);
/**************************************************************************//**
@Function P3041_GetDdrFactor
@Description Obtain DDR clock multiplication factor.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return DDR clock multiplication factor.
*//***************************************************************************/
uint32_t P3041_GetDdrFactor(uintptr_t gutilBase);
/**************************************************************************//**
@Function P3041_GetDdrType
@Description Obtain DDR memory type.
@Param[in] gutilBase - Gutil memory map virtual base address.
@Return DDR type.
*//***************************************************************************/
e_DdrType P3041_GetDdrType(uintptr_t gutilBase);
/**************************************************************************//**
@Function P3041_GetFmFactor
@Description returns FM multiplication factors. (This value is returned using
two parameters to avoid using float parameter).
@Param[in] gutilBase - Gutil memory map virtual base address.
@Param[out] p_FmMulFactor - FM to CCB multification factor.
@Param[out] p_FmDivFactor - FM to CCB division factor.
*//***************************************************************************/
void P3041_GetFmFactor(uintptr_t gutilBase,
uint32_t *p_FmMulFactor,
uint32_t *p_FmDivFactor);
void P3041_CoreTimeBaseEnable(uintptr_t rcpmBase);
void P3041_CoreTimeBaseDisable(uintptr_t rcpmBase);
typedef enum e_SerdesProtocol
{
SRDS_PROTOCOL_NONE = 0,
SRDS_PROTOCOL_PCIE1,
SRDS_PROTOCOL_PCIE2,
SRDS_PROTOCOL_PCIE3,
SRDS_PROTOCOL_PCIE4,
SRDS_PROTOCOL_SRIO1,
SRDS_PROTOCOL_SRIO2,
SRDS_PROTOCOL_SGMII_FM,
SRDS_PROTOCOL_XAUI_FM,
SRDS_PROTOCOL_SATA1,
SRDS_PROTOCOL_SATA2,
SRDS_PROTOCOL_AURORA
} e_SerdesProtocol;
t_Error P3041_DeviceDisable(uintptr_t gutilBase, e_P3041DeviceDisable device, bool disable);
void P3041_GetDevicesConfiguration(uintptr_t gutilBase, t_P3041Devices *p_Devices);
t_Error P3041_PamuDisableBypass(uintptr_t gutilBase, uint8_t pamuId, bool disable);
uint32_t P3041_SerdesRcwGetProtocol(uintptr_t gutilBase);
bool P3041_SerdesRcwIsDeviceConfigured(uintptr_t gutilBase, e_SerdesProtocol device);
bool P3041_SerdesRcwIsLaneEnabled(uintptr_t gutilBase, uint32_t lane);
/** @} */ /* end of P3041_init_grp group */
/** @} */ /* end of P3041_grp group */
/*****************************************************************************
INTEGRATION-SPECIFIC MODULE CODES
******************************************************************************/
#define MODULE_UNKNOWN 0x00000000
#define MODULE_MEM 0x00010000
#define MODULE_MM 0x00020000
#define MODULE_CORE 0x00030000
#define MODULE_P3041 0x00040000
#define MODULE_P3041_PLATFORM 0x00050000
#define MODULE_PM 0x00060000
#define MODULE_MMU 0x00070000
#define MODULE_PIC 0x00080000
#define MODULE_CPC 0x00090000
#define MODULE_DUART 0x000a0000
#define MODULE_SERDES 0x000b0000
#define MODULE_PIO 0x000c0000
#define MODULE_QM 0x000d0000
#define MODULE_BM 0x000e0000
#define MODULE_SEC 0x000f0000
#define MODULE_LAW 0x00100000
#define MODULE_LBC 0x00110000
#define MODULE_PAMU 0x00120000
#define MODULE_FM 0x00130000
#define MODULE_FM_MURAM 0x00140000
#define MODULE_FM_PCD 0x00150000
#define MODULE_FM_RTC 0x00160000
#define MODULE_FM_MAC 0x00170000
#define MODULE_FM_PORT 0x00180000
#define MODULE_DPA 0x00190000
#define MODULE_MII 0x001a0000
#define MODULE_I2C 0x001b0000
#define MODULE_DMA 0x001c0000
#define MODULE_DDR 0x001d0000
#define MODULE_ESPI 0x001e0000
/*****************************************************************************
PAMU INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define PAMU_NUM_OF_PARTITIONS 4
/*****************************************************************************
LAW INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define LAW_NUM_OF_WINDOWS 32
#define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */
#define LAW_MAX_WINDOW_SIZE 0x0000002000000000LL /**< 64GB */
/*****************************************************************************
LBC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
/**************************************************************************//**
@Group lbc_exception_grp LBC Exception Unit
@Description LBC Exception unit API functions, definitions and enums
@{
*//***************************************************************************/
/**************************************************************************//**
@Anchor lbc_exbm
@Collection LBC Errors Bit Mask
These errors are reported through the exceptions callback..
The values can be or'ed in any combination in the errors mask
parameter of the errors report structure.
These errors can also be passed as a bit-mask to
LBC_EnableErrorChecking() or LBC_DisableErrorChecking(),
for enabling or disabling error checking.
@{
*//***************************************************************************/
#define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */
#define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */
#define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */
#define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */
#define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \
LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT)
/**< All possible errors */
/* @} */
/** @} */ /* end of lbc_exception_grp group */
#define LBC_INCORRECT_ERROR_REPORT_ERRATA
#define LBC_NUM_OF_BANKS 8
#define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */
#define LBC_PARITY_SUPPORT
#define LBC_HIGH_CLK_DIVIDERS
#define LBC_FCM_AVAILABLE
/*****************************************************************************
GPIO INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define GPIO_NUM_OF_PORTS 1 /**< Number of ports in GPIO module;
Each port contains up to 32 I/O pins. */
#define GPIO_VALID_PIN_MASKS \
{ /* Port A */ 0xFFFFFFFF }
#define GPIO_VALID_INTR_MASKS \
{ /* Port A */ 0xFFFFFFFF }
/*****************************************************************************
SERDES INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define SRDS_MAX_LANES 18
#define SRDS_MAX_BANK 3
/* Serdes lanes general information provided in the following form:
1) Lane index in Serdes Control Registers Map
2) Lane enable/disable bit number in RCW
3) Lane bank index */
#define SRDS_LANES \
{ \
{ 0, 152, 0 }, \
{ 1, 153, 0 }, \
{ 2, 154, 0 }, \
{ 3, 155, 0 }, \
{ 4, 156, 0 }, \
{ 5, 157, 0 }, \
{ 6, 158, 0 }, \
{ 7, 159, 0 }, \
{ 8, 160, 0 }, \
{ 9, 161, 0 }, \
{ 16, 162, 1 }, \
{ 17, 163, 1 }, \
{ 18, 164, 1 }, \
{ 19, 165, 1 }, \
{ 20, 166, 2 }, \
{ 21, 167, 2 }, \
{ 22, 168, 2 }, \
{ 23, 169, 2 } \
}
#define SRDS_PROTOCOL_ALL_OPTIONS
/* Serdes lanes assignment and multiplexing.
Each option is selected by SRDS_PRTCL bits of RCW. */
#define SRDS_PROTOCOL_OPTIONS \
/* Protocol Lane assignment */ \
{ \
/* 0x00 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x01 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x02 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x03 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x04 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x05 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x06 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x07 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x08 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x09 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x0A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x0B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x0C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x0D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x0E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x0F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x10 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x11 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x12 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x13 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x14 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x15 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x16 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1}, \
/* 0x17 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x18 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x19 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x1A */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x1B */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x1C */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x1D */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x1E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x1F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x20 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x21 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x22 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x23 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x24 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x25 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x26 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
/* 0x27 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x28 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x29 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x2A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x2B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x2C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x2D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x2E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x2F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x30 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x31 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
/* 0x32 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
/* 0x33 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x34 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x35 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x36 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
/* 0x37 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2} \
}
/*****************************************************************************
DDR INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define DDR_NUM_OF_VALID_CS 4
/*****************************************************************************
DMA INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define DMA_NUM_OF_CONTROLLERS 2
/*****************************************************************************
CPC INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define CPC_MAX_SIZE_SRAM_ERRATA_CPC4
#define CPC_HARDWARE_FLUSH_ERRATA_CPC10
#endif /* __PART_INTEGRATION_EXT_H */

374
sys/contrib/ncsw/inc/integrations/P5020/dpaa_integration_ext.h Normal file
View File

@ -0,0 +1,374 @@
/******************************************************************************
© 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
All rights reserved.
This is proprietary source code of Freescale Semiconductor Inc.,
and its use is subject to the NetComm Device Drivers EULA.
The copyright notice above does not evidence any actual or intended
publication of such source code.
ALTERNATIVELY, redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Freescale Semiconductor nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**************************************************************************/
/**
@File dpaa_integration_ext.h
@Description P5020 FM external definitions and structures.
*//***************************************************************************/
#ifndef __DPAA_INTEGRATION_EXT_H
#define __DPAA_INTEGRATION_EXT_H
#include "std_ext.h"
/**************************************************************************//**
@Description DPAA SW Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_SWPORTAL0 = 0,
e_DPAA_SWPORTAL1,
e_DPAA_SWPORTAL2,
e_DPAA_SWPORTAL3,
e_DPAA_SWPORTAL4,
e_DPAA_SWPORTAL5,
e_DPAA_SWPORTAL6,
e_DPAA_SWPORTAL7,
e_DPAA_SWPORTAL8,
e_DPAA_SWPORTAL9,
e_DPAA_SWPORTAL_DUMMY_LAST
} e_DpaaSwPortal;
/**************************************************************************//**
@Description DPAA Direct Connect Portals Enumeration.
*//***************************************************************************/
typedef enum
{
e_DPAA_DCPORTAL0 = 0,
e_DPAA_DCPORTAL1,
e_DPAA_DCPORTAL2,
e_DPAA_DCPORTAL3,
e_DPAA_DCPORTAL4,
e_DPAA_DCPORTAL_DUMMY_LAST
} e_DpaaDcPortal;
#define DPAA_MAX_NUM_OF_SW_PORTALS e_DPAA_SWPORTAL_DUMMY_LAST
#define DPAA_MAX_NUM_OF_DC_PORTALS e_DPAA_DCPORTAL_DUMMY_LAST
/*****************************************************************************
QMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define QM_MAX_NUM_OF_POOL_CHANNELS 15 /**< Total number of channels, dedicated and pool */
#define QM_MAX_NUM_OF_WQ 8 /**< Number of work queues per channel */
#define QM_MAX_NUM_OF_CGS 256 /**< Congestion groups number */
#define QM_MAX_NUM_OF_FQIDS (16 * MEGABYTE)
/**< FQIDs range - 24 bits */
/**************************************************************************//**
@Description Work Queue Channel assignments in QMan.
*//***************************************************************************/
typedef enum
{
e_QM_FQ_CHANNEL_SWPORTAL0 = 0, /**< Dedicated channels serviced by software portals 0 to 9 */
e_QM_FQ_CHANNEL_SWPORTAL1,
e_QM_FQ_CHANNEL_SWPORTAL2,
e_QM_FQ_CHANNEL_SWPORTAL3,
e_QM_FQ_CHANNEL_SWPORTAL4,
e_QM_FQ_CHANNEL_SWPORTAL5,
e_QM_FQ_CHANNEL_SWPORTAL6,
e_QM_FQ_CHANNEL_SWPORTAL7,
e_QM_FQ_CHANNEL_SWPORTAL8,
e_QM_FQ_CHANNEL_SWPORTAL9,
e_QM_FQ_CHANNEL_POOL1 = 0x21, /**< Pool channels that can be serviced by any of the software portals */
e_QM_FQ_CHANNEL_POOL2,
e_QM_FQ_CHANNEL_POOL3,
e_QM_FQ_CHANNEL_POOL4,
e_QM_FQ_CHANNEL_POOL5,
e_QM_FQ_CHANNEL_POOL6,
e_QM_FQ_CHANNEL_POOL7,
e_QM_FQ_CHANNEL_POOL8,
e_QM_FQ_CHANNEL_POOL9,
e_QM_FQ_CHANNEL_POOL10,
e_QM_FQ_CHANNEL_POOL11,
e_QM_FQ_CHANNEL_POOL12,
e_QM_FQ_CHANNEL_POOL13,
e_QM_FQ_CHANNEL_POOL14,
e_QM_FQ_CHANNEL_POOL15,
e_QM_FQ_CHANNEL_FMAN0_SP0 = 0x40, /**< Dedicated channels serviced by Direct Connect Portal 0:
connected to FMan 0; assigned in incrementing order to
each sub-portal (SP) in the portal */
e_QM_FQ_CHANNEL_FMAN0_SP1,
e_QM_FQ_CHANNEL_FMAN0_SP2,
e_QM_FQ_CHANNEL_FMAN0_SP3,
e_QM_FQ_CHANNEL_FMAN0_SP4,
e_QM_FQ_CHANNEL_FMAN0_SP5,
e_QM_FQ_CHANNEL_FMAN0_SP6,
e_QM_FQ_CHANNEL_FMAN0_SP7,
e_QM_FQ_CHANNEL_FMAN0_SP8,
e_QM_FQ_CHANNEL_FMAN0_SP9,
e_QM_FQ_CHANNEL_FMAN0_SP10,
e_QM_FQ_CHANNEL_FMAN0_SP11,
e_QM_FQ_CHANNEL_RMAN_SP2 = 0x62, /**< Dedicated channels serviced by Direct Connect Portal 1: connected to RMan */
e_QM_FQ_CHANNEL_RMAN_SP3,
e_QM_FQ_CHANNEL_CAAM = 0x80, /**< Dedicated channel serviced by Direct Connect Portal 2:
connected to SEC 4.x */
e_QM_FQ_CHANNEL_PME = 0xA0, /**< Dedicated channel serviced by Direct Connect Portal 3:
connected to PME */
e_QM_FQ_CHANNEL_RAID = 0xC0 /**< Dedicated channel serviced by Direct Connect Portal 4:
connected to RAID */
} e_QmFQChannel;
/*****************************************************************************
BMan INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define BM_MAX_NUM_OF_POOLS 64 /**< Number of buffers pools */
/*****************************************************************************
FM INTEGRATION-SPECIFIC DEFINITIONS
******************************************************************************/
#define INTG_MAX_NUM_OF_FM 1
/* Ports defines */
#define FM_MAX_NUM_OF_1G_MACS 5
#define FM_MAX_NUM_OF_10G_MACS 1
#define FM_MAX_NUM_OF_MACS (FM_MAX_NUM_OF_1G_MACS + FM_MAX_NUM_OF_10G_MACS)
#define FM_MAX_NUM_OF_OH_PORTS 7
#define FM_MAX_NUM_OF_1G_RX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_RX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_RX_PORTS (FM_MAX_NUM_OF_10G_RX_PORTS + FM_MAX_NUM_OF_1G_RX_PORTS)
#define FM_MAX_NUM_OF_1G_TX_PORTS FM_MAX_NUM_OF_1G_MACS
#define FM_MAX_NUM_OF_10G_TX_PORTS FM_MAX_NUM_OF_10G_MACS
#define FM_MAX_NUM_OF_TX_PORTS (FM_MAX_NUM_OF_10G_TX_PORTS + FM_MAX_NUM_OF_1G_TX_PORTS)
#define FM_PORT_MAX_NUM_OF_EXT_POOLS 8 /**< Number of external BM pools per Rx port */
#define FM_PORT_NUM_OF_CONGESTION_GRPS 256 /**< Total number of congestion groups in QM */
#define FM_MAX_NUM_OF_SUB_PORTALS 12
#define FM_PORT_MAX_NUM_OF_OBSERVED_EXT_POOLS 0
/* RAMs defines */
#define FM_MURAM_SIZE (160 * KILOBYTE)
#define FM_IRAM_SIZE ( 64 * KILOBYTE)
/* PCD defines */
#define FM_PCD_PLCR_NUM_ENTRIES 256 /**< Total number of policer profiles */
#define FM_PCD_KG_NUM_OF_SCHEMES 32 /**< Total number of KG schemes */
#define FM_PCD_MAX_NUM_OF_CLS_PLANS 256 /**< Number of classification plan entries. */
/* RTC defines */
#define FM_RTC_NUM_OF_ALARMS 2 /**< RTC number of alarms */
#define FM_RTC_NUM_OF_PERIODIC_PULSES 2 /**< RTC number of periodic pulses */
#define FM_RTC_NUM_OF_EXT_TRIGGERS 2 /**< RTC number of external triggers */
/* QMI defines */
#define QMI_MAX_NUM_OF_TNUMS 64
#define MAX_QMI_DEQ_SUBPORTAL 12
#define QMI_DEF_TNUMS_THRESH 48
/* FPM defines */
#define FM_NUM_OF_FMAN_CTRL_EVENT_REGS 4
/* DMA defines */
#define DMA_THRESH_MAX_COMMQ 31
#define DMA_THRESH_MAX_BUF 127
/* BMI defines */
#define BMI_MAX_NUM_OF_TASKS 128
#define BMI_MAX_NUM_OF_DMAS 32
#define BMI_MAX_FIFO_SIZE (FM_MURAM_SIZE)
#define PORT_MAX_WEIGHT 16
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmEventModules
{
e_FM_MOD_PRS, /**< Parser event */
e_FM_MOD_KG, /**< Keygen event */
e_FM_MOD_PLCR, /**< Policer event */
e_FM_MOD_10G_MAC, /**< 10G MAC error event */
e_FM_MOD_1G_MAC, /**< 1G MAC error event */
e_FM_MOD_TMR, /**< Timer event */
e_FM_MOD_1G_MAC_TMR, /**< 1G MAC timer event */
e_FM_MOD_FMAN_CTRL, /**< FMAN Controller timer event */
e_FM_MOD_DUMMY_LAST
} e_FmEventModules;
/**************************************************************************//**
@Description Enum for interrupts types
*//***************************************************************************/
typedef enum e_FmIntrType
{
e_FM_INTR_TYPE_ERR,
e_FM_INTR_TYPE_NORMAL
} e_FmIntrType;
/**************************************************************************//**
@Description Enum for inter-module interrupts registration
*//***************************************************************************/
typedef enum e_FmInterModuleEvent
{
e_FM_EV_PRS, /**< Parser event */
e_FM_EV_ERR_PRS, /**< Parser error event */
e_FM_EV_KG, /**< Keygen event */
e_FM_EV_ERR_KG, /**< Keygen error event */
e_FM_EV_PLCR, /**< Policer event */
e_FM_EV_ERR_PLCR, /**< Policer error event */
e_FM_EV_ERR_10G_MAC0, /**< 10G MAC 0 error event */
e_FM_EV_ERR_1G_MAC0, /**< 1G MAC 0 error event */
e_FM_EV_ERR_1G_MAC1, /**< 1G MAC 1 error event */
e_FM_EV_ERR_1G_MAC2, /**< 1G MAC 2 error event */
e_FM_EV_ERR_1G_MAC3, /**< 1G MAC 3 error event */
e_FM_EV_ERR_1G_MAC4, /**< 1G MAC 4 error event */
e_FM_EV_TMR, /**< Timer event */
e_FM_EV_1G_MAC0_TMR, /**< 1G MAC 0 timer event */
e_FM_EV_1G_MAC1_TMR, /**< 1G MAC 1 timer event */
e_FM_EV_1G_MAC2_TMR, /**< 1G MAC 2 timer event */
e_FM_EV_1G_MAC3_TMR, /**< 1G MAC 3 timer event */
e_FM_EV_1G_MAC4_TMR, /**< 1G MAC 4 timer event */
e_FM_EV_FMAN_CTRL_0, /**< Fman controller event 0 */
e_FM_EV_FMAN_CTRL_1, /**< Fman controller event 1 */
e_FM_EV_FMAN_CTRL_2, /**< Fman controller event 2 */
e_FM_EV_FMAN_CTRL_3, /**< Fman controller event 3 */
e_FM_EV_DUMMY_LAST
} e_FmInterModuleEvent;
#define GET_FM_MODULE_EVENT(mod, id, intrType, event) \
switch(mod){ \
case e_FM_MOD_PRS: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \
break; \
case e_FM_MOD_KG: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_PLCR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \
break; \
case e_FM_MOD_10G_MAC: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_10G_MAC0 : e_FM_EV_DUMMY_LAST; \
break; \
case e_FM_MOD_1G_MAC: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC0 : e_FM_EV_DUMMY_LAST; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC1 : e_FM_EV_DUMMY_LAST; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC2 : e_FM_EV_DUMMY_LAST; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC3 : e_FM_EV_DUMMY_LAST; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_1G_MAC4 : e_FM_EV_DUMMY_LAST; break; \
} \
break; \
case e_FM_MOD_TMR: \
if (id) event = e_FM_EV_DUMMY_LAST; \
else event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \
break; \
case e_FM_MOD_1G_MAC_TMR: \
switch(id){ \
case(0): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC0_TMR; break; \
case(1): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC1_TMR; break; \
case(2): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC2_TMR; break; \
case(3): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC3_TMR; break; \
case(4): event = (intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_1G_MAC4_TMR; break; \
} \
break; \
case e_FM_MOD_FMAN_CTRL: \
if (intrType == e_FM_INTR_TYPE_ERR) event = e_FM_EV_DUMMY_LAST; \
else switch(id){ \
case(0): event = e_FM_EV_FMAN_CTRL_0; break; \
case(1): event = e_FM_EV_FMAN_CTRL_1; break; \
case(2): event = e_FM_EV_FMAN_CTRL_2; break; \
case(3): event = e_FM_EV_FMAN_CTRL_3; break; \
} \
break; \
default: event = e_FM_EV_DUMMY_LAST; \
break;}
#define FM_CHECK_PORT_RESTRICTIONS(__validPorts, __newPortIndx) TRUE
/* P5020 unique features */
#define FM_QMI_DEQ_OPTIONS_SUPPORT
#define FM_NO_DISPATCH_RAM_ECC
#define FM_FIFO_ALLOCATION_OLD_ALG
#define FM_NO_WATCHDOG
#define FM_NO_TNUM_AGING
#define FM_NO_TGEC_LOOPBACK
#define FM_KG_NO_BYPASS_FQID_GEN
#define FM_KG_NO_BYPASS_PLCR_PROFILE_GEN
#define FM_NO_BACKUP_POOLS
#define FM_NO_OP_OBSERVED_POOLS
#define FM_NO_ADVANCED_RATE_LIMITER
#define FM_NO_OP_OBSERVED_CGS
/* FM erratas */
#define FM_TX_ECC_FRMS_ERRATA_10GMAC_A004
#define FM_TX_SHORT_FRAME_BAD_TS_ERRATA_10GMAC_A006 /* No implementation, Out of LLD scope */
#define FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007
#define FM_ECC_HALT_NO_SYNC_ERRATA_10GMAC_A008
#define FM_NO_RX_PREAM_ERRATA_DTSECx1
#define FM_RX_PREAM_4_ERRATA_DTSEC_A001 FM_NO_RX_PREAM_ERRATA_DTSECx1
#define FM_GRS_ERRATA_DTSEC_A002
#define FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003
#define FM_GTS_ERRATA_DTSEC_A004
#define FM_PAUSE_BLOCK_ERRATA_DTSEC_A006 /* do nothing */
#define FM_RESERVED_ACCESS_TO_DISABLED_DEV_ERRATA_DTSEC_A0011 /* do nothing */
#define FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012 FM_GTS_ERRATA_DTSEC_A004
#define FM_MAGIC_PACKET_UNRECOGNIZED_ERRATA_DTSEC2 /* No implementation, Out of LLD scope */
#define FM_10_100_SGMII_NO_TS_ERRATA_DTSEC3
#define FM_TX_LOCKUP_ERRATA_DTSEC6
#define FM_IM_TX_SYNC_SKIP_TNUM_ERRATA_FMAN_A001 /* Implemented by ucode */
#define FM_HC_DEF_FQID_ONLY_ERRATA_FMAN_A003 /* Implemented by ucode */
#define FM_IM_TX_SHARED_TNUM_ERRATA_FMAN4 /* Implemented by ucode */
#define FM_IM_GS_DEADLOCK_ERRATA_FMAN5 /* Implemented by ucode */
#define FM_IM_DEQ_PIPELINE_DEPTH_ERRATA_FMAN10 /* Implemented by ucode */
#define FM_CC_GEN6_MISSMATCH_ERRATA_FMAN12 /* Implemented by ucode */
#define FM_CC_CHANGE_SHARED_TNUM_ERRATA_FMAN13 /* Implemented by ucode */
#define FM_IM_LARGE_MRBLR_ERRATA_FMAN15 /* Implemented by ucode */
#define FM_BMI_TO_RISC_ENQ_ERRATA_FMANc /* No implementation, Out of LLD scope */
#define FM_INVALID_SWPRS_DATA_ERRATA_FMANd
//#define FM_PRS_MPLS_SSA_ERRATA_FMANj /* No implementation, No patch yet */
//#define FM_PRS_INITIAL_PLANID_ERRATA_FMANk /* No implementation, No patch yet */
#define FM_UCODE_NOT_RESET_ERRATA_BUGZILLA6173
#define FM_NO_COPY_CTXA_CTXB_ERRATA_FMAN_SW001
#define FM_PRS_MEM_ERRATA_FMAN_SW003
#define FM_LEN_CHECK_ERRATA_FMAN_SW002
#define FM_10G_REM_N_LCL_FLT_EX_ERRATA_10GMAC001
#endif /* __DPAA_INTEGRATION_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File part_ext.h
@Description Definitions for the part (integration) module.
*//***************************************************************************/
#ifndef __PART_EXT_H
#define __PART_EXT_H
#include "std_ext.h"
#include "part_integration_ext.h"
#if !(defined(MPC8306) || \
defined(MPC8309) || \
defined(MPC834x) || \
defined(MPC836x) || \
defined(MPC832x) || \
defined(MPC837x) || \
defined(MPC8568) || \
defined(MPC8569) || \
defined(P1020) || \
defined(P1021) || \
defined(P1022) || \
defined(P1023) || \
defined(P2020) || \
defined(P2040) || \
defined(P2041) || \
defined(P3041) || \
defined(P4080) || \
defined(SC4080) || \
defined(P5020) || \
defined(MSC814x))
#error "unable to proceed without chip-definition"
#endif /* !(defined(MPC834x) || ... */
/**************************************************************************//*
@Description Part data structure - must be contained in any integration
data structure.
*//***************************************************************************/
typedef struct t_Part
{
uintptr_t (* f_GetModuleBase)(t_Handle h_Part, e_ModuleId moduleId);
/**< Returns the address of the module's memory map base. */
e_ModuleId (* f_GetModuleIdByBase)(t_Handle h_Part, uintptr_t baseAddress);
/**< Returns the module's ID according to its memory map base. */
} t_Part;
#endif /* __PART_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MATH_EXT_H
#define __MATH_EXT_H
#if defined(NCSW_LINUX) && defined(__KERNEL__)
#include <linux/math.h>
#elif defined(__MWERKS__)
#define LOW(x) ( sizeof(x)==8 ? *(1+(int32_t*)&x) : (*(int32_t*)&x))
#define HIGH(x) (*(int32_t*)&x)
#define ULOW(x) ( sizeof(x)==8 ? *(1+(uint32_t*)&x) : (*(uint32_t*)&x))
#define UHIGH(x) (*(uint32_t*)&x)
static const double big = 1.0e300;
/* Macro for checking if a number is a power of 2 */
static __inline__ double ceil(double x)
{
int32_t i0,i1,j0; /*- cc 020130 -*/
uint32_t i,j; /*- cc 020130 -*/
i0 = HIGH(x);
i1 = LOW(x);
j0 = ((i0>>20)&0x7ff)-0x3ff;
if(j0<20) {
if(j0<0) { /* raise inexact if x != 0 */
if(big+x>0.0) {/* return 0*sign(x) if |x|<1 */
if(i0<0) {i0=0x80000000;i1=0;}
else if((i0|i1)!=0) { i0=0x3ff00000;i1=0;}
}
} else {
i = (uint32_t)(0x000fffff)>>j0;
if(((i0&i)|i1)==0) return x; /* x is integral */
if(big+x>0.0) { /* raise inexact flag */
if(i0>0) i0 += (0x00100000)>>j0;
i0 &= (~i); i1=0;
}
}
} else if (j0>51) {
if(j0==0x400) return x+x; /* inf or NaN */
else return x; /* x is integral */
} else {
i = ((uint32_t)(0xffffffff))>>(j0-20); /*- cc 020130 -*/
if((i1&i)==0) return x; /* x is integral */
if(big+x>0.0) { /* raise inexact flag */
if(i0>0) {
if(j0==20) i0+=1;
else {
j = (uint32_t)(i1 + (1<<(52-j0)));
if(j<i1) i0+=1; /* got a carry */
i1 = (int32_t)j;
}
}
i1 &= (~i);
}
}
HIGH(x) = i0;
LOW(x) = i1;
return x;
}
#else
#include <math.h>
#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */
#endif /* __MATH_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File ncsw_ext.h
@Description General NetCommSw Standard Definitions
*//***************************************************************************/
#ifndef __NCSW_EXT_H
#define __NCSW_EXT_H
#include "memcpy_ext.h"
#define WRITE_BLOCK IOMemSet32
#define COPY_BLOCK Mem2IOCpy32
#define PTR_TO_UINT(_ptr) ((uintptr_t)(_ptr))
#define UINT_TO_PTR(_val) ((void*)(uintptr_t)(_val))
#define PTR_MOVE(_ptr, _offset) (void*)((uint8_t*)(_ptr) + (_offset))
#define WRITE_UINT8_UINT24(arg, data08, data24) WRITE_UINT32(arg,((uint32_t)(data08)<<24)|((uint32_t)(data24)&0x00FFFFFF))
#define WRITE_UINT24_UINT8(arg, data24, data08) WRITE_UINT32(arg,((uint32_t)(data24)<< 8)|((uint32_t)(data08)&0x000000FF))
/* Little-Endian access macros */
#define WRITE_UINT16_LE(arg, data) \
WRITE_UINT16((arg), SwapUint16(data))
#define WRITE_UINT32_LE(arg, data) \
WRITE_UINT32((arg), SwapUint32(data))
#define WRITE_UINT64_LE(arg, data) \
WRITE_UINT64((arg), SwapUint64(data))
#define GET_UINT16_LE(arg) \
SwapUint16(GET_UINT16(arg))
#define GET_UINT32_LE(arg) \
SwapUint32(GET_UINT32(arg))
#define GET_UINT64_LE(arg) \
SwapUint64(GET_UINT64(arg))
/* Write and Read again macros */
#define WRITE_UINT_SYNC(size, arg, data) \
do { \
WRITE_UINT##size((arg), (data)); \
CORE_MemoryBarrier(); \
} while (0)
#define WRITE_UINT8_SYNC(arg, data) WRITE_UINT_SYNC(8, (arg), (data))
#define WRITE_UINT16_SYNC(arg, data) WRITE_UINT_SYNC(16, (arg), (data))
#define WRITE_UINT32_SYNC(arg, data) WRITE_UINT_SYNC(32, (arg), (data))
#define MAKE_UINT64(high32, low32) (((uint64_t)high32 << 32) | (low32))
/*----------------------*/
/* Miscellaneous macros */
/*----------------------*/
#define UNUSED(X) (X=X)
#define KILOBYTE 0x400UL /* 1024 */
#define MEGABYTE (KILOBYTE * KILOBYTE) /* 1024*1024 */
#define GIGABYTE (KILOBYTE * MEGABYTE) /* 1024*1024*1024 */
#undef NO_IRQ
#define NO_IRQ (-1)
#define NCSW_MASTER_ID (0)
/* Macro for checking if a number is a power of 2 */
#define POWER_OF_2(n) (!((n) & ((n)-1)))
/* Macro for calculating log of base 2 */
#define LOG2(num, log2Num) \
do \
{ \
uint64_t tmp = (num); \
log2Num = 0; \
while (tmp > 1) \
{ \
log2Num++; \
tmp >>= 1; \
} \
} while (0)
#define NEXT_POWER_OF_2(_num, _nextPow) \
do \
{ \
if (POWER_OF_2(_num)) \
_nextPow = (_num); \
else \
{ \
uint64_t tmp = (_num); \
_nextPow = 1; \
while (tmp) \
{ \
_nextPow <<= 1; \
tmp >>= 1; \
} \
} \
} while (0)
/* Ceiling division - not the fastest way, but safer in terms of overflow */
#define DIV_CEIL(x,y) (((x)/(y)) + ((((((x)/(y)))*(y)) == (x)) ? 0 : 1))
/* Round up a number to be a multiple of a second number */
#define ROUND_UP(x,y) ((((x) + (y) - 1) / (y)) * (y))
/* Timing macro for converting usec units to number of ticks. */
/* (number of usec * clock_Hz) / 1,000,000) - since */
/* clk is in MHz units, no division needed. */
#define USEC_TO_CLK(usec,clk) ((usec) * (clk))
#define CYCLES_TO_USEC(cycles,clk) ((cycles) / (clk))
/* Timing macros for converting between nsec units and number of clocks. */
#define NSEC_TO_CLK(nsec,clk) DIV_CEIL(((nsec) * (clk)), 1000)
#define CYCLES_TO_NSEC(cycles,clk) (((cycles) * 1000) / (clk))
/* Timing macros for converting between psec units and number of clocks. */
#define PSEC_TO_CLK(psec,clk) DIV_CEIL(((psec) * (clk)), 1000000)
#define CYCLES_TO_PSEC(cycles,clk) (((cycles) * 1000000) / (clk))
/* Min, Max macros */
#define NCSW_MIN(a,b) ((a) < (b) ? (a) : (b))
#define NCSW_MAX(a,b) ((a) > (b) ? (a) : (b))
#define IN_RANGE(min,val,max) ((min)<=(val) && (val)<=(max))
#define ABS(a) ((a<0)?(a*-1):a)
#if !(defined(ARRAY_SIZE))
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#endif /* !defined(ARRAY_SIZE) */
/* possible alignments */
#define HALF_WORD_ALIGNMENT 2
#define WORD_ALIGNMENT 4
#define DOUBLE_WORD_ALIGNMENT 8
#define BURST_ALIGNMENT 32
#define HALF_WORD_ALIGNED 0x00000001
#define WORD_ALIGNED 0x00000003
#define DOUBLE_WORD_ALIGNED 0x00000007
#define BURST_ALIGNED 0x0000001f
#ifndef IS_ALIGNED
#define IS_ALIGNED(n,align) (!((uint32_t)(n) & (align - 1)))
#endif /* IS_ALIGNED */
#define LAST_BUF 1
#define FIRST_BUF 2
#define SINGLE_BUF (LAST_BUF | FIRST_BUF)
#define MIDDLE_BUF 4
#define ARRAY_END -1
#define ILLEGAL_BASE (~0)
#define BUF_POSITION(first, last) state[(!!(last))<<1 | !!(first)]
#define DECLARE_POSITION static uint8_t state[4] = { (uint8_t)MIDDLE_BUF, (uint8_t)FIRST_BUF, (uint8_t)LAST_BUF, (uint8_t)SINGLE_BUF };
/**************************************************************************//**
@Description Timers operation mode
*//***************************************************************************/
typedef enum e_TimerMode
{
e_TIMER_MODE_INVALID = 0,
e_TIMER_MODE_FREE_RUN, /**< Free run - counter continues to increase
after reaching the reference value. */
e_TIMER_MODE_PERIODIC, /**< Periodic - counter restarts counting from 0
after reaching the reference value. */
e_TIMER_MODE_SINGLE /**< Single (one-shot) - counter stops counting
after reaching the reference value. */
} e_TimerMode;
/**************************************************************************//**
@Description Enumeration (bit flags) of communication modes (Transmit,
receive or both).
*//***************************************************************************/
typedef enum e_CommMode
{
e_COMM_MODE_NONE = 0, /**< No transmit/receive communication */
e_COMM_MODE_RX = 1, /**< Only receive communication */
e_COMM_MODE_TX = 2, /**< Only transmit communication */
e_COMM_MODE_RX_AND_TX = 3 /**< Both transmit and receive communication */
} e_CommMode;
/**************************************************************************//**
@Description General Diagnostic Mode
*//***************************************************************************/
typedef enum e_DiagMode
{
e_DIAG_MODE_NONE = 0, /**< Normal operation; no diagnostic mode */
e_DIAG_MODE_CTRL_LOOPBACK, /**< Loopback in the controller */
e_DIAG_MODE_CHIP_LOOPBACK, /**< Loopback in the chip but not in the
controller; e.g. IO-pins, SerDes, etc. */
e_DIAG_MODE_PHY_LOOPBACK, /**< Loopback in the external PHY */
e_DIAG_MODE_EXT_LOOPBACK, /**< Loopback in the external line (beyond the PHY) */
e_DIAG_MODE_CTRL_ECHO, /**< Echo incoming data by the controller */
e_DIAG_MODE_PHY_ECHO /**< Echo incoming data by the PHY */
} e_DiagMode;
/**************************************************************************//**
@Description Possible RxStore callback responses.
*//***************************************************************************/
typedef enum e_RxStoreResponse
{
e_RX_STORE_RESPONSE_PAUSE /**< Pause invoking callback with received data;
in polling mode, start again invoking callback
only next time user invokes the receive routine;
in interrupt mode, start again invoking callback
only next time a receive event triggers an interrupt;
in all cases, received data that are pending are not
lost, rather, their processing is temporarily deferred;
in all cases, received data are processed in the order
in which they were received. */
, e_RX_STORE_RESPONSE_CONTINUE /**< Continue invoking callback with received data. */
} e_RxStoreResponse;
/**************************************************************************//**
@Description General Handle
*//***************************************************************************/
typedef void * t_Handle; /**< handle, used as object's descriptor */
/**************************************************************************//**
@Description MUTEX type
*//***************************************************************************/
typedef uint32_t t_Mutex;
/**************************************************************************//**
@Description Error Code.
The high word of the error code is the code of the software
module (driver). The low word is the error type (e_ErrorType).
To get the values from the error code, use GET_ERROR_TYPE()
and GET_ERROR_MODULE().
*//***************************************************************************/
typedef uint32_t t_Error;
/**************************************************************************//**
@Description General prototype of interrupt service routine (ISR).
@Param[in] handle - Optional handle of the module handling the interrupt.
@Return None
*//***************************************************************************/
typedef void (t_Isr)(t_Handle handle);
/**************************************************************************//**
@Anchor mem_attr
@Collection Memory Attributes
Various attributes of memory partitions. These values may be
or'ed together to create a mask of all memory attributes.
@{
*//***************************************************************************/
#define MEMORY_ATTR_CACHEABLE 0x00000001
/**< Memory is cacheable */
#define MEMORY_ATTR_QE_2ND_BUS_ACCESS 0x00000002
/**< Memory can be accessed by QUICC Engine
through its secondary bus interface */
/* @} */
/**************************************************************************//**
@Function t_GetBufFunction
@Description User callback function called by driver to get data buffer.
User provides this function. Driver invokes it.
@Param[in] h_BufferPool - A handle to buffer pool manager
@Param[out] p_BufContextHandle - Returns the user's private context that
should be associated with the buffer
@Return Pointer to data buffer, NULL if error
*//***************************************************************************/
typedef uint8_t * (t_GetBufFunction)(t_Handle h_BufferPool,
t_Handle *p_BufContextHandle);
/**************************************************************************//**
@Function t_PutBufFunction
@Description User callback function called by driver to return data buffer.
User provides this function. Driver invokes it.
@Param[in] h_BufferPool - A handle to buffer pool manager
@Param[in] p_Buffer - A pointer to buffer to return
@Param[in] h_BufContext - The user's private context associated with
the returned buffer
@Return E_OK on success; Error code otherwise
*//***************************************************************************/
typedef t_Error (t_PutBufFunction)(t_Handle h_BufferPool,
uint8_t *p_Buffer,
t_Handle h_BufContext);
/**************************************************************************//**
@Function t_PhysToVirt
@Description Translates a physical address to the matching virtual address.
@Param[in] addr - The physical address to translate.
@Return Virtual address.
*//***************************************************************************/
typedef void * t_PhysToVirt(physAddress_t addr);
/**************************************************************************//**
@Function t_VirtToPhys
@Description Translates a virtual address to the matching physical address.
@Param[in] addr - The virtual address to translate.
@Return Physical address.
*//***************************************************************************/
typedef physAddress_t t_VirtToPhys(void *addr);
/**************************************************************************//**
@Description Buffer Pool Information Structure.
*//***************************************************************************/
typedef struct t_BufferPoolInfo
{
t_Handle h_BufferPool; /**< A handle to the buffer pool manager */
t_GetBufFunction *f_GetBuf; /**< User callback to get a free buffer */
t_PutBufFunction *f_PutBuf; /**< User callback to return a buffer */
uint16_t bufferSize; /**< Buffer size (in bytes) */
t_PhysToVirt *f_PhysToVirt; /**< User callback to translate pool buffers
physical addresses to virtual addresses */
t_VirtToPhys *f_VirtToPhys; /**< User callback to translate pool buffers
virtual addresses to physical addresses */
} t_BufferPoolInfo;
/**************************************************************************//**
@Description User callback function called by driver when transmit completed.
User provides this function. Driver invokes it.
@Param[in] h_App - Application's handle, as was provided to the
driver by the user
@Param[in] queueId - Transmit queue ID
@Param[in] p_Data - Pointer to the data buffer
@Param[in] h_BufContext - The user's private context associated with
the given data buffer
@Param[in] status - Transmit status and errors
@Param[in] flags - Driver-dependent information
*//***************************************************************************/
typedef void (t_TxConfFunction)(t_Handle h_App,
uint32_t queueId,
uint8_t *p_Data,
t_Handle h_BufContext,
uint16_t status,
uint32_t flags);
/**************************************************************************//**
@Description User callback function called by driver with receive data.
User provides this function. Driver invokes it.
@Param[in] h_App - Application's handle, as was provided to the
driver by the user
@Param[in] queueId - Receive queue ID
@Param[in] p_Data - Pointer to the buffer with received data
@Param[in] h_BufContext - The user's private context associated with
the given data buffer
@Param[in] length - Length of received data
@Param[in] status - Receive status and errors
@Param[in] position - Position of buffer in frame
@Param[in] flags - Driver-dependent information
@Retval e_RX_STORE_RESPONSE_CONTINUE - order the driver to continue Rx
operation for all ready data.
@Retval e_RX_STORE_RESPONSE_PAUSE - order the driver to stop Rx operation.
*//***************************************************************************/
typedef e_RxStoreResponse (t_RxStoreFunction)(t_Handle h_App,
uint32_t queueId,
uint8_t *p_Data,
t_Handle h_BufContext,
uint32_t length,
uint16_t status,
uint8_t position,
uint32_t flags);
#endif /* __NCSW_EXT_H */

388
sys/contrib/ncsw/inc/net_ext.h Normal file
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@ -0,0 +1,388 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File net_ext.h
@Description This file contains common and general netcomm headers definitions.
*//***************************************************************************/
#ifndef __NET_EXT_H
#define __NET_EXT_H
#include "std_ext.h"
typedef uint8_t headerFieldPpp_t;
#define NET_HEADER_FIELD_PPP_PID (1)
#define NET_HEADER_FIELD_PPP_COMPRESSED (NET_HEADER_FIELD_PPP_PID << 1)
#define NET_HEADER_FIELD_PPP_ALL_FIELDS ((NET_HEADER_FIELD_PPP_PID << 2) - 1)
typedef uint8_t headerFieldPppoe_t;
#define NET_HEADER_FIELD_PPPoE_VER (1)
#define NET_HEADER_FIELD_PPPoE_TYPE (NET_HEADER_FIELD_PPPoE_VER << 1)
#define NET_HEADER_FIELD_PPPoE_CODE (NET_HEADER_FIELD_PPPoE_VER << 2)
#define NET_HEADER_FIELD_PPPoE_SID (NET_HEADER_FIELD_PPPoE_VER << 3)
#define NET_HEADER_FIELD_PPPoE_LEN (NET_HEADER_FIELD_PPPoE_VER << 4)
#define NET_HEADER_FIELD_PPPoE_SESSION (NET_HEADER_FIELD_PPPoE_VER << 5)
#define NET_HEADER_FIELD_PPPoE_PID (NET_HEADER_FIELD_PPPoE_VER << 6)
#define NET_HEADER_FIELD_PPPoE_ALL_FIELDS ((NET_HEADER_FIELD_PPPoE_VER << 7) - 1)
#define NET_HEADER_FIELD_PPPMUX_PID (1)
#define NET_HEADER_FIELD_PPPMUX_CKSUM (NET_HEADER_FIELD_PPPMUX_PID << 1)
#define NET_HEADER_FIELD_PPPMUX_COMPRESSED (NET_HEADER_FIELD_PPPMUX_PID << 2)
#define NET_HEADER_FIELD_PPPMUX_ALL_FIELDS ((NET_HEADER_FIELD_PPPMUX_PID << 3) - 1)
#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF (1)
#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_LXT (NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 1)
#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_LEN (NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 2)
#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_PID (NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 3)
#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_USE_PID (NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 4)
#define NET_HEADER_FIELD_PPPMUX_SUBFRAME_ALL_FIELDS ((NET_HEADER_FIELD_PPPMUX_SUBFRAME_PFF << 5) - 1)
typedef uint8_t headerFieldEth_t;
#define NET_HEADER_FIELD_ETH_DA (1)
#define NET_HEADER_FIELD_ETH_SA (NET_HEADER_FIELD_ETH_DA << 1)
#define NET_HEADER_FIELD_ETH_LENGTH (NET_HEADER_FIELD_ETH_DA << 2)
#define NET_HEADER_FIELD_ETH_TYPE (NET_HEADER_FIELD_ETH_DA << 3)
#define NET_HEADER_FIELD_ETH_FINAL_CKSUM (NET_HEADER_FIELD_ETH_DA << 4)
#define NET_HEADER_FIELD_ETH_PADDING (NET_HEADER_FIELD_ETH_DA << 5)
#define NET_HEADER_FIELD_ETH_ALL_FIELDS ((NET_HEADER_FIELD_ETH_DA << 6) - 1)
typedef uint16_t headerFieldIpv4_t;
#define NET_HEADER_FIELD_IPv4_VER (1)
#define NET_HEADER_FIELD_IPv4_HDR_LEN (NET_HEADER_FIELD_IPv4_VER << 1)
#define NET_HEADER_FIELD_IPv4_TOS (NET_HEADER_FIELD_IPv4_VER << 2)
#define NET_HEADER_FIELD_IPv4_TOTAL_LEN (NET_HEADER_FIELD_IPv4_VER << 3)
#define NET_HEADER_FIELD_IPv4_ID (NET_HEADER_FIELD_IPv4_VER << 4)
#define NET_HEADER_FIELD_IPv4_FLAG_D (NET_HEADER_FIELD_IPv4_VER << 5)
#define NET_HEADER_FIELD_IPv4_FLAG_M (NET_HEADER_FIELD_IPv4_VER << 6)
#define NET_HEADER_FIELD_IPv4_OFFSET (NET_HEADER_FIELD_IPv4_VER << 7)
#define NET_HEADER_FIELD_IPv4_TTL (NET_HEADER_FIELD_IPv4_VER << 8)
#define NET_HEADER_FIELD_IPv4_PROTO (NET_HEADER_FIELD_IPv4_VER << 9)
#define NET_HEADER_FIELD_IPv4_CKSUM (NET_HEADER_FIELD_IPv4_VER << 10)
#define NET_HEADER_FIELD_IPv4_SRC_IP (NET_HEADER_FIELD_IPv4_VER << 11)
#define NET_HEADER_FIELD_IPv4_DST_IP (NET_HEADER_FIELD_IPv4_VER << 12)
#define NET_HEADER_FIELD_IPv4_OPTS (NET_HEADER_FIELD_IPv4_VER << 13)
#define NET_HEADER_FIELD_IPv4_OPTS_COUNT (NET_HEADER_FIELD_IPv4_VER << 14)
#define NET_HEADER_FIELD_IPv4_ALL_FIELDS ((NET_HEADER_FIELD_IPv4_VER << 15) - 1)
typedef uint8_t headerFieldIpv6_t;
#define NET_HEADER_FIELD_IPv6_VER (1)
#define NET_HEADER_FIELD_IPv6_TC (NET_HEADER_FIELD_IPv6_VER << 1)
#define NET_HEADER_FIELD_IPv6_SRC_IP (NET_HEADER_FIELD_IPv6_VER << 2)
#define NET_HEADER_FIELD_IPv6_DST_IP (NET_HEADER_FIELD_IPv6_VER << 3)
#define NET_HEADER_FIELD_IPv6_NEXT_HDR (NET_HEADER_FIELD_IPv6_VER << 4)
#define NET_HEADER_FIELD_IPv6_FL (NET_HEADER_FIELD_IPv6_VER << 5)
#define NET_HEADER_FIELD_IPv6_HOP_LIMIT (NET_HEADER_FIELD_IPv6_VER << 6)
#define NET_HEADER_FIELD_IPv6_ALL_FIELDS ((NET_HEADER_FIELD_IPv6_VER << 7) - 1)
#define NET_HEADER_FIELD_ICMP_TYPE (1)
#define NET_HEADER_FIELD_ICMP_CODE (NET_HEADER_FIELD_ICMP_TYPE << 1)
#define NET_HEADER_FIELD_ICMP_CKSUM (NET_HEADER_FIELD_ICMP_TYPE << 2)
#define NET_HEADER_FIELD_ICMP_ID (NET_HEADER_FIELD_ICMP_TYPE << 3)
#define NET_HEADER_FIELD_ICMP_SQ_NUM (NET_HEADER_FIELD_ICMP_TYPE << 4)
#define NET_HEADER_FIELD_ICMP_ALL_FIELDS ((NET_HEADER_FIELD_ICMP_TYPE << 5) - 1)
#define NET_HEADER_FIELD_IGMP_VERSION (1)
#define NET_HEADER_FIELD_IGMP_TYPE (NET_HEADER_FIELD_IGMP_VERSION << 1)
#define NET_HEADER_FIELD_IGMP_CKSUM (NET_HEADER_FIELD_IGMP_VERSION << 2)
#define NET_HEADER_FIELD_IGMP_DATA (NET_HEADER_FIELD_IGMP_VERSION << 3)
#define NET_HEADER_FIELD_IGMP_ALL_FIELDS ((NET_HEADER_FIELD_IGMP_VERSION << 4) - 1)
typedef uint16_t headerFieldTcp_t;
#define NET_HEADER_FIELD_TCP_PORT_SRC (1)
#define NET_HEADER_FIELD_TCP_PORT_DST (NET_HEADER_FIELD_TCP_PORT_SRC << 1)
#define NET_HEADER_FIELD_TCP_SEQ (NET_HEADER_FIELD_TCP_PORT_SRC << 2)
#define NET_HEADER_FIELD_TCP_ACK (NET_HEADER_FIELD_TCP_PORT_SRC << 3)
#define NET_HEADER_FIELD_TCP_OFFSET (NET_HEADER_FIELD_TCP_PORT_SRC << 4)
#define NET_HEADER_FIELD_TCP_FLAGS (NET_HEADER_FIELD_TCP_PORT_SRC << 5)
#define NET_HEADER_FIELD_TCP_WINDOW (NET_HEADER_FIELD_TCP_PORT_SRC << 6)
#define NET_HEADER_FIELD_TCP_CKSUM (NET_HEADER_FIELD_TCP_PORT_SRC << 7)
#define NET_HEADER_FIELD_TCP_URGPTR (NET_HEADER_FIELD_TCP_PORT_SRC << 8)
#define NET_HEADER_FIELD_TCP_OPTS (NET_HEADER_FIELD_TCP_PORT_SRC << 9)
#define NET_HEADER_FIELD_TCP_OPTS_COUNT (NET_HEADER_FIELD_TCP_PORT_SRC << 10)
#define NET_HEADER_FIELD_TCP_ALL_FIELDS ((NET_HEADER_FIELD_TCP_PORT_SRC << 11) - 1)
typedef uint8_t headerFieldSctp_t;
#define NET_HEADER_FIELD_SCTP_PORT_SRC (1)
#define NET_HEADER_FIELD_SCTP_PORT_DST (NET_HEADER_FIELD_SCTP_PORT_SRC << 1)
#define NET_HEADER_FIELD_SCTP_VER_TAG (NET_HEADER_FIELD_SCTP_PORT_SRC << 2)
#define NET_HEADER_FIELD_SCTP_CKSUM (NET_HEADER_FIELD_SCTP_PORT_SRC << 3)
#define NET_HEADER_FIELD_SCTP_ALL_FIELDS ((NET_HEADER_FIELD_SCTP_PORT_SRC << 4) - 1)
typedef uint8_t headerFieldDccp_t;
#define NET_HEADER_FIELD_DCCP_PORT_SRC (1)
#define NET_HEADER_FIELD_DCCP_PORT_DST (NET_HEADER_FIELD_DCCP_PORT_SRC << 1)
#define NET_HEADER_FIELD_DCCP_ALL_FIELDS ((NET_HEADER_FIELD_DCCP_PORT_SRC << 2) - 1)
typedef uint8_t headerFieldUdp_t;
#define NET_HEADER_FIELD_UDP_PORT_SRC (1)
#define NET_HEADER_FIELD_UDP_PORT_DST (NET_HEADER_FIELD_UDP_PORT_SRC << 1)
#define NET_HEADER_FIELD_UDP_LEN (NET_HEADER_FIELD_UDP_PORT_SRC << 2)
#define NET_HEADER_FIELD_UDP_CKSUM (NET_HEADER_FIELD_UDP_PORT_SRC << 3)
#define NET_HEADER_FIELD_UDP_ALL_FIELDS ((NET_HEADER_FIELD_UDP_PORT_SRC << 4) - 1)
typedef uint8_t headerFieldUdpEncapEsp_t;
#define NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC (1)
#define NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_DST (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 1)
#define NET_HEADER_FIELD_UDP_ENCAP_ESP_LEN (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 2)
#define NET_HEADER_FIELD_UDP_ENCAP_ESP_CKSUM (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 3)
#define NET_HEADER_FIELD_UDP_ENCAP_ESP_SPI (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 4)
#define NET_HEADER_FIELD_UDP_ENCAP_ESP_SEQUENCE_NUM (NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 5)
#define NET_HEADER_FIELD_UDP_ENCAP_ESP_ALL_FIELDS ((NET_HEADER_FIELD_UDP_ENCAP_ESP_PORT_SRC << 6) - 1)
#define NET_HEADER_FIELD_IPHC_CID (1)
#define NET_HEADER_FIELD_IPHC_CID_TYPE (NET_HEADER_FIELD_IPHC_CID << 1)
#define NET_HEADER_FIELD_IPHC_HCINDEX (NET_HEADER_FIELD_IPHC_CID << 2)
#define NET_HEADER_FIELD_IPHC_GEN (NET_HEADER_FIELD_IPHC_CID << 3)
#define NET_HEADER_FIELD_IPHC_D_BIT (NET_HEADER_FIELD_IPHC_CID << 4)
#define NET_HEADER_FIELD_IPHC_ALL_FIELDS ((NET_HEADER_FIELD_IPHC_CID << 5) - 1)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE (1)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_FLAGS (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 1)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_LENGTH (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 2)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_TSN (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 3)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_STREAM_ID (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 4)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_STREAM_SQN (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 5)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_PAYLOAD_PID (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 6)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_UNORDERED (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 7)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_BEGGINING (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 8)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_END (NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 9)
#define NET_HEADER_FIELD_SCTP_CHUNK_DATA_ALL_FIELDS ((NET_HEADER_FIELD_SCTP_CHUNK_DATA_TYPE << 10) - 1)
#define NET_HEADER_FIELD_L2TPv2_TYPE_BIT (1)
#define NET_HEADER_FIELD_L2TPv2_LENGTH_BIT (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 1)
#define NET_HEADER_FIELD_L2TPv2_SEQUENCE_BIT (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 2)
#define NET_HEADER_FIELD_L2TPv2_OFFSET_BIT (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 3)
#define NET_HEADER_FIELD_L2TPv2_PRIORITY_BIT (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 4)
#define NET_HEADER_FIELD_L2TPv2_VERSION (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 5)
#define NET_HEADER_FIELD_L2TPv2_LEN (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 6)
#define NET_HEADER_FIELD_L2TPv2_TUNNEL_ID (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 7)
#define NET_HEADER_FIELD_L2TPv2_SESSION_ID (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 8)
#define NET_HEADER_FIELD_L2TPv2_NS (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 9)
#define NET_HEADER_FIELD_L2TPv2_NR (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 10)
#define NET_HEADER_FIELD_L2TPv2_OFFSET_SIZE (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 11)
#define NET_HEADER_FIELD_L2TPv2_FIRST_BYTE (NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 12)
#define NET_HEADER_FIELD_L2TPv2_ALL_FIELDS ((NET_HEADER_FIELD_L2TPv2_TYPE_BIT << 13) - 1)
#define NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT (1)
#define NET_HEADER_FIELD_L2TPv3_CTRL_LENGTH_BIT (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 1)
#define NET_HEADER_FIELD_L2TPv3_CTRL_SEQUENCE_BIT (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 2)
#define NET_HEADER_FIELD_L2TPv3_CTRL_VERSION (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 3)
#define NET_HEADER_FIELD_L2TPv3_CTRL_LENGTH (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 4)
#define NET_HEADER_FIELD_L2TPv3_CTRL_CONTROL (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 5)
#define NET_HEADER_FIELD_L2TPv3_CTRL_SENT (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 6)
#define NET_HEADER_FIELD_L2TPv3_CTRL_RECV (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 7)
#define NET_HEADER_FIELD_L2TPv3_CTRL_FIRST_BYTE (NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 8)
#define NET_HEADER_FIELD_L2TPv3_CTRL_ALL_FIELDS ((NET_HEADER_FIELD_L2TPv3_CTRL_TYPE_BIT << 9) - 1)
#define NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT (1)
#define NET_HEADER_FIELD_L2TPv3_SESS_VERSION (NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 1)
#define NET_HEADER_FIELD_L2TPv3_SESS_ID (NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 2)
#define NET_HEADER_FIELD_L2TPv3_SESS_COOKIE (NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 3)
#define NET_HEADER_FIELD_L2TPv3_SESS_ALL_FIELDS ((NET_HEADER_FIELD_L2TPv3_SESS_TYPE_BIT << 4) - 1)
typedef uint8_t headerFieldVlan_t;
#define NET_HEADER_FIELD_VLAN_VPRI (1)
#define NET_HEADER_FIELD_VLAN_CFI (NET_HEADER_FIELD_VLAN_VPRI << 1)
#define NET_HEADER_FIELD_VLAN_VID (NET_HEADER_FIELD_VLAN_VPRI << 2)
#define NET_HEADER_FIELD_VLAN_LENGTH (NET_HEADER_FIELD_VLAN_VPRI << 3)
#define NET_HEADER_FIELD_VLAN_TYPE (NET_HEADER_FIELD_VLAN_VPRI << 4)
#define NET_HEADER_FIELD_VLAN_ALL_FIELDS ((NET_HEADER_FIELD_VLAN_VPRI << 5) - 1)
#define NET_HEADER_FIELD_VLAN_TCI (NET_HEADER_FIELD_VLAN_VPRI | \
NET_HEADER_FIELD_VLAN_CFI | \
NET_HEADER_FIELD_VLAN_VID)
typedef uint8_t headerFieldLlc_t;
#define NET_HEADER_FIELD_LLC_DSAP (1)
#define NET_HEADER_FIELD_LLC_SSAP (NET_HEADER_FIELD_LLC_DSAP << 1)
#define NET_HEADER_FIELD_LLC_CTRL (NET_HEADER_FIELD_LLC_DSAP << 2)
#define NET_HEADER_FIELD_LLC_ALL_FIELDS ((NET_HEADER_FIELD_LLC_DSAP << 3) - 1)
#define NET_HEADER_FIELD_NLPID_NLPID (1)
#define NET_HEADER_FIELD_NLPID_ALL_FIELDS ((NET_HEADER_FIELD_NLPID_NLPID << 1) - 1)
typedef uint8_t headerFieldSnap_t;
#define NET_HEADER_FIELD_SNAP_OUI (1)
#define NET_HEADER_FIELD_SNAP_PID (NET_HEADER_FIELD_SNAP_OUI << 1)
#define NET_HEADER_FIELD_SNAP_ALL_FIELDS ((NET_HEADER_FIELD_SNAP_OUI << 2) - 1)
typedef uint8_t headerFieldLlcSnap_t;
#define NET_HEADER_FIELD_LLC_SNAP_TYPE (1)
#define NET_HEADER_FIELD_LLC_SNAP_ALL_FIELDS ((NET_HEADER_FIELD_LLC_SNAP_TYPE << 1) - 1)
#define NET_HEADER_FIELD_ARP_HTYPE (1)
#define NET_HEADER_FIELD_ARP_PTYPE (NET_HEADER_FIELD_ARP_HTYPE << 1)
#define NET_HEADER_FIELD_ARP_HLEN (NET_HEADER_FIELD_ARP_HTYPE << 2)
#define NET_HEADER_FIELD_ARP_PLEN (NET_HEADER_FIELD_ARP_HTYPE << 3)
#define NET_HEADER_FIELD_ARP_OPER (NET_HEADER_FIELD_ARP_HTYPE << 4)
#define NET_HEADER_FIELD_ARP_SHA (NET_HEADER_FIELD_ARP_HTYPE << 5)
#define NET_HEADER_FIELD_ARP_SPA (NET_HEADER_FIELD_ARP_HTYPE << 6)
#define NET_HEADER_FIELD_ARP_THA (NET_HEADER_FIELD_ARP_HTYPE << 7)
#define NET_HEADER_FIELD_ARP_TPA (NET_HEADER_FIELD_ARP_HTYPE << 8)
#define NET_HEADER_FIELD_ARP_ALL_FIELDS ((NET_HEADER_FIELD_ARP_HTYPE << 9) - 1)
#define NET_HEADER_FIELD_RFC2684_LLC (1)
#define NET_HEADER_FIELD_RFC2684_NLPID (NET_HEADER_FIELD_RFC2684_LLC << 1)
#define NET_HEADER_FIELD_RFC2684_OUI (NET_HEADER_FIELD_RFC2684_LLC << 2)
#define NET_HEADER_FIELD_RFC2684_PID (NET_HEADER_FIELD_RFC2684_LLC << 3)
#define NET_HEADER_FIELD_RFC2684_VPN_OUI (NET_HEADER_FIELD_RFC2684_LLC << 4)
#define NET_HEADER_FIELD_RFC2684_VPN_IDX (NET_HEADER_FIELD_RFC2684_LLC << 5)
#define NET_HEADER_FIELD_RFC2684_ALL_FIELDS ((NET_HEADER_FIELD_RFC2684_LLC << 6) - 1)
#define NET_HEADER_FIELD_USER_DEFINED_SRCPORT (1)
#define NET_HEADER_FIELD_USER_DEFINED_PCDID (NET_HEADER_FIELD_USER_DEFINED_SRCPORT << 1)
#define NET_HEADER_FIELD_USER_DEFINED_ALL_FIELDS ((NET_HEADER_FIELD_USER_DEFINED_SRCPORT << 2) - 1)
#define NET_HEADER_FIELD_PAYLOAD_BUFFER (1)
#define NET_HEADER_FIELD_PAYLOAD_SIZE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 1)
#define NET_HEADER_FIELD_MAX_FRM_SIZE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 2)
#define NET_HEADER_FIELD_MIN_FRM_SIZE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 3)
#define NET_HEADER_FIELD_PAYLOAD_TYPE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 4)
#define NET_HEADER_FIELD_FRAME_SIZE (NET_HEADER_FIELD_PAYLOAD_BUFFER << 5)
#define NET_HEADER_FIELD_PAYLOAD_ALL_FIELDS ((NET_HEADER_FIELD_PAYLOAD_BUFFER << 6) - 1)
typedef uint8_t headerFieldGre_t;
#define NET_HEADER_FIELD_GRE_TYPE (1)
#define NET_HEADER_FIELD_GRE_ALL_FIELDS ((NET_HEADER_FIELD_GRE_TYPE << 1) - 1)
typedef uint8_t headerFieldMinencap_t;
#define NET_HEADER_FIELD_MINENCAP_SRC_IP (1)
#define NET_HEADER_FIELD_MINENCAP_DST_IP (NET_HEADER_FIELD_MINENCAP_SRC_IP << 1)
#define NET_HEADER_FIELD_MINENCAP_TYPE (NET_HEADER_FIELD_MINENCAP_SRC_IP << 2)
#define NET_HEADER_FIELD_MINENCAP_ALL_FIELDS ((NET_HEADER_FIELD_MINENCAP_SRC_IP << 3) - 1)
typedef uint8_t headerFieldIpsecAh_t;
#define NET_HEADER_FIELD_IPSEC_AH_SPI (1)
#define NET_HEADER_FIELD_IPSEC_AH_NH (NET_HEADER_FIELD_IPSEC_AH_SPI << 1)
#define NET_HEADER_FIELD_IPSEC_AH_ALL_FIELDS ((NET_HEADER_FIELD_IPSEC_AH_SPI << 2) - 1)
typedef uint8_t headerFieldIpsecEsp_t;
#define NET_HEADER_FIELD_IPSEC_ESP_SPI (1)
#define NET_HEADER_FIELD_IPSEC_ESP_SEQUENCE_NUM (NET_HEADER_FIELD_IPSEC_ESP_SPI << 1)
#define NET_HEADER_FIELD_IPSEC_ESP_ALL_FIELDS ((NET_HEADER_FIELD_IPSEC_ESP_SPI << 2) - 1)
typedef uint8_t headerFieldMpls_t;
#define NET_HEADER_FIELD_MPLS_LABEL_STACK (1)
#define NET_HEADER_FIELD_MPLS_LABEL_STACK_ALL_FIELDS ((NET_HEADER_FIELD_MPLS_LABEL_STACK << 1) - 1)
typedef uint8_t headerFieldMacsec_t;
#define NET_HEADER_FIELD_MACSEC_SECTAG (1)
#define NET_HEADER_FIELD_MACSEC_ALL_FIELDS ((NET_HEADER_FIELD_MACSEC_SECTAG << 1) - 1)
typedef enum {
HEADER_TYPE_NONE = 0,
HEADER_TYPE_PAYLOAD,
HEADER_TYPE_ETH,
HEADER_TYPE_VLAN,
HEADER_TYPE_IPv4,
HEADER_TYPE_IPv6,
HEADER_TYPE_TCP,
HEADER_TYPE_UDP,
HEADER_TYPE_IPHC,
HEADER_TYPE_SCTP,
HEADER_TYPE_SCTP_CHUNK_DATA,
HEADER_TYPE_PPPoE,
HEADER_TYPE_PPP,
HEADER_TYPE_PPPMUX,
HEADER_TYPE_PPPMUX_SUBFRAME,
HEADER_TYPE_L2TPv2,
HEADER_TYPE_L2TPv3_CTRL,
HEADER_TYPE_L2TPv3_SESS,
HEADER_TYPE_LLC,
HEADER_TYPE_LLC_SNAP,
HEADER_TYPE_NLPID,
HEADER_TYPE_SNAP,
HEADER_TYPE_MPLS,
HEADER_TYPE_IPSEC_AH,
HEADER_TYPE_IPSEC_ESP,
HEADER_TYPE_UDP_ENCAP_ESP, /* RFC 3948 */
HEADER_TYPE_MACSEC,
HEADER_TYPE_GRE,
HEADER_TYPE_MINENCAP,
HEADER_TYPE_DCCP,
HEADER_TYPE_ICMP,
HEADER_TYPE_IGMP,
HEADER_TYPE_ARP,
HEADER_TYPE_CAPWAP,
HEADER_TYPE_CAPWAP_DTLS,
HEADER_TYPE_RFC2684,
HEADER_TYPE_USER_DEFINED_L2,
HEADER_TYPE_USER_DEFINED_L3,
HEADER_TYPE_USER_DEFINED_L4,
HEADER_TYPE_USER_DEFINED_SHIM1,
HEADER_TYPE_USER_DEFINED_SHIM2,
MAX_HEADER_TYPE_COUNT
} e_NetHeaderType;
#endif /* __NET_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File std_ext.h
@Description General Standard Definitions
*//***************************************************************************/
#ifndef __STD_EXT_H
#define __STD_EXT_H
#include "types_ext.h"
#include "ncsw_ext.h"
#endif /* __STD_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __STDARG_EXT_H
#define __STDARG_EXT_H
#if defined(NCSW_LINUX) && defined(__KERNEL__)
#include <stdarg.h>
#elif defined(NCSW_FREEBSD)
#include <sys/param.h>
#include <sys/kernel.h>
#include <machine/stdarg.h>
#else
#include <stdarg.h>
#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */
#include "std_ext.h"
#endif /* __STDARG_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __STDLIB_EXT_H
#define __STDLIB_EXT_H
#if (defined(NCSW_LINUX)) && defined(__KERNEL__)
#include "stdarg_ext.h"
#include "std_ext.h"
/**
* strtoul - convert a string to an uint32_t
* @cp: The start of the string
* @endp: A pointer to the end of the parsed string will be placed here
* @base: The number base to use
*/
uint32_t strtoul(const char *cp,char **endp,uint32_t base);
/**
* strtol - convert a string to a int32_t
* @cp: The start of the string
* @endp: A pointer to the end of the parsed string will be placed here
* @base: The number base to use
*/
long strtol(const char *cp,char **endp,uint32_t base);
/**
* strtoull - convert a string to an uint64_t
* @cp: The start of the string
* @endp: A pointer to the end of the parsed string will be placed here
* @base: The number base to use
*/
uint64_t strtoull(const char *cp,char **endp,uint32_t base);
/**
* strtoll - convert a string to a int64 long
* @cp: The start of the string
* @endp: A pointer to the end of the parsed string will be placed here
* @base: The number base to use
*/
long long strtoll(const char *cp,char **endp,uint32_t base);
/**
* atoi - convert a character to a int
* @s: The start of the string
*/
int atoi(const char *s);
/**
* strnlen - Find the length of a length-limited string
* @s: The string to be sized
* @count: The maximum number of bytes to search
*/
size_t strnlen(const char * s, size_t count);
/**
* strlen - Find the length of a string
* @s: The string to be sized
*/
size_t strlen(const char * s);
/**
* strtok - Split a string into tokens
* @s: The string to be searched
* @ct: The characters to search for
*
* WARNING: strtok is deprecated, use strsep instead.
*/
char * strtok(char * s,const char * ct);
/**
* strncpy - Copy a length-limited, %NUL-terminated string
* @dest: Where to copy the string to
* @src: Where to copy the string from
* @count: The maximum number of bytes to copy
*
* Note that unlike userspace strncpy, this does not %NUL-pad the buffer.
* However, the result is not %NUL-terminated if the source exceeds
* @count bytes.
*/
char * strncpy(char * dest,const char *src,size_t count);
/**
* strcpy - Copy a %NUL terminated string
* @dest: Where to copy the string to
* @src: Where to copy the string from
*/
char * strcpy(char * dest,const char *src);
/**
* vsscanf - Unformat a buffer into a list of arguments
* @buf: input buffer
* @fmt: format of buffer
* @args: arguments
*/
int vsscanf(const char * buf, const char * fmt, va_list args);
/**
* vsnprintf - Format a string and place it in a buffer
* @buf: The buffer to place the result into
* @size: The size of the buffer, including the trailing null space
* @fmt: The format string to use
* @args: Arguments for the format string
*
* Call this function if you are already dealing with a va_list.
* You probably want snprintf instead.
*/
int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
/**
* vsprintf - Format a string and place it in a buffer
* @buf: The buffer to place the result into
* @fmt: The format string to use
* @args: Arguments for the format string
*
* Call this function if you are already dealing with a va_list.
* You probably want sprintf instead.
*/
int vsprintf(char *buf, const char *fmt, va_list args);
#elif defined(NCSW_FREEBSD)
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/libkern.h>
#else
#include <stdlib.h>
#include <stdio.h>
#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */
#include "std_ext.h"
#endif /* __STDLIB_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __STRING_EXT_H
#define __STRING_EXT_H
#if defined(NCSW_LINUX) && defined(__KERNEL__)
#include <linux/kernel.h>
#include <linux/string.h>
extern char * strtok ( char * str, const char * delimiters );
#elif defined(__KERNEL__)
#include "linux/types.h"
#include "linux/posix_types.h"
#include "linux/string.h"
#elif defined(NCSW_FREEBSD)
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/libkern.h>
extern char *strtok(char *str, const char *delimiters);
#else
#include <string.h>
#endif /* defined(NCSW_LINUX) && defined(__KERNEL__) */
#include "std_ext.h"
#endif /* __STRING_EXT_H */

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/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File types_ext.h
@Description General types Standard Definitions
*//***************************************************************************/
#ifndef __TYPES_EXT_H
#define __TYPES_EXT_H
#if defined(NCSW_LINUX)
#include "types_linux.h"
#elif defined(NCSW_LINUX_USD)
#include "types_linux_usd.h"
#elif defined(NCSW_VXWORKS)
#include "types_vxworks.h"
#elif defined(__MWERKS__) && defined(__GNUC__) && defined(__cplusplus)
#include "types_bb_gpp.h"
#elif defined(__MWERKS__) && defined(__GNUC__)
#include "types_bb_gcc.h"
#elif defined(__ghs__)
#include "types_ghs.h"
#elif defined(NCSW_FREEBSD)
#include "types_freebsd.h"
#else
#include "types_dflt.h"
#endif /* defined (__ROCOO__) */
static __inline__ void TypesChecker(void)
{
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(push,1)
#endif /* defined(__MWERKS__) && ... */
#define MEM_MAP_START
_Packed struct strct {
__volatile__ int vi;
} _PackedType;
#define MEM_MAP_END
#if defined(__MWERKS__) && !defined(__GNUC__)
#pragma pack(pop)
#endif /* defined(__MWERKS__) && ... */
size_t size = 0;
bool tr = TRUE, fls = FALSE;
struct strct *p_Strct = NULL;
physAddress_t addr = 0x100;
tr = fls;
p_Strct = p_Strct;
size++;
if (tr) size++;
WRITE_UINT8(*((uint8_t*)((size_t)(addr))),
GET_UINT8(*((uint8_t*)((size_t)(addr)))));
WRITE_UINT8(*((uint8_t*)((size_t)(UINT8_MAX))),
GET_UINT8(*((uint8_t*)((size_t)(UINT8_MAX)))));
WRITE_UINT16(*((uint16_t*)((size_t)(UINT16_MAX))),
GET_UINT16(*((uint16_t*)((size_t)(UINT16_MAX)))));
WRITE_UINT32(*((uint32_t*)((size_t)(UINT32_MAX))),
GET_UINT32(*((uint32_t*)((size_t)(UINT32_MAX)))));
WRITE_UINT64(*((uint64_t*)((size_t)(UINT64_MAX))),
GET_UINT64(*((uint64_t*)((size_t)(UINT64_MAX)))));
WRITE_UINT8(*((uint8_t*)((size_t)(INT8_MAX))),
GET_UINT8(*((uint8_t*)((size_t)(INT8_MIN)))));
WRITE_UINT16(*((uint16_t*)((size_t)(INT16_MAX))),
GET_UINT16(*((uint16_t*)((size_t)(INT16_MIN)))));
WRITE_UINT32(*((uint32_t*)((size_t)(INT32_MAX))),
GET_UINT32(*((uint32_t*)((size_t)(INT32_MIN)))));
WRITE_UINT64(*((uint64_t*)((size_t)(INT64_MAX))),
GET_UINT64(*((uint64_t*)((size_t)(INT64_MIN)))));
}
#endif /* __TYPES_EXT_H */

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sys/contrib/ncsw/inc/types_freebsd.h Normal file
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/*-
* Copyright (c) 2011 Semihalf.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef TYPES_FREEBSD_H_
#define TYPES_FREEBSD_H_
#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/libkern.h>
#include <sys/stddef.h>
#include <sys/types.h>
#include <machine/pio.h>
#if !defined(__bool_true_false_are_defined)
typedef boolean_t bool;
#endif
#define TRUE 1
#define FALSE 0
typedef vm_paddr_t physAddress_t;
#define _Packed
#define _PackedType __attribute__ ((packed))
/**
* Accessor defines.
* TODO: These are only stubs and have to be redefined (use bus_space
* facilities).
*/
#define GET_UINT32(arg) in32(&(arg))
#define GET_UINT64(arg) in64(&(arg))
#define _WRITE_UINT32(arg, data) out32(&(arg), (data))
#define _WRITE_UINT64(arg, data) out64(&(arg), (data))
#ifndef QE_32_BIT_ACCESS_RESTRICTION
#define GET_UINT8(arg) in8(&(arg))
#define GET_UINT16(arg) in16(&(arg))
#define _WRITE_UINT8(arg, data) out8(&(arg), (data))
#define _WRITE_UINT16(arg, data) out16(&(arg), (data))
#else /* QE_32_BIT_ACCESS_RESTRICTION */
#define QE_32_BIT_ADDR(_arg) (uint32_t)((uint32_t)&(_arg) & 0xFFFFFFFC)
#define QE_32_BIT_SHIFT8(__arg) (uint32_t)((3 - ((uint32_t)&(__arg) & 0x3)) * 8)
#define QE_32_BIT_SHIFT16(__arg) (uint32_t)((2 - ((uint32_t)&(__arg) & 0x3)) * 8)
#define GET_UINT8(arg) (uint8_t)(in32(QE_32_BIT_ADDR(arg)) >> QE_32_BIT_SHIFT8(arg))
#define GET_UINT16(arg) (uint16_t)(in32(QE_32_BIT_ADDR(arg)) >> QE_32_BIT_SHIFT16(arg))
#define _WRITE_UINT8(arg, data) \
do \
{ \
uint32_t addr = QE_32_BIT_ADDR(arg); \
uint32_t shift = QE_32_BIT_SHIFT8(arg); \
uint32_t tmp = in32(addr); \
tmp = (uint32_t)((tmp & ~(0x000000FF << shift)) | ((uint32_t)(data & 0x000000FF) << shift)); \
out32(addr, tmp); \
} while (0)
#define _WRITE_UINT16(arg, data) \
do \
{ \
uint32_t addr = QE_32_BIT_ADDR(arg); \
uint32_t shift = QE_32_BIT_SHIFT16(arg); \
uint32_t tmp = in32(addr); \
tmp = (uint32_t)((tmp & ~(0x0000FFFF << shift)) | ((uint32_t)(data & 0x0000FFFF) << shift)); \
out32(addr, tmp); \
} while (0)
#endif /* QE_32_BIT_ACCESS_RESTRICTION */
#define WRITE_UINT8 _WRITE_UINT8
#define WRITE_UINT16 _WRITE_UINT16
#define WRITE_UINT32 _WRITE_UINT32
#define WRITE_UINT64 _WRITE_UINT64
#endif /* TYPES_FREEBSD_H_ */

938
sys/contrib/ncsw/inc/xx_ext.h Normal file
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@ -0,0 +1,938 @@
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**************************************************************************//**
@File xx_ext.h
@Description Prototypes, externals and typedefs for system-supplied
(external) routines
*//***************************************************************************/
#ifndef __XX_EXT_H
#define __XX_EXT_H
#include "std_ext.h"
#include "part_ext.h"
#if defined(__MWERKS__) && defined(OPTIMIZED_FOR_SPEED)
#include "xx_integration_ext.h"
#endif /* defined(__MWERKS__) && defined(OPTIMIZED_FOR_SPEED) */
/**************************************************************************//**
@Group xx_id XX Interface (System call hooks)
@Description Prototypes, externals and typedefs for system-supplied
(external) routines
@{
*//***************************************************************************/
#if (defined(REPORT_EVENTS) && (REPORT_EVENTS > 0))
/**************************************************************************//**
@Function XX_EventById
@Description Event reporting routine - executed only when REPORT_EVENTS=1.
@Param[in] event - Event code (e_Event).
@Param[in] appId - Application identifier.
@Param[in] flags - Event flags.
@Param[in] msg - Event message.
@Return None
*//***************************************************************************/
void XX_EventById(uint32_t event, t_Handle appId, uint16_t flags, char *msg);
#else /* not REPORT_EVENTS */
#define XX_EventById(event, appId, flags, msg)
#endif /* REPORT_EVENTS */
#ifdef DEBUG_XX_MALLOC
void * XX_MallocDebug(uint32_t size, char *fname, int line);
void * XX_MallocSmartDebug(uint32_t size,
int memPartitionId,
uint32_t alignment,
char *fname,
int line);
#define XX_Malloc(sz) \
XX_MallocDebug((sz), __FILE__, __LINE__)
#define XX_MallocSmart(sz, memt, al) \
XX_MallocSmartDebug((sz), (memt), (al), __FILE__, __LINE__)
#else /* not DEBUG_XX_MALLOC */
/**************************************************************************//**
@Function XX_Malloc
@Description allocates contiguous block of memory.
@Param[in] size - Number of bytes to allocate.
@Return The address of the newly allocated block on success, NULL on failure.
*//***************************************************************************/
void * XX_Malloc(uint32_t size);
/**************************************************************************//**
@Function XX_MallocSmartInit
@Description Initializes SmartMalloc allocator.
@Return E_OK on success, error code otherwise.
*//***************************************************************************/
int XX_MallocSmartInit(void);
/**************************************************************************//**
@Function XX_MallocSmart
@Description Allocates contiguous block of memory in a specified
alignment and from the specified segment.
@Param[in] size - Number of bytes to allocate.
@Param[in] memPartitionId - Memory partition ID; The value zero must
be mapped to the default heap partition.
@Param[in] alignment - Required memory alignment (in bytes).
@Return The address of the newly allocated block on success, NULL on failure.
*//***************************************************************************/
void * XX_MallocSmart(uint32_t size, int memPartitionId, uint32_t alignment);
#endif /* not DEBUG_XX_MALLOC */
/**************************************************************************//**
@Function XX_FreeSmart
@Description Frees the memory block pointed to by "p".
Only for memory allocated by XX_MallocSmart
@Param[in] p_Memory - pointer to the memory block.
@Return None.
*//***************************************************************************/
void XX_FreeSmart(void *p_Memory);
/**************************************************************************//**
@Function XX_Free
@Description frees the memory block pointed to by "p".
@Param[in] p_Memory - pointer to the memory block.
@Return None.
*//***************************************************************************/
void XX_Free(void *p_Memory);
#ifndef NCSW_LINUX
/**************************************************************************//**
@Function XX_GetMemPartitionBase
@Description This routine gets the address of a memory segment according to
the memory type.
@Param[in] memPartitionId - Memory partition ID; The value zero must
be mapped to the default heap partition.
@Return The address of the required memory type.
*//***************************************************************************/
void * XX_GetMemPartitionBase(int memPartitionId);
#endif
/**************************************************************************//**
@Function XX_Print
@Description print a string.
@Param[in] str - string to print.
@Return None.
*//***************************************************************************/
void XX_Print(char *str, ...);
/**************************************************************************//**
@Function XX_GetChar
@Description Get character from console.
@Return Character is returned on success. Zero is returned otherwise.
*//***************************************************************************/
char XX_GetChar(void);
/**************************************************************************//**
@Function XX_PreallocAndBindIntr
@Description Preallocate and optionally bind it to given CPU.
@Param[in] irq - Interrupt ID (system-specific number).
@Param[in] cpu - CPU to bind to or -1 if iRQ should be unbound.
@Return E_OK on success; error code otherwise..
*//***************************************************************************/
t_Error XX_PreallocAndBindIntr(int irq, unsigned int cpu);
/**************************************************************************//**
@Function XX_DeallocIntr
@Description Deallocate preallocated interupt.
@Param[in] irq - Interrupt ID (system-specific number).
@Return E_OK on success; error code otherwise..
*//***************************************************************************/
t_Error XX_DeallocIntr(int irq);
/**************************************************************************//**
@Function XX_SetIntr
@Description Set an interrupt service routine for a specific interrupt source.
@Param[in] irq - Interrupt ID (system-specific number).
@Param[in] f_Isr - Callback routine that will be called when the interrupt occurs.
@Param[in] handle - The argument for the user callback routine.
@Return E_OK on success; error code otherwise..
*//***************************************************************************/
t_Error XX_SetIntr(int irq, t_Isr *f_Isr, t_Handle handle);
/**************************************************************************//**
@Function XX_FreeIntr
@Description Free a specific interrupt and a specific callback routine.
@Param[in] irq - Interrupt ID (system-specific number).
@Return E_OK on success; error code otherwise..
*//***************************************************************************/
t_Error XX_FreeIntr(int irq);
/**************************************************************************//**
@Function XX_EnableIntr
@Description Enable a specific interrupt.
@Param[in] irq - Interrupt ID (system-specific number).
@Return E_OK on success; error code otherwise..
*//***************************************************************************/
t_Error XX_EnableIntr(int irq);
/**************************************************************************//**
@Function XX_DisableIntr
@Description Disable a specific interrupt.
@Param[in] irq - Interrupt ID (system-specific number).
@Return E_OK on success; error code otherwise..
*//***************************************************************************/
t_Error XX_DisableIntr(int irq);
#if !(defined(__MWERKS__) && defined(OPTIMIZED_FOR_SPEED))
/**************************************************************************//**
@Function XX_DisableAllIntr
@Description Disable all interrupts by masking them at the CPU.
@Return A value that represents the interrupts state before the
operation, and should be passed to the matching
XX_RestoreAllIntr() call.
*//***************************************************************************/
uint32_t XX_DisableAllIntr(void);
/**************************************************************************//**
@Function XX_RestoreAllIntr
@Description Restore previous state of interrupts level at the CPU.
@Param[in] flags - A value that represents the interrupts state to restore,
as returned by the matching call for XX_DisableAllIntr().
@Return None.
*//***************************************************************************/
void XX_RestoreAllIntr(uint32_t flags);
#endif /* !(defined(__MWERKS__) && defined(OPTIMIZED_FOR_SPEED)) */
/**************************************************************************//**
@Function XX_Call
@Description Call a service in another task.
Activate the routine "f" via the queue identified by "IntrManagerId". The
parameter to "f" is Id - the handle of the destination object
@Param[in] intrManagerId - Queue ID.
@Param[in] f - routine pointer.
@Param[in] Id - the parameter to be passed to f().
@Param[in] h_App - Application handle.
@Param[in] flags - Unused,
@Return E_OK is returned on success. E_FAIL is returned otherwise (usually an operating system level failure).
*//***************************************************************************/
t_Error XX_Call( uint32_t intrManagerId,
t_Error (* f)(t_Handle),
t_Handle Id,
t_Handle h_App,
uint16_t flags );
/**************************************************************************//**
@Function XX_Exit
@Description Stop execution and report status (where it is applicable)
@Param[in] status - exit status
*//***************************************************************************/
void XX_Exit(int status);
/*****************************************************************************/
/* Tasklet Service Routines */
/*****************************************************************************/
typedef t_Handle t_TaskletHandle;
/**************************************************************************//**
@Function XX_InitTasklet
@Description Create and initialize a tasklet object.
@Param[in] routine - A routine to be ran as a tasklet.
@Param[in] data - An argument to pass to the tasklet.
@Return Tasklet handle is returned on success. NULL is returned otherwise.
*//***************************************************************************/
t_TaskletHandle XX_InitTasklet (void (*routine)(void *), void *data);
/**************************************************************************//**
@Function XX_FreeTasklet
@Description Free a tasklet object.
@Param[in] h_Tasklet - A handle to a tasklet to be free.
@Return None.
*//***************************************************************************/
void XX_FreeTasklet (t_TaskletHandle h_Tasklet);
/**************************************************************************//**
@Function XX_ScheduleTask
@Description Schedule a tasklet object.
@Param[in] h_Tasklet - A handle to a tasklet to be scheduled.
@Param[in] immediate - Indicate whether to schedule this tasklet on
the immediate queue or on the delayed one.
@Return 0 - on success. Error code - otherwise.
*//***************************************************************************/
int XX_ScheduleTask(t_TaskletHandle h_Tasklet, int immediate);
/**************************************************************************//**
@Function XX_FlushScheduledTasks
@Description Flush all tasks there are in the scheduled tasks queue.
@Return None.
*//***************************************************************************/
void XX_FlushScheduledTasks(void);
/**************************************************************************//**
@Function XX_TaskletIsQueued
@Description Check if task is queued.
@Param[in] h_Tasklet - A handle to a tasklet to be scheduled.
@Return 1 - task is queued. 0 - otherwise.
*//***************************************************************************/
int XX_TaskletIsQueued(t_TaskletHandle h_Tasklet);
/**************************************************************************//**
@Function XX_SetTaskletData
@Description Set data to a scheduled task. Used to change data of already
scheduled task.
@Param[in] h_Tasklet - A handle to a tasklet to be scheduled.
@Param[in] data - Data to be set.
*//***************************************************************************/
void XX_SetTaskletData(t_TaskletHandle h_Tasklet, t_Handle data);
/**************************************************************************//**
@Function XX_GetTaskletData
@Description Get the data of scheduled task.
@Param[in] h_Tasklet - A handle to a tasklet to be scheduled.
@Return handle to the data of the task.
*//***************************************************************************/
t_Handle XX_GetTaskletData(t_TaskletHandle h_Tasklet);
/**************************************************************************//**
@Function XX_BottomHalf
@Description Bottom half implementation, invoked by the interrupt handler.
This routine handles all bottom-half tasklets with interrupts
enabled.
@Return None.
*//***************************************************************************/
void XX_BottomHalf(void);
/*****************************************************************************/
/* Spinlock Service Routines */
/*****************************************************************************/
/**************************************************************************//**
@Function XX_InitSpinlock
@Description Creates a spinlock.
@Return Spinlock handle is returned on success; NULL otherwise.
*//***************************************************************************/
t_Handle XX_InitSpinlock(void);
/**************************************************************************//**
@Function XX_FreeSpinlock
@Description Frees the memory allocated for the spinlock creation.
@Param[in] h_Spinlock - A handle to a spinlock.
@Return None.
*//***************************************************************************/
void XX_FreeSpinlock(t_Handle h_Spinlock);
/**************************************************************************//**
@Function XX_LockSpinlock
@Description Locks a spinlock.
@Param[in] h_Spinlock - A handle to a spinlock.
@Return None.
*//***************************************************************************/
void XX_LockSpinlock(t_Handle h_Spinlock);
/**************************************************************************//**
@Function XX_UnlockSpinlock
@Description Unlocks a spinlock.
@Param[in] h_Spinlock - A handle to a spinlock.
@Return None.
*//***************************************************************************/
void XX_UnlockSpinlock(t_Handle h_Spinlock);
/**************************************************************************//**
@Function XX_LockIntrSpinlock
@Description Locks a spinlock (interrupt safe).
@Param[in] h_Spinlock - A handle to a spinlock.
@Return A value that represents the interrupts state before the
operation, and should be passed to the matching
XX_UnlockIntrSpinlock() call.
*//***************************************************************************/
uint32_t XX_LockIntrSpinlock(t_Handle h_Spinlock);
/**************************************************************************//**
@Function XX_UnlockIntrSpinlock
@Description Unlocks a spinlock (interrupt safe).
@Param[in] h_Spinlock - A handle to a spinlock.
@Param[in] intrFlags - A value that represents the interrupts state to
restore, as returned by the matching call for
XX_LockIntrSpinlock().
@Return None.
*//***************************************************************************/
void XX_UnlockIntrSpinlock(t_Handle h_Spinlock, uint32_t intrFlags);
/*****************************************************************************/
/* Timers Service Routines */
/*****************************************************************************/
/**************************************************************************//**
@Function XX_CurrentTime
@Description Returns current system time.
@Return Current system time (in milliseconds).
*//***************************************************************************/
uint32_t XX_CurrentTime(void);
/**************************************************************************//**
@Function XX_CreateTimer
@Description Creates a timer.
@Return Timer handle is returned on success; NULL otherwise.
*//***************************************************************************/
t_Handle XX_CreateTimer(void);
/**************************************************************************//**
@Function XX_FreeTimer
@Description Frees the memory allocated for the timer creation.
@Param[in] h_Timer - A handle to a timer.
@Return None.
*//***************************************************************************/
void XX_FreeTimer(t_Handle h_Timer);
/**************************************************************************//**
@Function XX_StartTimer
@Description Starts a timer.
The user can select to start the timer as periodic timer or as
one-shot timer. The user should provide a callback routine that
will be called when the timer expires.
@Param[in] h_Timer - A handle to a timer.
@Param[in] msecs - Timer expiration period (in milliseconds).
@Param[in] periodic - TRUE for a periodic timer;
FALSE for a one-shot timer..
@Param[in] f_TimerExpired - A callback routine to be called when the
timer expires.
@Param[in] h_Arg - The argument to pass in the timer-expired
callback routine.
@Return None.
*//***************************************************************************/
void XX_StartTimer(t_Handle h_Timer,
uint32_t msecs,
bool periodic,
void (*f_TimerExpired)(t_Handle h_Arg),
t_Handle h_Arg);
/**************************************************************************//**
@Function XX_StopTimer
@Description Frees the memory allocated for the timer creation.
@Param[in] h_Timer - A handle to a timer.
@Return None.
*//***************************************************************************/
void XX_StopTimer(t_Handle h_Timer);
/**************************************************************************//**
@Function XX_GetExpirationTime
@Description Returns the time (in milliseconds) remaining until the
expiration of a timer.
@Param[in] h_Timer - A handle to a timer.
@Return The time left until the timer expires.
*//***************************************************************************/
uint32_t XX_GetExpirationTime(t_Handle h_Timer);
/**************************************************************************//**
@Function XX_ModTimer
@Description Updates the expiration time of a timer.
This routine adds the given time to the current system time,
and sets this value as the new expiration time of the timer.
@Param[in] h_Timer - A handle to a timer.
@Param[in] msecs - The new interval until timer expiration
(in milliseconds).
@Return None.
*//***************************************************************************/
void XX_ModTimer(t_Handle h_Timer, uint32_t msecs);
/**************************************************************************//**
@Function XX_TimerIsActive
@Description Checks whether a timer is active (pending) or not.
@Param[in] h_Timer - A handle to a timer.
@Return 0 - the timer is inactive; Non-zero value - the timer is active;
*//***************************************************************************/
int XX_TimerIsActive(t_Handle h_Timer);
/**************************************************************************//**
@Function XX_Sleep
@Description Non-busy wait until the desired time (in milliseconds) has passed.
@Param[in] msecs - The requested sleep time (in milliseconds).
@Return None.
@Cautions This routine enables interrupts during its wait time.
*//***************************************************************************/
uint32_t XX_Sleep(uint32_t msecs);
/**************************************************************************//**
@Function XX_UDelay
@Description Busy-wait until the desired time (in microseconds) has passed.
@Param[in] usecs - The requested delay time (in microseconds).
@Return None.
@Cautions It is highly unrecommended to call this routine during interrupt
time, because the system time may not be updated properly during
the delay loop. The behavior of this routine during interrupt
time is unexpected.
*//***************************************************************************/
void XX_UDelay(uint32_t usecs);
/*****************************************************************************/
/* Other Service Routines */
/*****************************************************************************/
/**************************************************************************//**
@Function XX_PhysToVirt
@Description Translates a physical address to the matching virtual address.
@Param[in] addr - The physical address to translate.
@Return Virtual address.
*//***************************************************************************/
void * XX_PhysToVirt(physAddress_t addr);
/**************************************************************************//**
@Function XX_VirtToPhys
@Description Translates a virtual address to the matching physical address.
@Param[in] addr - The virtual address to translate.
@Return Physical address.
*//***************************************************************************/
physAddress_t XX_VirtToPhys(void *addr);
/**************************************************************************//**
@Function XX_PortalSetInfo
@Description Save physical and virtual adresses of the portals.
@Param[in] dev - Portals device - either bman or qman.
@Return Physical, virtual addresses and size.
*//***************************************************************************/
void XX_PortalSetInfo(device_t dev);
/**************************************************************************//**
@Function XX_FmanSetIntrInfo
@Description Workaround for FMan interrupt, which must be binded to one CPU
only.
@Param[in] irq - Interrupt number.
@Return None.
*//***************************************************************************/
void XX_FmanFixIntr(int irq);
/**************************************************************************//**
@Group xx_ipc XX Inter-Partition-Communication API
@Description The following API is to be used when working with multiple
partitions configuration.
@{
*//***************************************************************************/
#define XX_IPC_MAX_ADDR_NAME_LENGTH 16 /**< Maximum length of an endpoint name string;
The IPC service can use this constant to limit
the storage space for IPC endpoint names. */
/**************************************************************************//**
@Function t_IpcMsgCompletion
@Description Callback function used upon IPC non-blocking transaction completion
to return message buffer to the caller and to forward reply if available.
This callback function may be attached by the source endpoint to any outgoing
IPC message to indicate a non-blocking send (see also XX_IpcSendMessage() routine).
Upon completion of an IPC transaction (consisting of a message and an optional reply),
the IPC service invokes this callback routine to return the message buffer to the sender
and to provide the received reply, if requested.
User provides this function. Driver invokes it.
@Param[in] h_Module - Abstract handle to the sending module - the same handle as was passed
in the XX_IpcSendMessage() function; This handle is typically used to point
to the internal data structure of the source endpoint.
@Param[in] p_Msg - Pointer to original (sent) message buffer;
The source endpoint can free (or reuse) this buffer when message
completion callback is called.
@Param[in] p_Reply - Pointer to (received) reply buffer;
This pointer is the same as was provided by the source endpoint in
XX_IpcSendMessage().
@Param[in] replyLength - Length (in bytes) of actual data in the reply buffer.
@Param[in] status - Completion status - E_OK or failure indication, e.g. IPC transaction completion
timeout.
@Return None
*//***************************************************************************/
typedef void (t_IpcMsgCompletion)(t_Handle h_Module,
uint8_t *p_Msg,
uint8_t *p_Reply,
uint32_t replyLength,
t_Error status);
/**************************************************************************//**
@Function t_IpcMsgHandler
@Description Callback function used as IPC message handler.
The IPC service invokes message handlers for each IPC message received.
The actual function pointer should be registered by each destination endpoint
via the XX_IpcRegisterMsgHandler() routine.
User provides this function. Driver invokes it.
@Param[in] h_Module - Abstract handle to the message handling module - the same handle as
was passed in the XX_IpcRegisterMsgHandler() function; this handle is
typically used to point to the internal data structure of the destination
endpoint.
@Param[in] p_Msg - Pointer to message buffer with data received from peer.
@Param[in] msgLength - Length (in bytes) of message data.
@Param[in] p_Reply - Pointer to reply buffer, to be filled by the message handler and then sent
by the IPC service;
The reply buffer is allocated by the IPC service with size equals to the
replyLength parameter provided in message handler registration (see
XX_IpcRegisterMsgHandler() function);
If replyLength was initially specified as zero during message handler registration,
the IPC service may set this pointer to NULL and assume that a reply is not needed;
The IPC service is also responsible for freeing the reply buffer after the
reply has been sent or dismissed.
@Param[in,out] p_ReplyLength - Pointer to reply length, which has a dual role in this function:
[In] equals the replyLength parameter provided in message handler
registration (see XX_IpcRegisterMsgHandler() function), and
[Out] should be updated by message handler to the actual reply length; if
this value is set to zero, the IPC service must assume that a reply should
not be sent;
Note: If p_Reply is not NULL, p_ReplyLength must not be NULL as well.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
typedef t_Error (t_IpcMsgHandler)(t_Handle h_Module,
uint8_t *p_Msg,
uint32_t msgLength,
uint8_t *p_Reply,
uint32_t *p_ReplyLength);
/**************************************************************************//**
@Function XX_IpcRegisterMsgHandler
@Description IPC mailbox registration.
This function is used for registering an IPC message handler in the IPC service.
This function is called by each destination endpoint to indicate that it is ready
to handle incoming messages. The IPC service invokes the message handler upon receiving
a message addressed to the specified destination endpoint.
@Param[in] addr - The address name string associated with the destination endpoint;
This address must be unique across the IPC service domain to ensure
correct message routing.
@Param[in] f_MsgHandler - Pointer to the message handler callback for processing incoming
message; invoked by the IPC service upon receiving a message
addressed to the destination endpoint specified by the addr
parameter.
@Param[in] h_Module - Abstract handle to the message handling module, passed unchanged
to f_MsgHandler callback function.
@Param[in] replyLength - The maximal data length (in bytes) of any reply that the specified message handler
may generate; the IPC service provides the message handler with buffer
for reply according to the length specified here (refer also to the description
of #t_IpcMsgHandler callback function type);
This size shall be zero if the message handler never generates replies.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error XX_IpcRegisterMsgHandler(char addr[XX_IPC_MAX_ADDR_NAME_LENGTH],
t_IpcMsgHandler *f_MsgHandler,
t_Handle h_Module,
uint32_t replyLength);
/**************************************************************************//**
@Function XX_IpcUnregisterMsgHandler
@Description Release IPC mailbox routine.
This function is used for unregistering an IPC message handler from the IPC service.
This function is called by each destination endpoint to indicate that it is no longer
capable of handling incoming messages.
@Param[in] addr - The address name string associated with the destination endpoint;
This address is the same as was used when the message handler was
registered via XX_IpcRegisterMsgHandler().
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error XX_IpcUnregisterMsgHandler(char addr[XX_IPC_MAX_ADDR_NAME_LENGTH]);
/**************************************************************************//**
@Function XX_IpcInitSession
@Description This function is used for creating an IPC session between the source endpoint
and the destination endpoint.
The actual implementation and representation of a session is left for the IPC service.
The function returns an abstract handle to the created session. This handle shall be used
by the source endpoint in subsequent calls to XX_IpcSendMessage().
The IPC service assumes that before this function is called, no messages are sent from
the specified source endpoint to the specified destination endpoint.
The IPC service may use a connection-oriented approach or a connectionless approach (or both)
as described below.
@par Connection-Oriented Approach
The IPC service may implement a session in a connection-oriented approach - when this function is called,
the IPC service should take the necessary steps to bring up a source-to-destination channel for messages
and a destination-to-source channel for replies. The returned handle should represent the internal
representation of these channels.
@par Connectionless Approach
The IPC service may implement a session in a connectionless approach - when this function is called, the
IPC service should not perform any particular steps, but it must store the pair of source and destination
addresses in some session representation and return it as a handle. When XX_IpcSendMessage() shall be
called, the IPC service may use this handle to provide the necessary identifiers for routing the messages
through the connectionless medium.
@Param[in] destAddr - The address name string associated with the destination endpoint.
@Param[in] srcAddr - The address name string associated with the source endpoint.
@Return Abstract handle to the initialized session, or NULL on error.
*//***************************************************************************/
t_Handle XX_IpcInitSession(char destAddr[XX_IPC_MAX_ADDR_NAME_LENGTH],
char srcAddr[XX_IPC_MAX_ADDR_NAME_LENGTH]);
/**************************************************************************//**
@Function XX_IpcFreeSession
@Description This function is used for terminating an existing IPC session between a source endpoint
and a destination endpoint.
The IPC service assumes that after this function is called, no messages shall be sent from
the associated source endpoint to the associated destination endpoint.
@Param[in] h_Session - Abstract handle to the IPC session - the same handle as was originally
returned by the XX_IpcInitSession() function.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error XX_IpcFreeSession(t_Handle h_Session);
/**************************************************************************//**
@Function XX_IpcSendMessage
@Description IPC message send routine.
This function may be used by a source endpoint to send an IPC message to a destination
endpoint. The source endpoint cannot send a message to the destination endpoint without
first initiating a session with that destination endpoint via XX_IpcInitSession() routine.
The source endpoint must provide the buffer pointer and length of the outgoing message.
Optionally, it may also provide a buffer for an expected reply. In the latter case, the
transaction is not considered complete by the IPC service until the reply has been received.
If the source endpoint does not provide a reply buffer, the transaction is considered
complete after the message has been sent. The source endpoint must keep the message (and
optional reply) buffers valid until the transaction is complete.
@par Non-blocking mode
The source endpoint may request a non-blocking send by providing a non-NULL pointer to a message
completion callback function (f_Completion). Upon completion of the IPC transaction (consisting of a
message and an optional reply), the IPC service invokes this callback routine to return the message
buffer to the sender and to provide the received reply, if requested.
@par Blocking mode
The source endpoint may request a blocking send by setting f_Completion to NULL. The function is
expected to block until the IPC transaction is complete - either the reply has been received or (if no reply
was requested) the message has been sent.
@Param[in] h_Session - Abstract handle to the IPC session - the same handle as was originally
returned by the XX_IpcInitSession() function.
@Param[in] p_Msg - Pointer to message buffer to send.
@Param[in] msgLength - Length (in bytes) of actual data in the message buffer.
@Param[in] p_Reply - Pointer to reply buffer - if this buffer is not NULL, the IPC service
fills this buffer with the received reply data;
In blocking mode, the reply data must be valid when the function returns;
In non-blocking mode, the reply data is valid when f_Completion is called;
If this pointer is NULL, no reply is expected.
@Param[in,out] p_ReplyLength - Pointer to reply length, which has a dual role in this function:
[In] specifies the maximal length (in bytes) of the reply buffer pointed by
p_Reply, and
[Out] in non-blocking mode this value is updated by the IPC service to the
actual reply length (in bytes).
@Param[in] f_Completion - Pointer to a completion callback to be used in non-blocking send mode;
The completion callback is invoked by the IPC service upon
completion of the IPC transaction (consisting of a message and an optional
reply);
If this pointer is NULL, the function is expected to block until the IPC
transaction is complete.
@Param[in] h_Arg - Abstract handle to the sending module; passed unchanged to the f_Completion
callback function as the first argument.
@Return E_OK on success; Error code otherwise.
*//***************************************************************************/
t_Error XX_IpcSendMessage(t_Handle h_Session,
uint8_t *p_Msg,
uint32_t msgLength,
uint8_t *p_Reply,
uint32_t *p_ReplyLength,
t_IpcMsgCompletion *f_Completion,
t_Handle h_Arg);
/** @} */ /* end of xx_ipc group */
/** @} */ /* end of xx_id group */
/** FreeBSD Specific additions. */
void XX_TrackInit(void);
void XX_TrackAddress(void *addr);
void XX_UntrackAddress(void *addr);
#endif /* __XX_EXT_H */

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