Rename e500 prefix to match other Book-E CPU variations. CPU id tidbits for
the new cores. Obtained from: Freescale, Semihalf.
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0557f549f6
commit
8c2ef762a7
@ -185,8 +185,8 @@ SYSCTL_INT(_machdep, CPU_CACHELINE, cacheline_size,
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int hw_direct_map = 0;
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static void cpu_e500_startup(void *);
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SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_e500_startup, NULL);
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static void cpu_booke_startup(void *);
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SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_booke_startup, NULL);
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void print_kernel_section_addr(void);
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void print_kenv(void);
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@ -195,7 +195,7 @@ u_int booke_init(uint32_t, uint32_t);
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extern int elf32_nxstack;
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static void
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cpu_e500_startup(void *dummy)
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cpu_booke_startup(void *dummy)
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{
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int indx, size;
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@ -538,7 +538,8 @@ cpu_halt(void)
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{
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mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE));
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while (1);
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while (1)
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;
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}
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int
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@ -73,7 +73,7 @@ static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref);
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static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref);
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static int bare_smp_start_cpu(platform_t, struct pcpu *cpu);
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static void e500_reset(platform_t);
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static void booke_reset(platform_t);
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static platform_method_t bare_methods[] = {
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PLATFORMMETHOD(platform_probe, bare_probe),
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@ -85,7 +85,7 @@ static platform_method_t bare_methods[] = {
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PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp),
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PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu),
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PLATFORMMETHOD(platform_reset, e500_reset),
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PLATFORMMETHOD(platform_reset, booke_reset),
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{ 0, 0 }
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};
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@ -307,7 +307,7 @@ bare_smp_start_cpu(platform_t plat, struct pcpu *pc)
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}
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static void
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e500_reset(platform_t plat)
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booke_reset(platform_t plat)
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{
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/*
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@ -328,6 +328,7 @@ e500_reset(platform_t plat)
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mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM);
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printf("Reset failed...\n");
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while (1);
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while (1)
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;
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}
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@ -75,13 +75,13 @@
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#include <machine/spr.h>
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static void cpu_6xx_setup(int cpuid, uint16_t vers);
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static void cpu_e500_setup(int cpuid, uint16_t vers);
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static void cpu_970_setup(int cpuid, uint16_t vers);
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static void cpu_booke_setup(int cpuid, uint16_t vers);
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int powerpc_pow_enabled;
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void (*cpu_idle_hook)(void) = NULL;
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static void cpu_idle_60x(void);
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static void cpu_idle_e500(void);
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static void cpu_idle_booke(void);
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struct cputab {
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const char *name;
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@ -146,9 +146,13 @@ static const struct cputab models[] = {
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{ "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
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{ "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN,
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0, cpu_e500_setup },
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0, cpu_booke_setup },
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{ "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN,
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0, cpu_e500_setup },
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0, cpu_booke_setup },
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{ "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN,
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0, cpu_booke_setup },
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{ "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN,
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0, cpu_booke_setup },
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{ "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
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NULL},
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@ -191,6 +195,8 @@ cpu_setup(u_int cpuid)
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break;
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case FSL_E500v1:
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case FSL_E500v2:
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case FSL_E500mc:
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case FSL_E5500:
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maj = (pvr >> 4) & 0xf;
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min = (pvr >> 0) & 0xf;
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break;
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@ -438,7 +444,7 @@ cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
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}
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static void
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cpu_e500_setup(int cpuid, uint16_t vers)
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cpu_booke_setup(int cpuid, uint16_t vers)
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{
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register_t hid0;
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@ -453,7 +459,7 @@ cpu_e500_setup(int cpuid, uint16_t vers)
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printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK);
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if (cpu_idle_hook == NULL)
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cpu_idle_hook = cpu_idle_e500;
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cpu_idle_hook = cpu_idle_booke;
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}
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static void
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@ -519,6 +525,7 @@ cpu_idle(int busy)
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CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
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busy, curcpu);
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if (cpu_idle_hook != NULL) {
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if (!busy) {
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critical_enter();
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@ -530,6 +537,7 @@ cpu_idle(int busy)
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critical_exit();
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}
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}
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CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
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busy, curcpu);
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}
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@ -576,7 +584,7 @@ cpu_idle_60x(void)
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}
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static void
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cpu_idle_e500(void)
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cpu_idle_booke(void)
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{
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register_t msr;
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