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aic79xx_pci.c:

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aic7xxx_pci.c:
	When performing our register test, be careful
	to avoid resetting the chip when pausing the
	controller.  The test reads the HCNTRL register
	and then writes it back with the PAUSE bit
	explicitly set.  If the last write to the controller
	before our probe is to reset it, the CHIPRST
	bit will still be set, so we must mask it off
	before the PAUSE operation.  On some chip versions,
	we cannot access registers for a few 100us after
	a reset, so this inadvertant reset was causing PCI
	errors to occur on the read to check for paused
	status.

Submitted by:	gibbs
This commit is contained in:
scottl 2003-09-25 23:36:41 +00:00
parent 46474cb341
commit 8dab67f1ba
2 changed files with 8 additions and 4 deletions
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6
sys/dev/aic7xxx/aic79xx_pci.c
View File

@ -38,7 +38,7 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#76 $
* $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#80 $
*/
#include <sys/cdefs.h>
@ -453,8 +453,10 @@ ahd_pci_test_register_access(struct ahd_softc *ahd)
* or read prefetching could be initiated by the
* CPU or host bridge. Our device does not support
* either, so look for data corruption and/or flaged
* PCI errors.
* PCI errors. First pause without causing another
* chip reset.
*/
hcntrl &= ~CHIPRST;
ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
while (ahd_is_paused(ahd) == 0)
;

6
sys/dev/aic7xxx/aic7xxx_pci.c
View File

@ -39,7 +39,7 @@
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#69 $
* $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#72 $
*/
#include <sys/cdefs.h>
@ -1285,8 +1285,10 @@ ahc_pci_test_register_access(struct ahc_softc *ahc)
* or read prefetching could be initiated by the
* CPU or host bridge. Our device does not support
* either, so look for data corruption and/or flagged
* PCI errors.
* PCI errors. First pause without causing another
* chip reset.
*/
hcntrl &= ~CHIPRST;
ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
while (ahc_is_paused(ahc) == 0)
;