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Octeon 2 (6xxx) and newer CPUs don't use the clock CPU speed for its

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I/O clock. Thankfully, the simple executive provies a way to querry
the proper clock that works on all models. Move to asking for the SCLK
via this interface.

This gets the serial console working after we start init and open the
console and set the divisor (which turned the output from good to
bad). I can login on the console now.
This commit is contained in:
Warner Losh 2013-04-26 05:42:35 +00:00
parent 70c29e3930
commit 8e015fd886
1 changed files with 1 additions and 1 deletions
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2
sys/mips/cavium/uart_dev_oct16550.c
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@ -656,7 +656,7 @@ oct16550_bus_probe (struct uart_softc *sc)
int error;
bas = &sc->sc_bas;
bas->rclk = uart_oct16550_class.uc_rclk = cvmx_sysinfo_get()->cpu_clock_hz;
bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
error = oct16550_probe(bas);
if (error) {