Add sysctls to control PS-PL level shifters and FCLK settings.
PL (programmable logic) uses FCLK0..FCLK3 as a clock sources.
Normally they're configured by first stage boot loader (FSBL)
and normal user never has to touch them. These sysctls may come
useful for hardware developers
hw.fpga.fclk.N.source: clock source (IO, DDR, ARM)
hw.fpga.fclk.N.freq: requested frequency in Hz
hw.fpga.fclk.N.actual_freq: actual frequency in Hz (R/O)
hw.fgpa.level_shifters: 0/1 to enable/disable PS-PL level shifters,
normally they're enabled either by FSBL or after programming
FPGA through devcfg(4)
This commit is contained in:
Oleksandr Tymoshenko
parent
23e9ffb0e1
commit
8e01fdea2b
@ -72,10 +72,23 @@ struct zy7_devcfg_softc {
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bus_dmamap_t dma_map;
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int is_open;
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struct sysctl_ctx_list sysctl_tree;
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struct sysctl_oid *sysctl_tree_top;
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};
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static struct zy7_devcfg_softc *zy7_devcfg_softc_p;
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#define FCLK_NUM 4
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struct zy7_fclk_config {
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int source;
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int frequency;
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int actual_frequency;
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};
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static struct zy7_fclk_config fclk_configs[FCLK_NUM];
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#define DEVCFG_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define DEVCFG_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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#define DEVCFG_SC_LOCK_INIT(sc) \
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@ -103,13 +116,17 @@ static int zy7_ps_vers = 0;
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SYSCTL_INT(_hw, OID_AUTO, ps_vers, CTLFLAG_RD, &zy7_ps_vers, 0,
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"Zynq-7000 PS version");
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static int zy7_devcfg_fclk_sysctl_level_shifters(SYSCTL_HANDLER_ARGS);
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SYSCTL_PROC(_hw_fpga, OID_AUTO, level_shifters,
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CTLFLAG_RW | CTLTYPE_INT,
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NULL, 0, zy7_devcfg_fclk_sysctl_level_shifters,
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"I", "Enable/disable level shifters");
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/* cdev entry points. */
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static int zy7_devcfg_open(struct cdev *, int, int, struct thread *);
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static int zy7_devcfg_write(struct cdev *, struct uio *, int);
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static int zy7_devcfg_close(struct cdev *, int, int, struct thread *);
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struct cdevsw zy7_devcfg_cdevsw = {
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.d_version = D_VERSION,
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.d_open = zy7_devcfg_open,
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@ -230,6 +247,151 @@ struct cdevsw zy7_devcfg_cdevsw = {
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#define ZY7_DEVCFG_XADCIF_RD_FIFO 0x114
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#define ZY7_DEVCFG_XADCIF_MCTL 0x118
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static int
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zy7_devcfg_fclk_sysctl_source(SYSCTL_HANDLER_ARGS)
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{
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char buf[4];
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struct zy7_fclk_config *cfg;
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int unit;
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int error;
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cfg = arg1;
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unit = arg2;
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switch (cfg->source) {
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case ZY7_PL_FCLK_SRC_IO:
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case ZY7_PL_FCLK_SRC_IO_ALT:
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strncpy(buf, "IO", sizeof(buf));
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break;
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case ZY7_PL_FCLK_SRC_DDR:
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strncpy(buf, "DDR", sizeof(buf));
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break;
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case ZY7_PL_FCLK_SRC_ARM:
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strncpy(buf, "ARM", sizeof(buf));
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break;
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default:
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strncpy(buf, "???", sizeof(buf));
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break;
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}
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error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (strcasecmp(buf, "io") == 0)
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cfg->source = ZY7_PL_FCLK_SRC_IO;
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else if (strcasecmp(buf, "ddr") == 0)
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cfg->source = ZY7_PL_FCLK_SRC_DDR;
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else if (strcasecmp(buf, "arm") == 0)
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cfg->source = ZY7_PL_FCLK_SRC_ARM;
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else
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return (EINVAL);
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zy7_pl_fclk_set_source(unit, cfg->source);
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if (cfg->frequency > 0)
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cfg->actual_frequency = zy7_pl_fclk_get_freq(unit);
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return (0);
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}
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static int
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zy7_devcfg_fclk_sysctl_freq(SYSCTL_HANDLER_ARGS)
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{
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struct zy7_fclk_config *cfg;
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int unit;
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int error;
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int freq;
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int new_actual_freq;
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cfg = arg1;
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unit = arg2;
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freq = cfg->frequency;
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error = sysctl_handle_int(oidp, &freq, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (freq > 0) {
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new_actual_freq = zy7_pl_fclk_set_freq(unit, freq);
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if (new_actual_freq < 0)
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return (EINVAL);
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if (!zy7_pl_fclk_enabled(unit))
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zy7_pl_fclk_enable(unit);
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}
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else {
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zy7_pl_fclk_disable(unit);
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new_actual_freq = 0;
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}
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cfg->frequency = freq;
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cfg->actual_frequency = new_actual_freq;
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return (0);
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}
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static int
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zy7_devcfg_fclk_sysctl_level_shifters(SYSCTL_HANDLER_ARGS)
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{
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int error, enabled;
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enabled = zy7_pl_level_shifters_enabled();
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error = sysctl_handle_int(oidp, &enabled, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (enabled)
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zy7_pl_level_shifters_enable();
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else
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zy7_pl_level_shifters_disable();
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return (0);
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}
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static int
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zy7_devcfg_init_fclk_sysctl(struct zy7_devcfg_softc *sc)
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{
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struct sysctl_oid *fclk_node;
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char fclk_num[4];
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int i;
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sysctl_ctx_init(&sc->sysctl_tree);
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sc->sysctl_tree_top = SYSCTL_ADD_NODE(&sc->sysctl_tree,
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SYSCTL_STATIC_CHILDREN(_hw_fpga), OID_AUTO, "fclk",
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CTLFLAG_RD, 0, "");
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if (sc->sysctl_tree_top == NULL) {
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sysctl_ctx_free(&sc->sysctl_tree);
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return (-1);
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}
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for (i = 0; i < FCLK_NUM; i++) {
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snprintf(fclk_num, sizeof(fclk_num), "%d", i);
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fclk_node = SYSCTL_ADD_NODE(&sc->sysctl_tree,
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SYSCTL_CHILDREN(sc->sysctl_tree_top), OID_AUTO, fclk_num,
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CTLFLAG_RD, 0, "");
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SYSCTL_ADD_INT(&sc->sysctl_tree,
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SYSCTL_CHILDREN(fclk_node), OID_AUTO,
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"actual_freq", CTLFLAG_RD,
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&fclk_configs[i].actual_frequency, i,
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"Actual frequency");
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SYSCTL_ADD_PROC(&sc->sysctl_tree,
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SYSCTL_CHILDREN(fclk_node), OID_AUTO,
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"freq", CTLFLAG_RW | CTLTYPE_INT,
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&fclk_configs[i], i,
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zy7_devcfg_fclk_sysctl_freq,
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"I", "Configured frequency");
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SYSCTL_ADD_PROC(&sc->sysctl_tree,
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SYSCTL_CHILDREN(fclk_node), OID_AUTO,
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"source", CTLFLAG_RW | CTLTYPE_STRING,
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&fclk_configs[i], i,
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zy7_devcfg_fclk_sysctl_source,
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"A", "Clock source");
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}
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return (0);
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}
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/* Enable programming the PL through PCAP. */
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static void
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@ -334,7 +496,6 @@ zy7_dma_cb2(void *arg, bus_dma_segment_t *seg, int nsegs, int error)
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*(bus_addr_t *)arg = seg[0].ds_addr;
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}
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static int
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zy7_devcfg_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
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{
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@ -474,10 +635,11 @@ zy7_devcfg_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
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bus_dma_tag_destroy(sc->dma_tag);
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DEVCFG_SC_UNLOCK(sc);
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zy7_slcr_postload_pl(zy7_en_level_shifters);
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return (0);
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}
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static void
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zy7_devcfg_intr(void *arg)
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{
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@ -549,6 +711,7 @@ static int
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zy7_devcfg_attach(device_t dev)
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{
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struct zy7_devcfg_softc *sc = device_get_softc(dev);
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int i;
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int rid, err;
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/* Allow only one attach. */
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@ -612,6 +775,17 @@ zy7_devcfg_attach(device_t dev)
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ZY7_DEVCFG_MCTRL_PS_VERS_MASK) >>
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ZY7_DEVCFG_MCTRL_PS_VERS_SHIFT;
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for (i = 0; i < FCLK_NUM; i++) {
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fclk_configs[i].source = zy7_pl_fclk_get_source(i);
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fclk_configs[i].actual_frequency =
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zy7_pl_fclk_enabled(i) ? zy7_pl_fclk_get_freq(i) : 0;
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/* Initially assume actual frequency is the configure one */
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fclk_configs[i].frequency = fclk_configs[i].actual_frequency;
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}
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if (zy7_devcfg_init_fclk_sysctl(sc) < 0)
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device_printf(dev, "failed to initialized sysctl tree\n");
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return (0);
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}
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@ -620,6 +794,11 @@ zy7_devcfg_detach(device_t dev)
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{
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struct zy7_devcfg_softc *sc = device_get_softc(dev);
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if (sc->sysctl_tree_top != NULL) {
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sysctl_ctx_free(&sc->sysctl_tree);
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sc->sysctl_tree_top = NULL;
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}
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if (device_is_attached(dev))
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bus_generic_detach(dev);
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@ -79,7 +79,6 @@ extern void (*zynq7_cpu_reset);
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#define ZYNQ_DEFAULT_PS_CLK_FREQUENCY 33333333 /* 33.3 Mhz */
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SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
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static char zynq_bootmode[64];
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@ -126,7 +125,6 @@ zy7_slcr_lock(struct zy7_slcr_softc *sc)
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WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
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}
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static void
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zy7_slcr_cpu_reset(void)
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{
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@ -255,6 +253,296 @@ cgem_set_ref_clk(int unit, int frequency)
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return (0);
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}
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/*
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* PL clocks management function
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*/
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int
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zy7_pl_fclk_set_source(int unit, int source)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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uint32_t reg;
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if (!sc)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* Modify FPGAx source. */
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reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
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reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK);
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reg |= (source << ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT);
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WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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return (0);
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}
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int
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zy7_pl_fclk_get_source(int unit)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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uint32_t reg;
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int source;
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if (!sc)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Modify GEM reference clock. */
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reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
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source = (reg & ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK) >>
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ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT;
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/* ZY7_PL_FCLK_SRC_IO is actually b0x */
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if ((source & 2) == 0)
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source = ZY7_PL_FCLK_SRC_IO;
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ZSLCR_UNLOCK(sc);
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return (source);
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}
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int
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zy7_pl_fclk_set_freq(int unit, int frequency)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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int div0, div1;
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int base_frequency;
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uint32_t reg;
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int source;
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if (!sc)
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return (-1);
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source = zy7_pl_fclk_get_source(unit);
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switch (source) {
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case ZY7_PL_FCLK_SRC_IO:
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base_frequency = io_pll_frequency;
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break;
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case ZY7_PL_FCLK_SRC_ARM:
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base_frequency = arm_pll_frequency;
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break;
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case ZY7_PL_FCLK_SRC_DDR:
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base_frequency = ddr_pll_frequency;
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break;
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default:
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return (-1);
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}
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/* Find suitable divisor pairs. Round result to nearest khz
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* to test for match.
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*/
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for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) {
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div0 = (base_frequency + div1 * frequency / 2) /
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div1 / frequency;
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if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX &&
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((base_frequency / div0 / div1) + 500) / 1000 ==
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(frequency + 500) / 1000)
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break;
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}
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if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX)
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return (-1);
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ZSLCR_LOCK(sc);
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/* Unlock SLCR registers. */
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zy7_slcr_unlock(sc);
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/* Modify FPGAx reference clock. */
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reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
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reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK |
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ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK);
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reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) |
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(div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT);
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WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
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/* Lock SLCR registers. */
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zy7_slcr_lock(sc);
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ZSLCR_UNLOCK(sc);
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return (base_frequency / div0 / div1);
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}
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int
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zy7_pl_fclk_get_freq(int unit)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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int div0, div1;
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int base_frequency;
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int frequency;
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uint32_t reg;
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int source;
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if (!sc)
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return (-1);
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source = zy7_pl_fclk_get_source(unit);
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switch (source) {
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case ZY7_PL_FCLK_SRC_IO:
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base_frequency = io_pll_frequency;
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break;
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case ZY7_PL_FCLK_SRC_ARM:
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base_frequency = arm_pll_frequency;
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break;
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case ZY7_PL_FCLK_SRC_DDR:
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base_frequency = ddr_pll_frequency;
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break;
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default:
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return (-1);
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}
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ZSLCR_LOCK(sc);
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/* Modify FPGAx reference clock. */
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reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
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div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >>
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ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT;
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div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >>
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ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT;
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ZSLCR_UNLOCK(sc);
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if (div0 == 0)
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div0 = 1;
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if (div1 == 0)
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div1 = 1;
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frequency = (base_frequency / div0 / div1);
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/* Round to KHz */
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frequency = (frequency + 500) / 1000;
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frequency = frequency * 1000;
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return (frequency);
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}
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int
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zy7_pl_fclk_enable(int unit)
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{
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struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
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if (!sc)
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return (-1);
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ZSLCR_LOCK(sc);
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|
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/* Unlock SLCR registers. */
|
||||
zy7_slcr_unlock(sc);
|
||||
|
||||
WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
|
||||
WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0);
|
||||
|
||||
/* Lock SLCR registers. */
|
||||
zy7_slcr_lock(sc);
|
||||
|
||||
ZSLCR_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
zy7_pl_fclk_disable(int unit)
|
||||
{
|
||||
struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
|
||||
|
||||
if (!sc)
|
||||
return (-1);
|
||||
|
||||
ZSLCR_LOCK(sc);
|
||||
|
||||
/* Unlock SLCR registers. */
|
||||
zy7_slcr_unlock(sc);
|
||||
|
||||
WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
|
||||
WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1);
|
||||
|
||||
/* Lock SLCR registers. */
|
||||
zy7_slcr_lock(sc);
|
||||
|
||||
ZSLCR_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
zy7_pl_fclk_enabled(int unit)
|
||||
{
|
||||
struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
|
||||
uint32_t reg;
|
||||
|
||||
if (!sc)
|
||||
return (-1);
|
||||
|
||||
ZSLCR_LOCK(sc);
|
||||
reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));
|
||||
ZSLCR_UNLOCK(sc);
|
||||
|
||||
return !(reg & 1);
|
||||
}
|
||||
|
||||
int
|
||||
zy7_pl_level_shifters_enabled()
|
||||
{
|
||||
struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
|
||||
|
||||
uint32_t reg;
|
||||
|
||||
if (!sc)
|
||||
return (-1);
|
||||
|
||||
ZSLCR_LOCK(sc);
|
||||
reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN);
|
||||
ZSLCR_UNLOCK(sc);
|
||||
|
||||
return (reg == ZY7_SLCR_LVL_SHFTR_EN_ALL);
|
||||
}
|
||||
|
||||
void
|
||||
zy7_pl_level_shifters_enable()
|
||||
{
|
||||
struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
|
||||
|
||||
if (!sc)
|
||||
return;
|
||||
|
||||
ZSLCR_LOCK(sc);
|
||||
zy7_slcr_unlock(sc);
|
||||
WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
|
||||
zy7_slcr_lock(sc);
|
||||
ZSLCR_UNLOCK(sc);
|
||||
}
|
||||
|
||||
void
|
||||
zy7_pl_level_shifters_disable()
|
||||
{
|
||||
struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
|
||||
|
||||
if (!sc)
|
||||
return;
|
||||
|
||||
ZSLCR_LOCK(sc);
|
||||
zy7_slcr_unlock(sc);
|
||||
WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
|
||||
zy7_slcr_lock(sc);
|
||||
ZSLCR_UNLOCK(sc);
|
||||
}
|
||||
|
||||
static int
|
||||
zy7_slcr_probe(device_t dev)
|
||||
{
|
||||
|
||||
@ -37,7 +37,6 @@
|
||||
* are in appendix B.28.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _ZY7_SLCR_H_
|
||||
#define _ZY7_SLCR_H_
|
||||
|
||||
@ -148,10 +147,19 @@
|
||||
#define ZY7_SLCR_DBG_CLK_CTRL 0x0164
|
||||
#define ZY7_SLCR_PCAP_CLK_CTRL 0x0168
|
||||
#define ZY7_SLCR_TOPSW_CLK_CTRL 0x016c /* central intercnn clk ctrl */
|
||||
#define ZY7_SLCR_FPGA0_CLK_CTRL 0x0170
|
||||
#define ZY7_SLCR_FPGA1_CLK_CTRL 0x0180
|
||||
#define ZY7_SLCR_FPGA2_CLK_CTRL 0x0190
|
||||
#define ZY7_SLCR_FPGA3_CLK_CTRL 0x01a0
|
||||
#define ZY7_SLCR_FPGA_CLK_CTRL(unit) (0x0170 + 0x10*(unit))
|
||||
#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT 20
|
||||
#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK (0x3f << 20)
|
||||
#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT 8
|
||||
#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK (0x3f << 8)
|
||||
#define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX 0x3f
|
||||
#define ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_SHIFT 4
|
||||
#define ZY7_SLCR_FPGA_CLK_CTRL_SRCSEL_MASK (3 << 4)
|
||||
#define ZY7_SLCR_FPGA_THR_CTRL(unit) (0x0174 + 0x10*(unit))
|
||||
#define ZY7_SLCR_FPGA_THR_CTRL_CNT_RST (1 << 1)
|
||||
#define ZY7_SLCR_FPGA_THR_CTRL_CPU_START (1 << 0)
|
||||
#define ZY7_SLCR_FPGA_THR_CNT(unit) (0x0178 + 0x10*(unit))
|
||||
#define ZY7_SLCR_FPGA_THR_STA(unit) (0x017c + 0x10*(unit))
|
||||
#define ZY7_SLCR_CLK_621_TRUE 0x01c4 /* cpu clock ratio mode */
|
||||
|
||||
/* Reset controls. */
|
||||
@ -288,5 +296,23 @@
|
||||
extern void zy7_slcr_preload_pl(void);
|
||||
extern void zy7_slcr_postload_pl(int en_level_shifters);
|
||||
extern int cgem_set_ref_clk(int unit, int frequency);
|
||||
|
||||
/* Should be consistent with SRCSEL field of FPGAx_CLK_CTRL */
|
||||
#define ZY7_PL_FCLK_SRC_IO 0
|
||||
#define ZY7_PL_FCLK_SRC_IO_ALT 1 /* ZY7_PL_FCLK_SRC_IO is b0x */
|
||||
#define ZY7_PL_FCLK_SRC_ARM 2
|
||||
#define ZY7_PL_FCLK_SRC_DDR 3
|
||||
|
||||
int zy7_pl_fclk_set_source(int unit, int source);
|
||||
int zy7_pl_fclk_get_source(int unit);
|
||||
int zy7_pl_fclk_set_freq(int unit, int freq);
|
||||
int zy7_pl_fclk_get_freq(int unit);
|
||||
int zy7_pl_fclk_enable(int unit);
|
||||
int zy7_pl_fclk_disable(int unit);
|
||||
int zy7_pl_fclk_enabled(int unit);
|
||||
int zy7_pl_level_shifters_enabled(void);
|
||||
void zy7_pl_level_shifters_enable(void);
|
||||
void zy7_pl_level_shifters_disable(void);
|
||||
|
||||
#endif
|
||||
#endif /* _ZY7_SLCR_H_ */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user