Remove the non-INTRNG support from the GICv3 interrupt controller driver.
This is no longer needed. Obtained from: ABT Systems Ltd MFC after: 1 month Sponsored by: The FreeBSD Foundation
This commit is contained in:
andrew
parent
d620ee9519
commit
8e14fcd004
@ -69,7 +69,6 @@ __FBSDID("$FreeBSD$");
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static bus_read_ivar_t gic_v3_read_ivar;
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#ifdef INTRNG
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static pic_disable_intr_t gic_v3_disable_intr;
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static pic_enable_intr_t gic_v3_enable_intr;
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static pic_map_intr_t gic_v3_map_intr;
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@ -90,18 +89,6 @@ static u_int gic_irq_cpu;
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static u_int sgi_to_ipi[GIC_LAST_SGI - GIC_FIRST_SGI + 1];
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static u_int sgi_first_unused = GIC_FIRST_SGI;
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#endif
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#else
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/* Device and PIC methods */
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static int gic_v3_bind(device_t, u_int, u_int);
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static void gic_v3_dispatch(device_t, struct trapframe *);
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static void gic_v3_eoi(device_t, u_int);
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static void gic_v3_mask_irq(device_t, u_int);
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static void gic_v3_unmask_irq(device_t, u_int);
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#ifdef SMP
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static void gic_v3_init_secondary(device_t);
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static void gic_v3_ipi_send(device_t, cpuset_t, u_int);
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#endif
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#endif
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static device_method_t gic_v3_methods[] = {
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/* Device interface */
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@ -110,7 +97,6 @@ static device_method_t gic_v3_methods[] = {
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, gic_v3_read_ivar),
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#ifdef INTRNG
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/* Interrupt controller interface */
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DEVMETHOD(pic_disable_intr, gic_v3_disable_intr),
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DEVMETHOD(pic_enable_intr, gic_v3_enable_intr),
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@ -125,18 +111,6 @@ static device_method_t gic_v3_methods[] = {
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DEVMETHOD(pic_init_secondary, gic_v3_init_secondary),
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DEVMETHOD(pic_ipi_send, gic_v3_ipi_send),
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DEVMETHOD(pic_ipi_setup, gic_v3_ipi_setup),
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#endif
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#else
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/* PIC interface */
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DEVMETHOD(pic_bind, gic_v3_bind),
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DEVMETHOD(pic_dispatch, gic_v3_dispatch),
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DEVMETHOD(pic_eoi, gic_v3_eoi),
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DEVMETHOD(pic_mask, gic_v3_mask_irq),
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DEVMETHOD(pic_unmask, gic_v3_unmask_irq),
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#ifdef SMP
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DEVMETHOD(pic_init_secondary, gic_v3_init_secondary),
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DEVMETHOD(pic_ipi_send, gic_v3_ipi_send),
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#endif
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#endif
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/* End */
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@ -188,7 +162,6 @@ static gic_v3_initseq_t gic_v3_secondary_init[] = {
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};
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#endif
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#ifdef INTRNG
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uint32_t
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gic_r_read_4(device_t dev, bus_size_t offset)
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{
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@ -224,7 +197,6 @@ gic_r_write_8(device_t dev, bus_size_t offset, uint64_t val)
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sc = device_get_softc(dev);
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bus_write_8(sc->gic_redists.pcpu[PCPU_GET(cpuid)], offset, val);
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}
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#endif
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/*
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* Device interface.
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@ -238,10 +210,8 @@ gic_v3_attach(device_t dev)
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int rid;
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int err;
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size_t i;
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#ifdef INTRNG
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u_int irq;
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const char *name;
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#endif
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sc = device_get_softc(dev);
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sc->gic_registered = FALSE;
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@ -290,7 +260,6 @@ gic_v3_attach(device_t dev)
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if (sc->gic_nirqs > GIC_I_NUM_MAX)
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sc->gic_nirqs = GIC_I_NUM_MAX;
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#ifdef INTRNG
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sc->gic_irqs = malloc(sizeof(*sc->gic_irqs) * sc->gic_nirqs,
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M_GIC_V3, M_WAITOK | M_ZERO);
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name = device_get_nameunit(dev);
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@ -318,7 +287,6 @@ gic_v3_attach(device_t dev)
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return (err);
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}
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}
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#endif
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/* Get the number of supported interrupt identifier bits */
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sc->gic_idbits = GICD_TYPER_IDBITS(typer);
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@ -334,14 +302,6 @@ gic_v3_attach(device_t dev)
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if (err != 0)
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return (err);
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}
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/*
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* Full success.
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* Now register PIC to the interrupts handling layer.
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*/
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#ifndef INTRNG
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arm_register_root_pic(dev, sc->gic_nirqs);
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sc->gic_registered = TRUE;
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#endif
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return (0);
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}
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@ -394,7 +354,6 @@ gic_v3_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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return (ENOENT);
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}
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#ifdef INTRNG
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int
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arm_gic_v3_intr(void *arg)
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{
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@ -914,215 +873,6 @@ gic_v3_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
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return (0);
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}
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#endif /* SMP */
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#else /* INTRNG */
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/*
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* PIC interface.
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*/
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static int
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gic_v3_bind(device_t dev, u_int irq, u_int cpuid)
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{
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uint64_t aff;
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struct gic_v3_softc *sc;
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sc = device_get_softc(dev);
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if (irq <= GIC_LAST_PPI) {
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/* Can't bind PPI to another CPU but it's not an error */
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return (0);
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} else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) {
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aff = CPU_AFFINITY(cpuid);
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gic_d_write(sc, 4, GICD_IROUTER(irq), aff);
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return (0);
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} else if (irq >= GIC_FIRST_LPI)
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return (lpi_migrate(dev, irq, cpuid));
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return (EINVAL);
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}
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static void
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gic_v3_dispatch(device_t dev, struct trapframe *frame)
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{
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uint64_t active_irq;
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while (1) {
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if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) {
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/*
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* Hardware: Cavium ThunderX
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* Chip revision: Pass 1.0 (early version)
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* Pass 1.1 (production)
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* ERRATUM: 22978, 23154
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*/
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__asm __volatile(
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"nop;nop;nop;nop;nop;nop;nop;nop; \n"
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"mrs %0, ICC_IAR1_EL1 \n"
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"nop;nop;nop;nop; \n"
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"dsb sy \n"
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: "=&r" (active_irq));
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} else {
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active_irq = gic_icc_read(IAR1);
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}
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if (__predict_false(active_irq == ICC_IAR1_EL1_SPUR))
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break;
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if (__predict_true((active_irq >= GIC_FIRST_PPI &&
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active_irq <= GIC_LAST_SPI) || active_irq >= GIC_FIRST_LPI)) {
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arm_dispatch_intr(active_irq, frame);
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continue;
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}
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if (active_irq <= GIC_LAST_SGI) {
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gic_icc_write(EOIR1, (uint64_t)active_irq);
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arm_dispatch_intr(active_irq, frame);
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continue;
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}
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}
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}
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static void
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gic_v3_eoi(device_t dev, u_int irq)
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{
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gic_icc_write(EOIR1, (uint64_t)irq);
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}
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static void
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gic_v3_mask_irq(device_t dev, u_int irq)
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{
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struct gic_v3_softc *sc;
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sc = device_get_softc(dev);
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if (irq <= GIC_LAST_PPI) { /* SGIs and PPIs in corresponding Re-Distributor */
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gic_r_write(sc, 4,
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GICR_SGI_BASE_SIZE + GICD_ICENABLER(irq), GICD_I_MASK(irq));
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gic_v3_wait_for_rwp(sc, REDIST);
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} else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) { /* SPIs in distributor */
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gic_r_write(sc, 4, GICD_ICENABLER(irq), GICD_I_MASK(irq));
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gic_v3_wait_for_rwp(sc, DIST);
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} else if (irq >= GIC_FIRST_LPI) { /* LPIs */
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lpi_mask_irq(dev, irq);
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} else
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panic("%s: Unsupported IRQ number %u", __func__, irq);
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}
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static void
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gic_v3_unmask_irq(device_t dev, u_int irq)
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{
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struct gic_v3_softc *sc;
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sc = device_get_softc(dev);
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if (irq <= GIC_LAST_PPI) { /* SGIs and PPIs in corresponding Re-Distributor */
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gic_r_write(sc, 4,
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GICR_SGI_BASE_SIZE + GICD_ISENABLER(irq), GICD_I_MASK(irq));
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gic_v3_wait_for_rwp(sc, REDIST);
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} else if (irq >= GIC_FIRST_SPI && irq <= GIC_LAST_SPI) { /* SPIs in distributor */
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gic_d_write(sc, 4, GICD_ISENABLER(irq), GICD_I_MASK(irq));
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gic_v3_wait_for_rwp(sc, DIST);
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} else if (irq >= GIC_FIRST_LPI) { /* LPIs */
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lpi_unmask_irq(dev, irq);
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} else
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panic("%s: Unsupported IRQ number %u", __func__, irq);
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}
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#ifdef SMP
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static void
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gic_v3_init_secondary(device_t dev)
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{
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struct gic_v3_softc *sc;
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gic_v3_initseq_t *init_func;
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int err;
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sc = device_get_softc(dev);
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/* Train init sequence for boot CPU */
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for (init_func = gic_v3_secondary_init; *init_func != NULL; init_func++) {
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err = (*init_func)(sc);
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if (err != 0) {
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device_printf(dev,
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"Could not initialize GIC for CPU%u\n",
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PCPU_GET(cpuid));
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return;
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}
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}
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/*
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* Try to initialize ITS.
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* If there is no driver attached this routine will fail but that
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* does not mean failure here as only LPIs will not be functional
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* on the current CPU.
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*/
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if (its_init_cpu(NULL) != 0) {
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device_printf(dev,
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"Could not initialize ITS for CPU%u. "
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"No LPIs will arrive on this CPU\n",
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PCPU_GET(cpuid));
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}
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/*
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* ARM64TODO: Unmask timer PPIs. To be removed when appropriate
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* mechanism is implemented.
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* Activate the timer interrupts: virtual (27), secure (29),
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* and non-secure (30). Use hardcoded values here as there
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* should be no defines for them.
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*/
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gic_v3_unmask_irq(dev, 27);
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gic_v3_unmask_irq(dev, 29);
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gic_v3_unmask_irq(dev, 30);
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}
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static void
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gic_v3_ipi_send(device_t dev, cpuset_t cpuset, u_int ipi)
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{
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u_int cpu;
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uint64_t aff, tlist;
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uint64_t val;
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uint64_t aff_mask;
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/* Set affinity mask to match level 3, 2 and 1 */
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aff_mask = CPU_AFF1_MASK | CPU_AFF2_MASK | CPU_AFF3_MASK;
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/* Iterate through all CPUs in set */
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while (!CPU_EMPTY(&cpuset)) {
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aff = tlist = 0;
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for (cpu = 0; cpu < mp_ncpus; cpu++) {
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/* Compose target list for single AFF3:AFF2:AFF1 set */
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if (CPU_ISSET(cpu, &cpuset)) {
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if (!tlist) {
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/*
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* Save affinity of the first CPU to
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* send IPI to for later comparison.
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*/
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aff = CPU_AFFINITY(cpu);
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tlist |= (1UL << CPU_AFF0(aff));
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CPU_CLR(cpu, &cpuset);
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}
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/* Check for same Affinity level 3, 2 and 1 */
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if ((aff & aff_mask) == (CPU_AFFINITY(cpu) & aff_mask)) {
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tlist |= (1UL << CPU_AFF0(CPU_AFFINITY(cpu)));
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/* Clear CPU in cpuset from target list */
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CPU_CLR(cpu, &cpuset);
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}
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}
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}
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if (tlist) {
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KASSERT((tlist & ~ICC_SGI1R_EL1_TL_MASK) == 0,
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("Target list too long for GICv3 IPI"));
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/* Send SGI to CPUs in target list */
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val = tlist;
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val |= (uint64_t)CPU_AFF3(aff) << ICC_SGI1R_EL1_AFF3_SHIFT;
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val |= (uint64_t)CPU_AFF2(aff) << ICC_SGI1R_EL1_AFF2_SHIFT;
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val |= (uint64_t)CPU_AFF1(aff) << ICC_SGI1R_EL1_AFF1_SHIFT;
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val |= (uint64_t)(ipi & ICC_SGI1R_EL1_SGIID_MASK) <<
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ICC_SGI1R_EL1_SGIID_SHIFT;
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gic_icc_write(SGI1R, val);
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}
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}
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}
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#endif
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#endif /* !INTRNG */
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/*
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* Helper routines
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@ -116,9 +116,7 @@ gic_v3_fdt_attach(device_t dev)
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{
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struct gic_v3_softc *sc;
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pcell_t redist_regions;
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#ifdef INTRNG
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intptr_t xref;
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#endif
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int err;
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sc = device_get_softc(dev);
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@ -137,7 +135,6 @@ gic_v3_fdt_attach(device_t dev)
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if (err != 0)
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goto error;
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#ifdef INTRNG
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xref = OF_xref_from_node(ofw_bus_get_node(dev));
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sc->gic_pic = intr_pic_register(dev, xref);
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if (sc->gic_pic == NULL) {
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@ -151,7 +148,6 @@ gic_v3_fdt_attach(device_t dev)
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err = ENXIO;
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goto error;
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}
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#endif
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/*
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* Try to register ITS to this GIC.
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@ -165,10 +161,8 @@ gic_v3_fdt_attach(device_t dev)
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}
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}
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#ifdef INTRNG
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if (device_get_children(dev, &sc->gic_children, &sc->gic_nchildren) != 0)
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sc->gic_nchildren = 0;
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#endif
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return (err);
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@ -302,37 +296,3 @@ gic_v3_ofw_bus_attach(device_t dev)
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return (bus_generic_attach(dev));
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}
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#ifndef INTRNG
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static int gic_v3_its_fdt_probe(device_t dev);
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static device_method_t gic_v3_its_fdt_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, gic_v3_its_fdt_probe),
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/* End */
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(its, gic_v3_its_fdt_driver, gic_v3_its_fdt_methods,
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sizeof(struct gic_v3_its_softc), gic_v3_its_driver);
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static devclass_t gic_v3_its_fdt_devclass;
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EARLY_DRIVER_MODULE(its, gic, gic_v3_its_fdt_driver,
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gic_v3_its_fdt_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
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static int
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gic_v3_its_fdt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, GIC_V3_ITS_COMPSTR))
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return (ENXIO);
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device_set_desc(dev, GIC_V3_ITS_DEVSTR);
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return (BUS_PROBE_DEFAULT);
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}
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#endif
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@ -36,21 +36,12 @@
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DECLARE_CLASS(gic_v3_driver);
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#ifndef INTRNG
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#define LPI_FLAGS_CONF_FLUSH (1UL << 0)
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#define LPI_CONFTAB_SIZE PAGE_SIZE_64K
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/* 1 bit per LPI + 1 KB more for the obligatory PPI, SGI, SPI stuff */
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#define LPI_PENDTAB_SIZE ((LPI_CONFTAB_SIZE / 8) + 0x400)
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#endif
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#ifdef INTRNG
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struct gic_v3_irqsrc {
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struct intr_irqsrc gi_isrc;
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uint32_t gi_irq;
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enum intr_polarity gi_pol;
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enum intr_trigger gi_trig;
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};
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#endif
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struct redist_lpis {
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vm_offset_t conf_base;
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@ -87,17 +78,13 @@ struct gic_v3_softc {
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boolean_t gic_registered;
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#ifdef INTRNG
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int gic_nchildren;
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device_t *gic_children;
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struct intr_pic *gic_pic;
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struct gic_v3_irqsrc *gic_irqs;
|
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#endif
|
||||
};
|
||||
|
||||
#ifdef INTRNG
|
||||
#define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)
|
||||
#endif
|
||||
|
||||
MALLOC_DECLARE(M_GIC_V3);
|
||||
|
||||
@ -115,12 +102,10 @@ int gic_v3_attach(device_t dev);
|
||||
int gic_v3_detach(device_t dev);
|
||||
int arm_gic_v3_intr(void *);
|
||||
|
||||
#ifdef INTRNG
|
||||
uint32_t gic_r_read_4(device_t, bus_size_t);
|
||||
uint64_t gic_r_read_8(device_t, bus_size_t);
|
||||
void gic_r_write_4(device_t, bus_size_t, uint32_t var);
|
||||
void gic_r_write_8(device_t, bus_size_t, uint64_t var);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ITS
|
||||
@ -130,9 +115,6 @@ void gic_r_write_8(device_t, bus_size_t, uint64_t var);
|
||||
struct lpi_chunk {
|
||||
u_int lpi_base;
|
||||
u_int lpi_free; /* First free LPI in set */
|
||||
#ifndef INTRNG
|
||||
u_int *lpi_col_ids;
|
||||
#endif
|
||||
u_int lpi_num; /* Total number of LPIs in chunk */
|
||||
u_int lpi_busy; /* Number of busy LPIs in chink */
|
||||
};
|
||||
@ -150,64 +132,6 @@ struct its_dev {
|
||||
vm_offset_t itt;
|
||||
size_t itt_size;
|
||||
};
|
||||
#ifndef INTRNG
|
||||
TAILQ_HEAD(its_dev_list, its_dev);
|
||||
|
||||
/* ITS private table description */
|
||||
struct its_ptab {
|
||||
vm_offset_t ptab_vaddr; /* Virtual Address of table */
|
||||
size_t ptab_pgsz; /* Page size */
|
||||
size_t ptab_npages; /* Number of pages */
|
||||
};
|
||||
|
||||
/* ITS collection description. */
|
||||
struct its_col {
|
||||
uint64_t col_target; /* Target Re-Distributor */
|
||||
uint64_t col_id; /* Collection ID */
|
||||
};
|
||||
|
||||
/* ITS command. Each command is 32 bytes long */
|
||||
struct its_cmd {
|
||||
uint64_t cmd_dword[4]; /* ITS command double word */
|
||||
};
|
||||
|
||||
#define GIC_V3_ITS_DEVSTR "ARM GIC Interrupt Translation Service"
|
||||
#define GIC_V3_ITS_COMPSTR "arm,gic-v3-its"
|
||||
|
||||
DECLARE_CLASS(gic_v3_its_driver);
|
||||
|
||||
/* ITS commands encoding */
|
||||
#define ITS_CMD_MOVI (0x01)
|
||||
#define ITS_CMD_SYNC (0x05)
|
||||
#define ITS_CMD_MAPD (0x08)
|
||||
#define ITS_CMD_MAPC (0x09)
|
||||
#define ITS_CMD_MAPVI (0x0a)
|
||||
#define ITS_CMD_MAPI (0x0b)
|
||||
#define ITS_CMD_INV (0x0c)
|
||||
#define ITS_CMD_INVALL (0x0d)
|
||||
/* Command */
|
||||
#define CMD_COMMAND_MASK (0xFFUL)
|
||||
/* PCI device ID */
|
||||
#define CMD_DEVID_SHIFT (32)
|
||||
#define CMD_DEVID_MASK (0xFFFFFFFFUL << CMD_DEVID_SHIFT)
|
||||
/* Size of IRQ ID bitfield */
|
||||
#define CMD_SIZE_MASK (0xFFUL)
|
||||
/* Virtual LPI ID */
|
||||
#define CMD_ID_MASK (0xFFFFFFFFUL)
|
||||
/* Physical LPI ID */
|
||||
#define CMD_PID_SHIFT (32)
|
||||
#define CMD_PID_MASK (0xFFFFFFFFUL << CMD_PID_SHIFT)
|
||||
/* Collection */
|
||||
#define CMD_COL_MASK (0xFFFFUL)
|
||||
/* Target (CPU or Re-Distributor) */
|
||||
#define CMD_TARGET_SHIFT (16)
|
||||
#define CMD_TARGET_MASK (0xFFFFFFFFUL << CMD_TARGET_SHIFT)
|
||||
/* Interrupt Translation Table address */
|
||||
#define CMD_ITT_MASK (0xFFFFFFFFFF00UL)
|
||||
/* Valid command bit */
|
||||
#define CMD_VALID_SHIFT (63)
|
||||
#define CMD_VALID_MASK (1UL << CMD_VALID_SHIFT)
|
||||
#endif /* INTRNG */
|
||||
|
||||
/*
|
||||
* ITS command descriptor.
|
||||
@ -264,61 +188,6 @@ struct its_cmd_desc {
|
||||
|
||||
#define ITS_TARGET_NONE 0xFBADBEEF
|
||||
|
||||
#ifndef INTRNG
|
||||
#define ITS_CMDQ_SIZE PAGE_SIZE_64K
|
||||
#define ITS_CMDQ_NENTRIES (ITS_CMDQ_SIZE / sizeof(struct its_cmd))
|
||||
|
||||
#define ITS_FLAGS_CMDQ_FLUSH (1UL << 0)
|
||||
|
||||
struct gic_v3_its_softc {
|
||||
device_t dev;
|
||||
struct resource * its_res;
|
||||
|
||||
struct its_cmd * its_cmdq_base; /* ITS command queue base */
|
||||
struct its_cmd * its_cmdq_write; /* ITS command queue write ptr */
|
||||
struct its_ptab its_ptabs[GITS_BASER_NUM];/* ITS private tables */
|
||||
struct its_col * its_cols[MAXCPU];/* Per-CPU collections */
|
||||
|
||||
uint64_t its_flags;
|
||||
|
||||
#ifndef INTRNG
|
||||
struct its_dev_list its_dev_list;
|
||||
#endif
|
||||
|
||||
bitstr_t * its_lpi_bitmap;
|
||||
uint32_t its_lpi_maxid;
|
||||
|
||||
struct mtx its_dev_lock;
|
||||
struct mtx its_cmd_lock;
|
||||
|
||||
uint32_t its_socket; /* Socket number ITS is attached to */
|
||||
};
|
||||
|
||||
/* Stuff that is specific to the vendor's implementation */
|
||||
typedef uint32_t (*its_devbits_func_t)(device_t);
|
||||
|
||||
struct its_quirks {
|
||||
uint64_t cpuid;
|
||||
uint64_t cpuid_mask;
|
||||
its_devbits_func_t devbits_func;
|
||||
};
|
||||
|
||||
extern devclass_t gic_v3_its_devclass;
|
||||
|
||||
int gic_v3_its_detach(device_t);
|
||||
|
||||
int gic_v3_its_alloc_msix(device_t, device_t, int *);
|
||||
int gic_v3_its_release_msix(device_t, device_t, int);
|
||||
int gic_v3_its_alloc_msi(device_t, device_t, int, int *);
|
||||
int gic_v3_its_release_msi(device_t, device_t, int, int *);
|
||||
int gic_v3_its_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
|
||||
|
||||
int its_init_cpu(struct gic_v3_its_softc *);
|
||||
|
||||
int lpi_migrate(device_t, uint32_t, u_int);
|
||||
void lpi_unmask_irq(device_t, uint32_t);
|
||||
void lpi_mask_irq(device_t, uint32_t);
|
||||
#endif
|
||||
/*
|
||||
* GIC Distributor accessors.
|
||||
* Notice that only GIC sofc can be passed.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user