Keep the shadow PCIR_COMMAND synced with the real one for pass through.
This ensures that bhyve properly recognizes when decoding is disabled for BARs on passthru devices. To properly handle writes to the register, export a pci_emul_cmd_changed function from pci_emul.c that the pass through device model invokes for config writes that change PCIR_COMMAND. Reviewed by: rgrimes MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D20531
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44305ec379
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8e4b03df46
@ -1679,11 +1679,64 @@ pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
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}
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}
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}
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}
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/*
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* Update device state in response to changes to the PCI command
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* register.
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*/
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void
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pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old)
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{
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int i;
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uint16_t changed, new;
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new = pci_get_cfgdata16(pi, PCIR_COMMAND);
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changed = old ^ new;
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/*
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* If the MMIO or I/O address space decoding has changed then
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* register/unregister all BARs that decode that address space.
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*/
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for (i = 0; i <= PCI_BARMAX; i++) {
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switch (pi->pi_bar[i].type) {
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case PCIBAR_NONE:
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case PCIBAR_MEMHI64:
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break;
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case PCIBAR_IO:
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/* I/O address space decoding changed? */
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if (changed & PCIM_CMD_PORTEN) {
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if (new & PCIM_CMD_PORTEN)
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register_bar(pi, i);
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else
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unregister_bar(pi, i);
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}
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break;
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case PCIBAR_MEM32:
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case PCIBAR_MEM64:
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/* MMIO address space decoding changed? */
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if (changed & PCIM_CMD_MEMEN) {
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if (new & PCIM_CMD_MEMEN)
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register_bar(pi, i);
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else
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unregister_bar(pi, i);
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}
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break;
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default:
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assert(0);
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}
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}
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/*
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* If INTx has been unmasked and is pending, assert the
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* interrupt.
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*/
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pci_lintr_update(pi);
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}
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static void
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static void
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pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
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pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
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{
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{
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int i, rshift;
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int rshift;
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uint32_t cmd, cmd2, changed, old, readonly;
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uint32_t cmd, old, readonly;
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cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
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cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
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@ -1702,47 +1755,7 @@ pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
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new |= (old & readonly);
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new |= (old & readonly);
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CFGWRITE(pi, coff, new, bytes); /* update config */
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CFGWRITE(pi, coff, new, bytes); /* update config */
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cmd2 = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */
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pci_emul_cmd_changed(pi, cmd);
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changed = cmd ^ cmd2;
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/*
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* If the MMIO or I/O address space decoding has changed then
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* register/unregister all BARs that decode that address space.
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*/
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for (i = 0; i <= PCI_BARMAX; i++) {
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switch (pi->pi_bar[i].type) {
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case PCIBAR_NONE:
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case PCIBAR_MEMHI64:
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break;
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case PCIBAR_IO:
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/* I/O address space decoding changed? */
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if (changed & PCIM_CMD_PORTEN) {
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if (porten(pi))
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register_bar(pi, i);
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else
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unregister_bar(pi, i);
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}
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break;
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case PCIBAR_MEM32:
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case PCIBAR_MEM64:
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/* MMIO address space decoding changed? */
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if (changed & PCIM_CMD_MEMEN) {
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if (memen(pi))
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register_bar(pi, i);
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else
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unregister_bar(pi, i);
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}
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break;
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default:
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assert(0);
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}
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}
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/*
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* If INTx has been unmasked and is pending, assert the
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* interrupt.
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*/
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pci_lintr_update(pi);
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}
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}
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static void
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static void
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@ -223,6 +223,7 @@ int pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx,
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uint64_t hostbase, enum pcibar_type type, uint64_t size);
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uint64_t hostbase, enum pcibar_type type, uint64_t size);
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int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
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int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
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int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
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int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
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void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old);
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void pci_generate_msi(struct pci_devinst *pi, int msgnum);
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void pci_generate_msi(struct pci_devinst *pi, int msgnum);
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void pci_generate_msix(struct pci_devinst *pi, int msgnum);
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void pci_generate_msix(struct pci_devinst *pi, int msgnum);
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void pci_lintr_assert(struct pci_devinst *pi);
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void pci_lintr_assert(struct pci_devinst *pi);
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@ -639,6 +639,9 @@ cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
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goto done;
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goto done;
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}
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}
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pci_set_cfgdata16(pi, PCIR_COMMAND, read_config(&sc->psc_sel,
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PCIR_COMMAND, 2));
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error = 0; /* success */
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error = 0; /* success */
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done:
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done:
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return (error);
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return (error);
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@ -815,6 +818,7 @@ passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
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{
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{
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int error, msix_table_entries, i;
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int error, msix_table_entries, i;
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struct passthru_softc *sc;
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struct passthru_softc *sc;
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uint16_t cmd_old;
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sc = pi->pi_arg;
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sc = pi->pi_arg;
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@ -871,6 +875,14 @@ passthru_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
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#endif
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#endif
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write_config(&sc->psc_sel, coff, bytes, val);
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write_config(&sc->psc_sel, coff, bytes, val);
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if (coff == PCIR_COMMAND) {
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cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);
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if (bytes == 1)
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pci_set_cfgdata8(pi, PCIR_COMMAND, val);
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else if (bytes == 2)
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pci_set_cfgdata16(pi, PCIR_COMMAND, val);
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pci_emul_cmd_changed(pi, cmd_old);
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}
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return (0);
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return (0);
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}
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}
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