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For USIII CPUs the type of the trap caused by peeking/poking non-existent

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PCI devices apparently was changed from a special deferred trap with TPC
pointing to the membar #Sync following the failing load/store instruction
to a precise trap with TPC pointing to the failing load/store instruction.
Thus remove the check the check whether TPC points to a membar #Sync in
case of a data access trap as it's off-by-one for USIII CPUs and it should
be sufficient to check whether the trap happend while in fasword*() to
properly detect traps caused by peeking/poking. This also corresponds to
what other OSs do. Note that also only the USIIi manual suggests to check
the TPC for such traps while the USII one doesn't (in the public USIII
manual device peeking/poking isn't mentioned at all).
This commit is contained in:
marius 2006-04-04 21:00:44 +00:00
parent 06e487e0f3
commit 8ea6d154a2
1 changed files with 5 additions and 7 deletions
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12
sys/sparc64/sparc64/trap.c
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@ -354,14 +354,13 @@ trap(struct trapframe *tf)
break;
case T_DATA_ERROR:
/*
* handle PCI poke/peek as per UltraSPARC IIi
* User's Manual 16.2.1.
* Handle PCI poke/peek as per UltraSPARC IIi
* User's Manual 16.2.1, modulo checking the
* TPC as USIII CPUs generate a precise trap
* instead of a special deferred one.
*/
#define MEMBARSYNC_INST ((u_int32_t)0x8143e040)
if (tf->tf_tpc > (u_long)fas_nofault_begin &&
tf->tf_tpc < (u_long)fas_nofault_end &&
*(u_int32_t *)tf->tf_tpc == MEMBARSYNC_INST &&
((u_int32_t *)tf->tf_tpc)[-2] == MEMBARSYNC_INST) {
tf->tf_tpc < (u_long)fas_nofault_end) {
cache_flush();
cache_enable();
tf->tf_tpc = (u_long)fas_fault;
@ -369,7 +368,6 @@ trap(struct trapframe *tf)
error = 0;
break;
}
#undef MEMBARSYNC_INST
error = 1;
break;
default: