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amd-vi: clear event interrupt and overflow bits upon handling the interrupt

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This ensures that we can receive further event interrupts.
See the description of the bits in the specification for
MMIO Offset 2020h IOMMU Status Register.
The bits are defined as set-by-hardware write-1-to-clear, same as all
the bits in the status register.

Discussed with:	anish
This commit is contained in:
Andriy Gapon 2017-12-04 17:02:53 +00:00
parent 1f99cce2b0
commit 8f09494d1e
1 changed files with 6 additions and 0 deletions
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6
sys/amd64/vmm/amd/amdvi_hw.c
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@ -815,6 +815,7 @@ amdvi_event_intr(void *arg)
softc->total_cmd, ctrl->cmd_tail, ctrl->cmd_head);
amdvi_print_events(softc);
ctrl->status &= AMDVI_STATUS_EV_OF | AMDVI_STATUS_EV_INTR;
}
static void
@ -839,6 +840,7 @@ amdvi_free_evt_intr_res(device_t dev)
static bool
amdvi_alloc_intr_resources(struct amdvi_softc *softc)
{
struct amdvi_ctrl *ctrl;
device_t dev, pcib;
uint64_t msi_addr;
uint32_t msi_data, temp;
@ -903,6 +905,10 @@ amdvi_alloc_intr_resources(struct amdvi_softc *softc)
return (err);
}
/* Clear interrupt status bits. */
ctrl = softc->ctrl;
ctrl->status &= AMDVI_STATUS_EV_OF | AMDVI_STATUS_EV_INTR;
/* Configure MSI */
amdvi_pci_write(softc, msi_off + PCIR_MSI_ADDR, msi_addr);
amdvi_pci_write(softc, msi_off + PCIR_MSI_ADDR_HIGH,