Update to the ixgbe driver:
- Add a couple of new devices - Flow control changes in shared and core code - Bug fix to Flow Director for 82598 - Shared code sync to internal with required core change Thanks to those helping in the testing and improvements to this driver! MFC after:5 days
This commit is contained in:
jfv
parent
2fed9a44b5
commit
8f97f54d9e
@ -47,7 +47,7 @@ int ixgbe_display_debug_stats = 0;
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/*********************************************************************
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* Driver version
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*********************************************************************/
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char ixgbe_driver_version[] = "2.4.5";
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char ixgbe_driver_version[] = "2.4.8";
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/*********************************************************************
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* PCI Device ID Table
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@ -80,8 +80,10 @@ static ixgbe_vendor_info_t ixgbe_vendor_info_array[] =
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{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM, 0, 0, 0},
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{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE, 0, 0, 0},
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{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE, 0, 0, 0},
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{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2, 0, 0, 0},
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{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE, 0, 0, 0},
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{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP, 0, 0, 0},
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{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, 0, 0, 0},
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{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T, 0, 0, 0},
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/* required last entry */
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{0, 0, 0, 0, 0}
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@ -242,10 +244,6 @@ TUNABLE_INT("hw.ixgbe.max_interrupt_rate", &ixgbe_max_interrupt_rate);
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static int ixgbe_rx_process_limit = 128;
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TUNABLE_INT("hw.ixgbe.rx_process_limit", &ixgbe_rx_process_limit);
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/* Flow control setting, default to full */
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static int ixgbe_flow_control = ixgbe_fc_full;
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TUNABLE_INT("hw.ixgbe.flow_control", &ixgbe_flow_control);
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/*
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** Smart speed setting, default to on
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** this only works as a compile option
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@ -526,28 +524,25 @@ ixgbe_attach(device_t dev)
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goto err_late;
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}
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/* Get Hardware Flow Control setting */
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hw->fc.requested_mode = ixgbe_fc_full;
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adapter->fc = hw->fc.requested_mode;
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hw->fc.pause_time = IXGBE_FC_PAUSE;
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hw->fc.low_water = IXGBE_FC_LO;
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hw->fc.high_water[0] = IXGBE_FC_HI;
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hw->fc.send_xon = TRUE;
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error = ixgbe_init_hw(hw);
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if (error == IXGBE_ERR_EEPROM_VERSION) {
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switch (error) {
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case IXGBE_ERR_EEPROM_VERSION:
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device_printf(dev, "This device is a pre-production adapter/"
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"LOM. Please be aware there may be issues associated "
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"with your hardware.\n If you are experiencing problems "
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"please contact your Intel or hardware representative "
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"who provided you with this hardware.\n");
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} else if (error == IXGBE_ERR_SFP_NOT_SUPPORTED)
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break;
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case IXGBE_ERR_SFP_NOT_SUPPORTED:
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device_printf(dev,"Unsupported SFP+ Module\n");
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if (error) {
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error = EIO;
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device_printf(dev,"Hardware Initialization Failure\n");
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goto err_late;
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case IXGBE_ERR_SFP_NOT_PRESENT:
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device_printf(dev,"No SFP+ Module found\n");
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/* falls thru */
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default:
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break;
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}
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/* Detect and set physical type */
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@ -1236,7 +1231,7 @@ ixgbe_init_locked(struct adapter *adapter)
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#ifdef IXGBE_FDIR
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/* Init Flow director */
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if (hw->mac.type != ixgbe_mac_82598EB) {
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u32 hdrm = 64 << fdir_pballoc;
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u32 hdrm = 32 << fdir_pballoc;
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hw->mac.ops.setup_rxpba(hw, 0, hdrm, PBA_STRATEGY_EQUAL);
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ixgbe_init_fdir_signature_82599(&adapter->hw, fdir_pballoc);
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@ -1262,6 +1257,35 @@ ixgbe_init_locked(struct adapter *adapter)
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/* Config/Enable Link */
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ixgbe_config_link(adapter);
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/* Hardware Packet Buffer & Flow Control setup */
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{
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u32 rxpb, frame, size, tmp;
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frame = adapter->max_frame_size;
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/* Calculate High Water */
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if (hw->mac.type == ixgbe_mac_X540)
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tmp = IXGBE_DV_X540(frame, frame);
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else
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tmp = IXGBE_DV(frame, frame);
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size = IXGBE_BT2KB(tmp);
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rxpb = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) >> 10;
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hw->fc.high_water[0] = rxpb - size;
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/* Now calculate Low Water */
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if (hw->mac.type == ixgbe_mac_X540)
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tmp = IXGBE_LOW_DV_X540(frame);
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else
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tmp = IXGBE_LOW_DV(frame);
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hw->fc.low_water[0] = IXGBE_BT2KB(tmp);
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adapter->fc = hw->fc.requested_mode = ixgbe_fc_full;
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hw->fc.pause_time = IXGBE_FC_PAUSE;
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hw->fc.send_xon = TRUE;
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}
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/* Initialize the FC settings */
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ixgbe_start_hw(hw);
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/* And now turn on interrupts */
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ixgbe_enable_intr(adapter);
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@ -1551,10 +1575,8 @@ ixgbe_msix_link(void *arg)
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/* This is probably overkill :) */
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if (!atomic_cmpset_int(&adapter->fdir_reinit, 0, 1))
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return;
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/* Clear the interrupt */
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IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
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/* Turn off the interface */
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adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
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/* Disable the interrupt */
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IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EICR_FLOW_DIR);
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taskqueue_enqueue(adapter->tq, &adapter->fdir_task);
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} else
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#endif
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@ -2056,6 +2078,8 @@ ixgbe_update_link_status(struct adapter *adapter)
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((adapter->link_speed == 128)? 10:1),
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"Full Duplex");
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adapter->link_active = TRUE;
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/* Update any Flow Control changes */
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ixgbe_fc_enable(&adapter->hw);
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if_link_state_change(ifp, LINK_STATE_UP);
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}
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} else { /* Link down */
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@ -3063,7 +3087,7 @@ ixgbe_initialize_transmit_units(struct adapter *adapter)
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txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
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break;
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}
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txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
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txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
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switch (hw->mac.type) {
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case ixgbe_mac_82598EB:
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IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), txctrl);
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@ -5095,6 +5119,8 @@ ixgbe_reinit_fdir(void *context, int pending)
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return;
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ixgbe_reinit_fdir_tables_82599(&adapter->hw);
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adapter->fdir_reinit = 0;
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/* re-enable flow director interrupts */
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
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/* Restart the interface */
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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return;
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@ -5652,8 +5678,9 @@ ixgbe_set_flowcntl(SYSCTL_HANDLER_ARGS)
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default:
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adapter->hw.fc.requested_mode = ixgbe_fc_none;
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}
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ixgbe_fc_enable(&adapter->hw, 0);
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/* Don't autoneg if forcing a value */
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adapter->hw.fc.disable_fc_autoneg = TRUE;
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ixgbe_fc_enable(&adapter->hw);
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return error;
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}
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@ -5669,9 +5696,9 @@ ixgbe_add_rx_process_limit(struct adapter *adapter, const char *name,
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/*
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** Control link advertise speed:
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** 0 - normal
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** 1 - advertise only 1G
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** 2 - advertise 100Mb
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** 3 - advertise normal
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*/
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static int
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ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
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@ -5685,13 +5712,15 @@ ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
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adapter = (struct adapter *) arg1;
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dev = adapter->dev;
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hw = &adapter->hw;
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last = hw->phy.autoneg_advertised;
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last = adapter->advertise;
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error = sysctl_handle_int(oidp, &adapter->advertise, 0, req);
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if ((error) || (adapter->advertise == -1))
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return (error);
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if (adapter->advertise == last) /* no change */
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return (0);
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if (!((hw->phy.media_type == ixgbe_media_type_copper) ||
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(hw->phy.multispeed_fiber)))
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return (error);
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@ -5705,11 +5734,10 @@ ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
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speed = IXGBE_LINK_SPEED_1GB_FULL;
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else if (adapter->advertise == 2)
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speed = IXGBE_LINK_SPEED_100_FULL;
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else
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else if (adapter->advertise == 3)
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speed = IXGBE_LINK_SPEED_1GB_FULL |
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IXGBE_LINK_SPEED_10GB_FULL;
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if (speed == last) /* no change */
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else /* bogus value */
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return (error);
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hw->mac.autotry_restart = TRUE;
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@ -103,31 +103,6 @@ out:
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IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
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}
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/**
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* ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
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* @hw: pointer to hardware structure
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*
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* Read PCIe configuration space, and get the MSI-X vector count from
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* the capabilities table.
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**/
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u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
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{
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u32 msix_count = 18;
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DEBUGFUNC("ixgbe_get_pcie_msix_count_82598");
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if (hw->mac.msix_vectors_from_pcie) {
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msix_count = IXGBE_READ_PCIE_WORD(hw,
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IXGBE_PCIE_MSIX_82598_CAPS);
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msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
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/* MSI-X count is zero-based in HW, so increment to give
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* proper value */
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msix_count++;
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}
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return msix_count;
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}
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/**
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* ixgbe_init_ops_82598 - Inits func ptrs and MAC type
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* @hw: pointer to hardware structure
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@ -176,7 +151,7 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
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mac->rx_pb_size = 512;
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mac->max_tx_queues = 32;
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mac->max_rx_queues = 64;
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mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
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mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
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/* SFP+ Module */
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phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
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@ -280,15 +255,15 @@ s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
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for (i = 0; ((i < hw->mac.max_tx_queues) &&
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(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
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regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
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regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
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IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
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}
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for (i = 0; ((i < hw->mac.max_rx_queues) &&
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(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
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regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
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IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
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regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
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IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
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IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
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}
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@ -416,21 +391,41 @@ out:
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/**
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* ixgbe_fc_enable_82598 - Enable flow control
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* @hw: pointer to hardware structure
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* @packetbuf_num: packet buffer number (0-7)
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*
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* Enable flow control according to the current settings.
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**/
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s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
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s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
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{
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s32 ret_val = IXGBE_SUCCESS;
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u32 fctrl_reg;
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u32 rmcs_reg;
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u32 reg;
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u32 fcrtl, fcrth;
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u32 link_speed = 0;
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int i;
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bool link_up;
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DEBUGFUNC("ixgbe_fc_enable_82598");
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/* Validate the water mark configuration */
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if (!hw->fc.pause_time) {
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ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
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goto out;
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}
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/* Low water mark of zero causes XOFF floods */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
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hw->fc.high_water[i]) {
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if (!hw->fc.low_water[i] ||
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hw->fc.low_water[i] >= hw->fc.high_water[i]) {
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DEBUGOUT("Invalid water mark configuration\n");
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ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
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goto out;
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}
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}
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}
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/*
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* On 82598 having Rx FC on causes resets while doing 1G
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* so if it's on turn it off once we know link_speed. For
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@ -452,9 +447,7 @@ s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
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}
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/* Negotiate the fc mode to use */
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ret_val = ixgbe_fc_autoneg(hw);
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if (ret_val == IXGBE_ERR_FLOW_CONTROL)
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goto out;
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ixgbe_fc_autoneg(hw);
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/* Disable any previous flow control settings */
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fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
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@ -516,28 +509,27 @@ s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
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IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
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/* Set up and enable Rx high/low water mark thresholds, enable XON. */
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if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
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reg = hw->fc.low_water << 6;
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if (hw->fc.send_xon)
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reg |= IXGBE_FCRTL_XONE;
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
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hw->fc.high_water[i]) {
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fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
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fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
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} else {
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
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}
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IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
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reg = hw->fc.high_water[packetbuf_num] << 6;
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reg |= IXGBE_FCRTH_FCEN;
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IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
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}
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/* Configure pause time (2 TCs per register) */
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reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
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if ((packetbuf_num & 1) == 0)
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reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
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else
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reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
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IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
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reg = hw->fc.pause_time * 0x00010001;
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for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
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IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
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IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
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/* Configure flow control refresh threshold value */
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IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
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out:
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return ret_val;
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@ -1325,15 +1317,15 @@ void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
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for (i = 0; ((i < hw->mac.max_tx_queues) &&
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(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
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regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
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regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
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IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
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}
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for (i = 0; ((i < hw->mac.max_rx_queues) &&
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(i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
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regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
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regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
|
||||
IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
|
||||
regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
|
||||
IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
|
||||
}
|
||||
|
||||
|
||||
@ -36,7 +36,7 @@
|
||||
#define _IXGBE_82598_H_
|
||||
|
||||
u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
|
||||
s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
|
||||
void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
|
||||
|
||||
@ -243,6 +243,7 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
|
||||
|
||||
/* RAR, Multicast, VLAN */
|
||||
mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
|
||||
mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
|
||||
mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
|
||||
mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
|
||||
mac->rar_highwater = 1;
|
||||
@ -304,7 +305,9 @@ s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
|
||||
|
||||
/* Check if 1G SFP module. */
|
||||
if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
|
||||
hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
|
||||
hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
|
||||
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
|
||||
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
|
||||
*speed = IXGBE_LINK_SPEED_1GB_FULL;
|
||||
*negotiation = TRUE;
|
||||
goto out;
|
||||
@ -420,6 +423,7 @@ enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
|
||||
case IXGBE_DEV_ID_82599_SFP:
|
||||
case IXGBE_DEV_ID_82599_SFP_FCOE:
|
||||
case IXGBE_DEV_ID_82599_SFP_EM:
|
||||
case IXGBE_DEV_ID_82599_SFP_SF2:
|
||||
case IXGBE_DEV_ID_82599EN_SFP:
|
||||
media_type = ixgbe_media_type_fiber;
|
||||
break;
|
||||
@ -1088,6 +1092,9 @@ mac_reset_top:
|
||||
hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
|
||||
hw->mac.san_addr, 0, IXGBE_RAH_AV);
|
||||
|
||||
/* Save the SAN MAC RAR index */
|
||||
hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
|
||||
|
||||
/* Reserve the last RAR for the SAN MAC address */
|
||||
hw->mac.num_rar_entries--;
|
||||
}
|
||||
@ -2037,6 +2044,8 @@ sfp_check:
|
||||
physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
|
||||
else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
|
||||
physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
|
||||
else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
|
||||
physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
@ -2233,3 +2242,4 @@ static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -118,6 +118,7 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
|
||||
case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
|
||||
case IXGBE_DEV_ID_82599_SFP_FCOE:
|
||||
case IXGBE_DEV_ID_82599_SFP_EM:
|
||||
case IXGBE_DEV_ID_82599_SFP_SF2:
|
||||
case IXGBE_DEV_ID_82599EN_SFP:
|
||||
case IXGBE_DEV_ID_82599_CX4:
|
||||
case IXGBE_DEV_ID_82599_T3_LOM:
|
||||
@ -130,6 +131,7 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
|
||||
hw->mac.type = ixgbe_mac_X540_vf;
|
||||
break;
|
||||
case IXGBE_DEV_ID_X540T:
|
||||
case IXGBE_DEV_ID_X540T1:
|
||||
hw->mac.type = ixgbe_mac_X540;
|
||||
break;
|
||||
default:
|
||||
@ -811,6 +813,18 @@ s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
|
||||
{
|
||||
return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
|
||||
IXGBE_NOT_IMPLEMENTED);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
|
||||
* @hw: pointer to hardware structure
|
||||
* @vmdq: VMDq default pool index
|
||||
**/
|
||||
s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
|
||||
{
|
||||
return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
|
||||
(hw, vmdq), IXGBE_NOT_IMPLEMENTED);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -960,13 +974,12 @@ s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
|
||||
/**
|
||||
* ixgbe_fc_enable - Enable flow control
|
||||
* @hw: pointer to hardware structure
|
||||
* @packetbuf_num: packet buffer number (0-7)
|
||||
*
|
||||
* Configures the flow control settings based on SW configuration.
|
||||
**/
|
||||
s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
|
||||
s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
|
||||
{
|
||||
return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num),
|
||||
return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
|
||||
IXGBE_NOT_IMPLEMENTED);
|
||||
}
|
||||
|
||||
@ -1102,7 +1115,7 @@ u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics
|
||||
* ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
|
||||
* @hw: pointer to hardware structure
|
||||
* @regval: bitfield to write to the Rx DMA register
|
||||
*
|
||||
|
||||
@ -104,6 +104,7 @@ s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
|
||||
u32 enable_addr);
|
||||
s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
|
||||
s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
|
||||
s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
|
||||
s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
|
||||
s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
|
||||
u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
|
||||
@ -120,7 +121,7 @@ s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
|
||||
u32 vind, bool vlan_on);
|
||||
s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
|
||||
bool vlan_on, bool *vfta_changed);
|
||||
s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num);
|
||||
s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
|
||||
u8 ver);
|
||||
void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -42,7 +42,7 @@
|
||||
IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
|
||||
} while (0)
|
||||
|
||||
u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
|
||||
u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
|
||||
@ -95,8 +95,8 @@ s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
|
||||
s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packtetbuf_num);
|
||||
s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
|
||||
s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
|
||||
void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
|
||||
|
||||
s32 ixgbe_validate_mac_addr(u8 *mac_addr);
|
||||
s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
|
||||
@ -110,6 +110,7 @@ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
|
||||
s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
|
||||
|
||||
s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
|
||||
s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);
|
||||
s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
|
||||
s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
|
||||
s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
|
||||
|
||||
@ -55,6 +55,7 @@
|
||||
#include <dev/pci/pcireg.h>
|
||||
|
||||
#define ASSERT(x) if(!(x)) panic("IXGBE: x")
|
||||
#define EWARN(H, W, S) printf(W)
|
||||
|
||||
/* The happy-fun DELAY macro is defined in /usr/src/sys/i386/include/clock.h */
|
||||
#define usec_delay(x) DELAY(x)
|
||||
@ -110,6 +111,14 @@ typedef uint64_t u64;
|
||||
typedef boolean_t bool;
|
||||
#endif
|
||||
|
||||
/* shared code requires this */
|
||||
#define __le16 u16
|
||||
#define __le32 u32
|
||||
#define __le64 u64
|
||||
#define __be16 u16
|
||||
#define __be32 u32
|
||||
#define __be64 u64
|
||||
|
||||
#define le16_to_cpu
|
||||
|
||||
#if __FreeBSD_version < 800000
|
||||
|
||||
@ -1020,6 +1020,8 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
|
||||
* 8 SFP_act_lmt_DA_CORE1 - 82599-specific
|
||||
* 9 SFP_1g_cu_CORE0 - 82599-specific
|
||||
* 10 SFP_1g_cu_CORE1 - 82599-specific
|
||||
* 11 SFP_1g_sx_CORE0 - 82599-specific
|
||||
* 12 SFP_1g_sx_CORE1 - 82599-specific
|
||||
*/
|
||||
if (hw->mac.type == ixgbe_mac_82598EB) {
|
||||
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
|
||||
@ -1070,6 +1072,13 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
|
||||
else
|
||||
hw->phy.sfp_type =
|
||||
ixgbe_sfp_type_1g_cu_core1;
|
||||
} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
|
||||
if (hw->bus.lan_id == 0)
|
||||
hw->phy.sfp_type =
|
||||
ixgbe_sfp_type_1g_sx_core0;
|
||||
else
|
||||
hw->phy.sfp_type =
|
||||
ixgbe_sfp_type_1g_sx_core1;
|
||||
} else {
|
||||
hw->phy.sfp_type = ixgbe_sfp_type_unknown;
|
||||
}
|
||||
@ -1162,7 +1171,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
|
||||
/* Verify supported 1G SFP modules */
|
||||
if (comp_codes_10g == 0 &&
|
||||
!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
|
||||
hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
|
||||
hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
|
||||
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
|
||||
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
|
||||
hw->phy.type = ixgbe_phy_sfp_unsupported;
|
||||
status = IXGBE_ERR_SFP_NOT_SUPPORTED;
|
||||
goto out;
|
||||
@ -1177,14 +1188,31 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
|
||||
ixgbe_get_device_caps(hw, &enforce_sfp);
|
||||
if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
|
||||
!((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
|
||||
(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
|
||||
(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
|
||||
(hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
|
||||
(hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
|
||||
/* Make sure we're a supported PHY type */
|
||||
if (hw->phy.type == ixgbe_phy_sfp_intel) {
|
||||
status = IXGBE_SUCCESS;
|
||||
} else {
|
||||
DEBUGOUT("SFP+ module not supported\n");
|
||||
hw->phy.type = ixgbe_phy_sfp_unsupported;
|
||||
status = IXGBE_ERR_SFP_NOT_SUPPORTED;
|
||||
if (hw->allow_unsupported_sfp == TRUE) {
|
||||
EWARN(hw, "WARNING: Intel (R) Network "
|
||||
"Connections are quality tested "
|
||||
"using Intel (R) Ethernet Optics."
|
||||
" Using untested modules is not "
|
||||
"supported and may cause unstable"
|
||||
" operation or damage to the "
|
||||
"module or the adapter. Intel "
|
||||
"Corporation is not responsible "
|
||||
"for any harm caused by using "
|
||||
"untested modules.\n", status);
|
||||
status = IXGBE_SUCCESS;
|
||||
} else {
|
||||
DEBUGOUT("SFP+ module not supported\n");
|
||||
hw->phy.type =
|
||||
ixgbe_phy_sfp_unsupported;
|
||||
status = IXGBE_ERR_SFP_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
status = IXGBE_SUCCESS;
|
||||
@ -1238,10 +1266,12 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
|
||||
* SR modules
|
||||
*/
|
||||
if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
|
||||
sfp_type == ixgbe_sfp_type_1g_cu_core0)
|
||||
sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
|
||||
sfp_type == ixgbe_sfp_type_1g_sx_core0)
|
||||
sfp_type = ixgbe_sfp_type_srlr_core0;
|
||||
else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
|
||||
sfp_type == ixgbe_sfp_type_1g_cu_core1)
|
||||
sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
|
||||
sfp_type == ixgbe_sfp_type_1g_sx_core1)
|
||||
sfp_type = ixgbe_sfp_type_srlr_core1;
|
||||
|
||||
/* Read offset to PHY init contents */
|
||||
@ -1715,15 +1745,24 @@ static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
|
||||
**/
|
||||
static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
|
||||
{
|
||||
u32 i = 0;
|
||||
u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
|
||||
u32 i2cctl_r = 0;
|
||||
|
||||
DEBUGFUNC("ixgbe_raise_i2c_clk");
|
||||
|
||||
*i2cctl |= IXGBE_I2C_CLK_OUT;
|
||||
for (i = 0; i < timeout; i++) {
|
||||
*i2cctl |= IXGBE_I2C_CLK_OUT;
|
||||
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
|
||||
IXGBE_WRITE_FLUSH(hw);
|
||||
/* SCL rise time (1000ns) */
|
||||
usec_delay(IXGBE_I2C_T_RISE);
|
||||
|
||||
/* SCL rise time (1000ns) */
|
||||
usec_delay(IXGBE_I2C_T_RISE);
|
||||
i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
|
||||
if (i2cctl_r & IXGBE_I2C_CLK_IN)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1840,7 +1879,7 @@ void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_tn_check_overtemp - Checks if an overtemp occured.
|
||||
* ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Checks if the LASI temp alarm status was triggered due to overtemp
|
||||
|
||||
@ -66,12 +66,14 @@
|
||||
#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
|
||||
#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
|
||||
#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
|
||||
#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
|
||||
#define IXGBE_DEV_ID_82599EN_SFP 0x1557
|
||||
#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
|
||||
#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
|
||||
#define IXGBE_DEV_ID_82599_VF 0x10ED
|
||||
#define IXGBE_DEV_ID_X540_VF 0x1515
|
||||
#define IXGBE_DEV_ID_X540T 0x1528
|
||||
#define IXGBE_DEV_ID_X540T1 0x1560
|
||||
|
||||
/* General Registers */
|
||||
#define IXGBE_CTRL 0x00000
|
||||
@ -118,6 +120,8 @@
|
||||
#define IXGBE_I2C_CLK_OUT 0x00000002
|
||||
#define IXGBE_I2C_DATA_IN 0x00000004
|
||||
#define IXGBE_I2C_DATA_OUT 0x00000008
|
||||
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
|
||||
|
||||
|
||||
/* Interrupt Registers */
|
||||
#define IXGBE_EICR 0x00800
|
||||
@ -832,6 +836,7 @@
|
||||
#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
|
||||
#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
|
||||
IXGBE_GCR_EXT_VT_MODE_64)
|
||||
#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003
|
||||
/* Time Sync Registers */
|
||||
#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
|
||||
#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
|
||||
@ -852,6 +857,8 @@
|
||||
#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
|
||||
#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
|
||||
#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
|
||||
#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */
|
||||
#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */
|
||||
#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
|
||||
#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
|
||||
#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
|
||||
@ -1071,14 +1078,16 @@
|
||||
#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */
|
||||
#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */
|
||||
#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */
|
||||
#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* Rx wr Desc Relax Order */
|
||||
#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* Rx Split Header RO */
|
||||
#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
|
||||
#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
|
||||
|
||||
#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
|
||||
#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
|
||||
#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
|
||||
#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
|
||||
#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
|
||||
#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
|
||||
#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
|
||||
#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
|
||||
#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
|
||||
|
||||
/* MSCA Bit Masks */
|
||||
@ -1382,6 +1391,7 @@ enum {
|
||||
#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
|
||||
#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
|
||||
#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */
|
||||
#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */
|
||||
#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
|
||||
#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
|
||||
#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
|
||||
@ -1399,6 +1409,7 @@ enum {
|
||||
#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
|
||||
#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
|
||||
#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
|
||||
#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
|
||||
#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
|
||||
#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
|
||||
#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
|
||||
@ -1417,6 +1428,7 @@ enum {
|
||||
#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
|
||||
#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
|
||||
#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */
|
||||
#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
|
||||
#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
|
||||
#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
|
||||
#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
|
||||
@ -1434,6 +1446,7 @@ enum {
|
||||
#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
|
||||
#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
|
||||
#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
|
||||
#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
|
||||
#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
|
||||
#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
|
||||
#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
|
||||
@ -1519,6 +1532,7 @@ enum {
|
||||
#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
|
||||
#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
|
||||
#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
|
||||
#define IXGBE_ETQF_POOL_SHIFT 20
|
||||
|
||||
#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
|
||||
#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
|
||||
@ -1573,8 +1587,17 @@ enum {
|
||||
#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
|
||||
#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
|
||||
#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
|
||||
#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
|
||||
#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */
|
||||
#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */
|
||||
#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */
|
||||
#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */
|
||||
#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */
|
||||
#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
|
||||
#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */
|
||||
#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */
|
||||
#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */
|
||||
#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */
|
||||
|
||||
|
||||
/* LEDCTL Bit Masks */
|
||||
#define IXGBE_LED_IVRT_BASE 0x00000040
|
||||
@ -1777,7 +1800,9 @@ enum {
|
||||
#define IXGBE_DEVICE_CAPS 0x2C
|
||||
#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
|
||||
#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
|
||||
#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
|
||||
#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
|
||||
#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
|
||||
|
||||
/* MSI-X capability fields masks */
|
||||
#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
|
||||
@ -1872,6 +1897,7 @@ enum {
|
||||
#define IXGBE_PCI_LINK_SPEED 0xF
|
||||
#define IXGBE_PCI_LINK_SPEED_2500 0x1
|
||||
#define IXGBE_PCI_LINK_SPEED_5000 0x2
|
||||
#define IXGBE_PCI_LINK_SPEED_8000 0x3
|
||||
#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
|
||||
#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
|
||||
#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
|
||||
@ -1934,6 +1960,10 @@ enum {
|
||||
#define IXGBE_RXDCTL_RLPML_EN 0x00008000
|
||||
#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
|
||||
|
||||
#define IXGBE_TSAUXC_EN_CLK 0x00000004
|
||||
#define IXGBE_TSAUXC_SYNCLK 0x00000008
|
||||
#define IXGBE_TSAUXC_SDP0_INT 0x00000040
|
||||
|
||||
#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
|
||||
#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */
|
||||
|
||||
@ -1977,8 +2007,7 @@ enum {
|
||||
#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
|
||||
#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
|
||||
#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
|
||||
#define IXGBE_MFLCN_RPFCM 0x00000004 /* Receive Priority FC Mode */
|
||||
#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF0 /* Rx Priority FC bitmap mask */
|
||||
#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */
|
||||
#define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */
|
||||
|
||||
/* Multiple Receive Queue Control */
|
||||
@ -2513,13 +2542,14 @@ typedef u32 ixgbe_physical_layer;
|
||||
#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
|
||||
#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
|
||||
#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
|
||||
#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000
|
||||
|
||||
/* Flow Control Data Sheet defined values
|
||||
* Calculation and defines taken from 802.1bb Annex O
|
||||
*/
|
||||
|
||||
/* BitTimes (BT) conversion */
|
||||
#define IXGBE_BT2KB(BT) ((BT + 1023) / (8 * 1024))
|
||||
#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
|
||||
#define IXGBE_B2BT(BT) (BT * 8)
|
||||
|
||||
/* Calculate Delay to respond to PFC */
|
||||
@ -2550,24 +2580,31 @@ typedef u32 ixgbe_physical_layer;
|
||||
#define IXGBE_PCI_DELAY 10000
|
||||
|
||||
/* Calculate X540 delay value in bit times */
|
||||
#define IXGBE_FILL_RATE (36 / 25)
|
||||
|
||||
#define IXGBE_DV_X540(LINK, TC) (IXGBE_FILL_RATE * \
|
||||
(IXGBE_B2BT(LINK) + IXGBE_PFC_D + \
|
||||
(2 * IXGBE_CABLE_DC) + \
|
||||
(2 * IXGBE_ID_X540) + \
|
||||
IXGBE_HD + IXGBE_B2BT(TC)))
|
||||
#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
|
||||
((36 * \
|
||||
(IXGBE_B2BT(_max_frame_link) + \
|
||||
IXGBE_PFC_D + \
|
||||
(2 * IXGBE_CABLE_DC) + \
|
||||
(2 * IXGBE_ID_X540) + \
|
||||
IXGBE_HD) / 25 + 1) + \
|
||||
2 * IXGBE_B2BT(_max_frame_tc))
|
||||
|
||||
/* Calculate 82599, 82598 delay value in bit times */
|
||||
#define IXGBE_DV(LINK, TC) (IXGBE_FILL_RATE * \
|
||||
(IXGBE_B2BT(LINK) + IXGBE_PFC_D + \
|
||||
(2 * IXGBE_CABLE_DC) + (2 * IXGBE_ID) + \
|
||||
IXGBE_HD + IXGBE_B2BT(TC)))
|
||||
#define IXGBE_DV(_max_frame_link, _max_frame_tc) \
|
||||
((36 * \
|
||||
(IXGBE_B2BT(_max_frame_link) + \
|
||||
IXGBE_PFC_D + \
|
||||
(2 * IXGBE_CABLE_DC) + \
|
||||
(2 * IXGBE_ID) + \
|
||||
IXGBE_HD) / 25 + 1) + \
|
||||
2 * IXGBE_B2BT(_max_frame_tc))
|
||||
|
||||
/* Calculate low threshold delay values */
|
||||
#define IXGBE_LOW_DV_X540(TC) (2 * IXGBE_B2BT(TC) + \
|
||||
(IXGBE_FILL_RATE * IXGBE_PCI_DELAY))
|
||||
#define IXGBE_LOW_DV(TC) (2 * IXGBE_LOW_DV_X540(TC))
|
||||
#define IXGBE_LOW_DV_X540(_max_frame_tc) \
|
||||
(2 * IXGBE_B2BT(_max_frame_tc) + \
|
||||
(36 * IXGBE_PCI_DELAY / 25) + 1)
|
||||
#define IXGBE_LOW_DV(_max_frame_tc) \
|
||||
(2 * IXGBE_LOW_DV_X540(_max_frame_tc))
|
||||
|
||||
/* Software ATR hash keys */
|
||||
#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
|
||||
@ -2711,6 +2748,8 @@ enum ixgbe_sfp_type {
|
||||
ixgbe_sfp_type_da_act_lmt_core1 = 8,
|
||||
ixgbe_sfp_type_1g_cu_core0 = 9,
|
||||
ixgbe_sfp_type_1g_cu_core1 = 10,
|
||||
ixgbe_sfp_type_1g_sx_core0 = 11,
|
||||
ixgbe_sfp_type_1g_sx_core1 = 12,
|
||||
ixgbe_sfp_type_not_present = 0xFFFE,
|
||||
ixgbe_sfp_type_unknown = 0xFFFF
|
||||
};
|
||||
@ -2760,6 +2799,7 @@ enum ixgbe_bus_speed {
|
||||
ixgbe_bus_speed_133 = 133,
|
||||
ixgbe_bus_speed_2500 = 2500,
|
||||
ixgbe_bus_speed_5000 = 5000,
|
||||
ixgbe_bus_speed_8000 = 8000,
|
||||
ixgbe_bus_speed_reserved
|
||||
};
|
||||
|
||||
@ -2796,7 +2836,7 @@ struct ixgbe_bus_info {
|
||||
/* Flow control parameters */
|
||||
struct ixgbe_fc_info {
|
||||
u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
|
||||
u32 low_water; /* Flow Control Low-water */
|
||||
u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
|
||||
u16 pause_time; /* Flow Control Pause timer */
|
||||
bool send_xon; /* Flow control send XON */
|
||||
bool strict_ieee; /* Strict IEEE mode */
|
||||
@ -2955,6 +2995,7 @@ struct ixgbe_mac_operations {
|
||||
s32 (*clear_rar)(struct ixgbe_hw *, u32);
|
||||
s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
|
||||
s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
|
||||
s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
|
||||
s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
|
||||
s32 (*init_rx_addrs)(struct ixgbe_hw *);
|
||||
s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
|
||||
@ -2971,7 +3012,7 @@ struct ixgbe_mac_operations {
|
||||
void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
|
||||
|
||||
/* Flow Control */
|
||||
s32 (*fc_enable)(struct ixgbe_hw *, s32);
|
||||
s32 (*fc_enable)(struct ixgbe_hw *);
|
||||
|
||||
/* Manageability interface */
|
||||
s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
|
||||
@ -3027,11 +3068,11 @@ struct ixgbe_mac_info {
|
||||
u32 rx_pb_size;
|
||||
u32 max_tx_queues;
|
||||
u32 max_rx_queues;
|
||||
u32 max_msix_vectors;
|
||||
bool msix_vectors_from_pcie;
|
||||
u32 orig_autoc;
|
||||
bool arc_subsystem_valid;
|
||||
u8 san_mac_rar_index;
|
||||
u32 orig_autoc2;
|
||||
u16 max_msix_vectors;
|
||||
bool arc_subsystem_valid;
|
||||
bool orig_link_settings_stored;
|
||||
bool autotry_restart;
|
||||
u8 flags;
|
||||
@ -3102,6 +3143,7 @@ struct ixgbe_hw {
|
||||
u8 revision_id;
|
||||
bool adapter_stopped;
|
||||
bool force_full_reset;
|
||||
bool allow_unsupported_sfp;
|
||||
};
|
||||
|
||||
#define ixgbe_call_func(hw, func, params, error) \
|
||||
@ -3138,7 +3180,6 @@ struct ixgbe_hw {
|
||||
#define IXGBE_ERR_OVERTEMP -26
|
||||
#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
|
||||
#define IXGBE_ERR_FC_NOT_SUPPORTED -28
|
||||
#define IXGBE_ERR_FLOW_CONTROL -29
|
||||
#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
|
||||
#define IXGBE_ERR_PBA_SECTION -31
|
||||
#define IXGBE_ERR_INVALID_ARGUMENT -32
|
||||
|
||||
@ -366,6 +366,7 @@ s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
|
||||
{
|
||||
struct ixgbe_mbx_info *mbx = &hw->mbx;
|
||||
u32 msgbuf[2];
|
||||
s32 ret_val;
|
||||
UNREFERENCED_1PARAMETER(vind);
|
||||
|
||||
msgbuf[0] = IXGBE_VF_SET_VLAN;
|
||||
@ -373,7 +374,14 @@ s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
|
||||
/* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
|
||||
msgbuf[0] |= vlan_on << IXGBE_VT_MSGINFO_SHIFT;
|
||||
|
||||
return mbx->ops.write_posted(hw, msgbuf, 2, 0);
|
||||
ret_val = mbx->ops.write_posted(hw, msgbuf, 2, 0);
|
||||
if (!ret_val)
|
||||
ret_val = mbx->ops.read_posted(hw, msgbuf, 1, 0);
|
||||
|
||||
if (!ret_val && (msgbuf[0] & IXGBE_VT_MSGTYPE_ACK))
|
||||
return IXGBE_SUCCESS;
|
||||
|
||||
return ret_val | (msgbuf[0] & IXGBE_VT_MSGTYPE_NACK);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -491,11 +499,17 @@ s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
|
||||
else
|
||||
*link_up = FALSE;
|
||||
|
||||
if ((links_reg & IXGBE_LINKS_SPEED_10G_82599) ==
|
||||
IXGBE_LINKS_SPEED_10G_82599)
|
||||
switch (links_reg & IXGBE_LINKS_SPEED_10G_82599) {
|
||||
case IXGBE_LINKS_SPEED_10G_82599:
|
||||
*speed = IXGBE_LINK_SPEED_10GB_FULL;
|
||||
else
|
||||
break;
|
||||
case IXGBE_LINKS_SPEED_1G_82599:
|
||||
*speed = IXGBE_LINK_SPEED_1GB_FULL;
|
||||
break;
|
||||
case IXGBE_LINKS_SPEED_100_82599:
|
||||
*speed = IXGBE_LINK_SPEED_100_FULL;
|
||||
break;
|
||||
}
|
||||
|
||||
return IXGBE_SUCCESS;
|
||||
}
|
||||
|
||||
@ -98,6 +98,7 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
|
||||
|
||||
/* RAR, Multicast, VLAN */
|
||||
mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
|
||||
mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
|
||||
mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
|
||||
mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
|
||||
mac->rar_highwater = 1;
|
||||
@ -262,6 +263,9 @@ mac_reset_top:
|
||||
hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
|
||||
hw->mac.san_addr, 0, IXGBE_RAH_AV);
|
||||
|
||||
/* Save the SAN MAC RAR index */
|
||||
hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
|
||||
|
||||
/* Reserve the last RAR for the SAN MAC address */
|
||||
hw->mac.num_rar_entries--;
|
||||
}
|
||||
@ -798,7 +802,7 @@ out:
|
||||
* @hw: pointer to hardware structure
|
||||
* @mask: Mask to specify which semaphore to release
|
||||
*
|
||||
* Releases the SWFW semaphore throught the SW_FW_SYNC register
|
||||
* Releases the SWFW semaphore through the SW_FW_SYNC register
|
||||
* for the specified function (CSR, PHY0, PHY1, EVM, Flash)
|
||||
**/
|
||||
void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
|
||||
|
||||
@ -42,7 +42,7 @@
|
||||
/*********************************************************************
|
||||
* Driver version
|
||||
*********************************************************************/
|
||||
char ixv_driver_version[] = "1.1.2";
|
||||
char ixv_driver_version[] = "1.1.4";
|
||||
|
||||
/*********************************************************************
|
||||
* PCI Device ID Table
|
||||
@ -386,7 +386,7 @@ ixv_attach(device_t dev)
|
||||
/* Get Hardware Flow Control setting */
|
||||
hw->fc.requested_mode = ixgbe_fc_full;
|
||||
hw->fc.pause_time = IXV_FC_PAUSE;
|
||||
hw->fc.low_water = IXV_FC_LO;
|
||||
hw->fc.low_water[0] = IXV_FC_LO;
|
||||
hw->fc.high_water[0] = IXV_FC_HI;
|
||||
hw->fc.send_xon = TRUE;
|
||||
|
||||
@ -2299,7 +2299,7 @@ ixv_initialize_transmit_units(struct adapter *adapter)
|
||||
adapter->num_tx_desc *
|
||||
sizeof(struct ixgbe_legacy_tx_desc));
|
||||
txctrl = IXGBE_READ_REG(hw, IXGBE_VFDCA_TXCTRL(i));
|
||||
txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
|
||||
txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
|
||||
IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), txctrl);
|
||||
break;
|
||||
}
|
||||
@ -4004,7 +4004,7 @@ ixv_set_flowcntl(SYSCTL_HANDLER_ARGS)
|
||||
adapter->hw.fc.requested_mode = ixgbe_fc_none;
|
||||
}
|
||||
|
||||
ixgbe_fc_enable(&adapter->hw, 0);
|
||||
ixgbe_fc_enable(&adapter->hw);
|
||||
return error;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user