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Adapt libstand's setjmp/longjmp MIPS support to be portable across 32-bit

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and 64-bit MIPS.  Don't use the floating-point coprocessor in the libstand
context for MIPS.

Reviewed by:	imp
MFC after:	3 days
Sponsored by:	DARPA, AFRL
This commit is contained in:
Robert Watson 2013-04-16 17:03:35 +00:00
parent 6c81895dab
commit 909735d975
1 changed files with 27 additions and 56 deletions
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83
lib/libstand/mips/_setjmp.S
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@ -59,33 +59,20 @@
LEAF(_setjmp)
.set noreorder
li v0, 0xACEDBADE # sigcontext magic number
sw ra, (2 * 4)(a0) # sc_pc = return address
sw v0, (3 * 4)(a0) # saved in sc_regs[0]
sw s0, ((S0 + 3) * 4)(a0)
sw s1, ((S1 + 3) * 4)(a0)
sw s2, ((S2 + 3) * 4)(a0)
sw s3, ((S3 + 3) * 4)(a0)
sw s4, ((S4 + 3) * 4)(a0)
sw s5, ((S5 + 3) * 4)(a0)
sw s6, ((S6 + 3) * 4)(a0)
sw s7, ((S7 + 3) * 4)(a0)
sw sp, ((SP + 3) * 4)(a0)
sw s8, ((S8 + 3) * 4)(a0)
cfc1 v0, $31 # too bad cant check if FP used
swc1 $f20, ((20 + 38) * 4)(a0)
swc1 $f21, ((21 + 38) * 4)(a0)
swc1 $f22, ((22 + 38) * 4)(a0)
swc1 $f23, ((23 + 38) * 4)(a0)
swc1 $f24, ((24 + 38) * 4)(a0)
swc1 $f25, ((25 + 38) * 4)(a0)
swc1 $f26, ((26 + 38) * 4)(a0)
swc1 $f27, ((27 + 38) * 4)(a0)
swc1 $f28, ((28 + 38) * 4)(a0)
swc1 $f29, ((29 + 38) * 4)(a0)
swc1 $f30, ((30 + 38) * 4)(a0)
swc1 $f31, ((31 + 38) * 4)(a0)
sw v0, ((32 + 38) * 4)(a0)
REG_LI v0, 0xACEDBADE # sigcontext magic number
REG_S ra, (2 * SZREG)(a0) # sc_pc = return address
REG_S v0, (3 * SZREG)(a0) # saved in sc_regs[0]
REG_S s0, ((S0 + 3) * SZREG)(a0)
REG_S s1, ((S1 + 3) * SZREG)(a0)
REG_S s2, ((S2 + 3) * SZREG)(a0)
REG_S s3, ((S3 + 3) * SZREG)(a0)
REG_S s4, ((S4 + 3) * SZREG)(a0)
REG_S s5, ((S5 + 3) * SZREG)(a0)
REG_S s6, ((S6 + 3) * SZREG)(a0)
REG_S s7, ((S7 + 3) * SZREG)(a0)
REG_S sp, ((SP + 3) * SZREG)(a0)
REG_S s8, ((S8 + 3) * SZREG)(a0)
REG_S v0, ((32 + 38) * SZREG)(a0)
j ra
move v0, zero
END(_setjmp)
@ -96,38 +83,22 @@ LEAF(_longjmp)
.cprestore 16
#endif
.set noreorder
lw v0, (3 * 4)(a0) # get magic number
lw ra, (2 * 4)(a0)
REG_L v0, (3 * SZREG)(a0) # get magic number
REG_L ra, (2 * SZREG)(a0)
bne v0, 0xACEDBADE, botch # jump if error
addu sp, sp, 32 # does not matter, sanity
lw s0, ((S0 + 3) * 4)(a0)
lw s1, ((S1 + 3) * 4)(a0)
lw s2, ((S2 + 3) * 4)(a0)
lw s3, ((S3 + 3) * 4)(a0)
lw s4, ((S4 + 3) * 4)(a0)
lw s5, ((S5 + 3) * 4)(a0)
lw s6, ((S6 + 3) * 4)(a0)
lw s7, ((S7 + 3) * 4)(a0)
lw v0, ((32 + 38) * 4)(a0) # get fpu status
lw sp, ((SP + 3) * 4)(a0)
lw s8, ((S8 + 3) * 4)(a0)
/* Octeon does not have an FPU */
#if !defined(_MIPS_ARCH_OCTEON)
ctc1 v0, $31
lwc1 $f20, ((20 + 38) * 4)(a0)
lwc1 $f21, ((21 + 38) * 4)(a0)
lwc1 $f22, ((22 + 38) * 4)(a0)
lwc1 $f23, ((23 + 38) * 4)(a0)
lwc1 $f24, ((24 + 38) * 4)(a0)
lwc1 $f25, ((25 + 38) * 4)(a0)
lwc1 $f26, ((26 + 38) * 4)(a0)
lwc1 $f27, ((27 + 38) * 4)(a0)
lwc1 $f28, ((28 + 38) * 4)(a0)
lwc1 $f29, ((29 + 38) * 4)(a0)
lwc1 $f30, ((30 + 38) * 4)(a0)
lwc1 $f31, ((31 + 38) * 4)(a0)
#endif /* _MIPS_ARCH_OCTEON */
REG_L s0, ((S0 + 3) * SZREG)(a0)
REG_L s1, ((S1 + 3) * SZREG)(a0)
REG_L s2, ((S2 + 3) * SZREG)(a0)
REG_L s3, ((S3 + 3) * SZREG)(a0)
REG_L s4, ((S4 + 3) * SZREG)(a0)
REG_L s5, ((S5 + 3) * SZREG)(a0)
REG_L s6, ((S6 + 3) * SZREG)(a0)
REG_L s7, ((S7 + 3) * SZREG)(a0)
REG_L v0, ((32 + 38) * SZREG)(a0) # get fpu status
REG_L sp, ((SP + 3) * SZREG)(a0)
REG_L s8, ((S8 + 3) * SZREG)(a0)
j ra
move v0, a1