Backport Intel Core 2 and AMD Geode CPU types from gcc-4.3 (GPLv2)
These options are supported in this shape in all newer GCC versions. PR: gnu/155308 Obtained from: gcc 4.3 (rev. 118090, 118973, 120846; GPLv2) MFC after: 2 weeks
This commit is contained in:
Martin Matuska
parent
dd5759bf72
commit
91b1eb9429
@ -1207,14 +1207,14 @@ i[34567]86-*-solaris2*)
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# FIXME: -m64 for i[34567]86-*-* should be allowed just
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# like -m32 for x86_64-*-*.
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case X"${with_cpu}" in
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Xgeneric|Xnocona|Xx86-64|Xk8|Xopteron|Xathlon64|Xathlon-fx)
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Xgeneric|Xcore2|Xnocona|Xx86-64|Xk8|Xopteron|Xathlon64|Xathlon-fx)
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;;
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X)
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with_cpu=generic
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;;
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*)
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echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
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echo "generic nocona x86-64 k8 opteron athlon64 athlon-fx" 1>&2
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echo "generic core2 nocona x86-64 k8 opteron athlon64 athlon-fx" 1>&2
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exit 1
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;;
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esac
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@ -2537,6 +2537,9 @@ if test x$with_cpu = x ; then
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nocona-*)
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with_cpu=nocona
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;;
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core2-*)
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with_cpu=core2
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;;
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pentium_m-*)
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with_cpu=pentium-m
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;;
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@ -2556,6 +2559,9 @@ if test x$with_cpu = x ; then
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nocona-*)
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with_cpu=nocona
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;;
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core2-*)
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with_cpu=core2
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;;
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*)
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with_cpu=generic
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;;
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@ -2787,7 +2793,7 @@ case "${target}" in
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esac
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# OK
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;;
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"" | k8 | opteron | athlon64 | athlon-fx | nocona | generic)
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"" | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | generic)
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# OK
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;;
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*)
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153
contrib/gcc/config/i386/geode.md
Normal file
153
contrib/gcc/config/i386/geode.md
Normal file
@ -0,0 +1,153 @@
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;; Geode Scheduling
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;; Copyright (C) 2006
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;; Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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;; Boston, MA 02110-1301, USA.
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;;
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;; The Geode architecture is one insn issue processor.
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;;
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;; This description is based on data from the following documents:
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;;
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;; "AMD Geode GX Processor Data Book"
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;; Advanced Micro Devices, Inc., Aug 2005.
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;;
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;; "AMD Geode LX Processor Data Book"
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;; Advanced Micro Devices, Inc., Jan 2006.
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;;
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;;
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;; CPU execution units of the Geode:
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;;
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;; issue describes the issue pipeline.
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;; alu describes the Integer unit
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;; fpu describes the FP unit
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;;
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;; The fp unit is out of order execution unit with register renaming.
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;; There is also memory management unit and execution pipeline for
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;; load/store operations. We ignore it and difference between insns
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;; using memory and registers.
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(define_automaton "geode")
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(define_cpu_unit "geode_issue,geode_alu,geode_fpu" "geode")
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(define_insn_reservation "alu" 1
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "alu,alu1,negnot,icmp,lea,test,imov,imovx,icmov,incdec,setcc"))
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"geode_issue,geode_alu")
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(define_insn_reservation "shift" 2
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "ishift,ishift1,rotate,rotate1,cld"))
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"geode_issue,geode_alu*2")
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(define_insn_reservation "imul" 7
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "imul"))
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"geode_issue,geode_alu*7")
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(define_insn_reservation "idiv" 40
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "idiv"))
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"geode_issue,geode_alu*40")
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;; The branch unit.
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(define_insn_reservation "call" 2
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "call,callv"))
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"geode_issue,geode_alu*2")
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(define_insn_reservation "geode_branch" 1
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "ibr"))
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"geode_issue,geode_alu")
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(define_insn_reservation "geode_pop_push" 1
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "pop,push"))
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"geode_issue,geode_alu")
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(define_insn_reservation "geode_leave" 2
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "leave"))
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"geode_issue,geode_alu*2")
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(define_insn_reservation "geode_load_str" 4
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(and (eq_attr "cpu" "geode")
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(and (eq_attr "type" "str")
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(eq_attr "memory" "load,both")))
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"geode_issue,geode_alu*4")
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(define_insn_reservation "geode_store_str" 2
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(and (eq_attr "cpu" "geode")
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(and (eq_attr "type" "str")
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(eq_attr "memory" "store")))
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"geode_issue,geode_alu*2")
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;; Be optimistic
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(define_insn_reservation "geode_unknown" 1
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "multi,other"))
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"geode_issue,geode_alu")
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;; FPU
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(define_insn_reservation "geode_fop" 6
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "fop,fcmp"))
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"geode_issue,geode_fpu*6")
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(define_insn_reservation "geode_fsimple" 1
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "fmov,fcmov,fsgn,fxch"))
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"geode_issue,geode_fpu")
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(define_insn_reservation "geode_fist" 4
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "fistp,fisttp"))
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"geode_issue,geode_fpu*4")
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(define_insn_reservation "geode_fmul" 10
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "fmul"))
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"geode_issue,geode_fpu*10")
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(define_insn_reservation "geode_fdiv" 47
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "fdiv"))
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"geode_issue,geode_fpu*47")
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;; We use minimal latency (fsin) here
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(define_insn_reservation "geode_fpspc" 54
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "fpspc"))
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"geode_issue,geode_fpu*54")
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(define_insn_reservation "geode_frndint" 12
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "frndint"))
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"geode_issue,geode_fpu*12")
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(define_insn_reservation "geode_mmxmov" 1
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "mmxmov"))
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"geode_issue,geode_fpu")
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(define_insn_reservation "geode_mmx" 2
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(and (eq_attr "cpu" "geode")
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(eq_attr "type" "mmx,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"))
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"geode_issue,geode_fpu*2")
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@ -335,6 +335,60 @@ struct processor_costs pentiumpro_cost = {
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COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
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};
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static const
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struct processor_costs geode_cost = {
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COSTS_N_INSNS (1), /* cost of an add instruction */
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COSTS_N_INSNS (1), /* cost of a lea instruction */
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COSTS_N_INSNS (2), /* variable shift costs */
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COSTS_N_INSNS (1), /* constant shift costs */
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{COSTS_N_INSNS (3), /* cost of starting multiply for QI */
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COSTS_N_INSNS (4), /* HI */
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COSTS_N_INSNS (7), /* SI */
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COSTS_N_INSNS (7), /* DI */
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COSTS_N_INSNS (7)}, /* other */
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0, /* cost of multiply per each bit set */
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{COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
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COSTS_N_INSNS (23), /* HI */
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COSTS_N_INSNS (39), /* SI */
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COSTS_N_INSNS (39), /* DI */
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COSTS_N_INSNS (39)}, /* other */
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COSTS_N_INSNS (1), /* cost of movsx */
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COSTS_N_INSNS (1), /* cost of movzx */
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8, /* "large" insn */
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4, /* MOVE_RATIO */
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1, /* cost for loading QImode using movzbl */
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{1, 1, 1}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{1, 1, 1}, /* cost of storing integer registers */
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1, /* cost of reg,reg fld/fst */
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{1, 1, 1}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode */
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{4, 6, 6}, /* cost of storing fp registers
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in SFmode, DFmode and XFmode */
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1, /* cost of moving MMX register */
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{1, 1}, /* cost of loading MMX registers
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in SImode and DImode */
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{1, 1}, /* cost of storing MMX registers
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in SImode and DImode */
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1, /* cost of moving SSE register */
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{1, 1, 1}, /* cost of loading SSE registers
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in SImode, DImode and TImode */
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{1, 1, 1}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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1, /* MMX or SSE register to integer */
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32, /* size of prefetch block */
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1, /* number of parallel prefetches */
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1, /* Branch cost */
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COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
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COSTS_N_INSNS (11), /* cost of FMUL instruction. */
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COSTS_N_INSNS (47), /* cost of FDIV instruction. */
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COSTS_N_INSNS (1), /* cost of FABS instruction. */
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COSTS_N_INSNS (1), /* cost of FCHS instruction. */
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COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
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};
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static const
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struct processor_costs k6_cost = {
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COSTS_N_INSNS (1), /* cost of an add instruction */
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@ -600,6 +654,58 @@ struct processor_costs nocona_cost = {
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COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
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};
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static const
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struct processor_costs core2_cost = {
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COSTS_N_INSNS (1), /* cost of an add instruction */
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COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
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COSTS_N_INSNS (1), /* variable shift costs */
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COSTS_N_INSNS (1), /* constant shift costs */
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{COSTS_N_INSNS (3), /* cost of starting multiply for QI */
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COSTS_N_INSNS (3), /* HI */
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COSTS_N_INSNS (3), /* SI */
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COSTS_N_INSNS (3), /* DI */
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COSTS_N_INSNS (3)}, /* other */
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0, /* cost of multiply per each bit set */
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{COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
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COSTS_N_INSNS (22), /* HI */
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COSTS_N_INSNS (22), /* SI */
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COSTS_N_INSNS (22), /* DI */
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COSTS_N_INSNS (22)}, /* other */
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COSTS_N_INSNS (1), /* cost of movsx */
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COSTS_N_INSNS (1), /* cost of movzx */
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8, /* "large" insn */
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16, /* MOVE_RATIO */
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2, /* cost for loading QImode using movzbl */
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{6, 6, 6}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{4, 4, 4}, /* cost of storing integer registers */
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2, /* cost of reg,reg fld/fst */
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{6, 6, 6}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode */
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{4, 4, 4}, /* cost of loading integer registers */
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2, /* cost of moving MMX register */
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{6, 6}, /* cost of loading MMX registers
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in SImode and DImode */
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{4, 4}, /* cost of storing MMX registers
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in SImode and DImode */
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2, /* cost of moving SSE register */
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{6, 6, 6}, /* cost of loading SSE registers
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in SImode, DImode and TImode */
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{4, 4, 4}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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2, /* MMX or SSE register to integer */
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128, /* size of prefetch block */
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8, /* number of parallel prefetches */
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3, /* Branch cost */
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COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
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COSTS_N_INSNS (5), /* cost of FMUL instruction. */
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COSTS_N_INSNS (32), /* cost of FDIV instruction. */
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COSTS_N_INSNS (1), /* cost of FABS instruction. */
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COSTS_N_INSNS (1), /* cost of FCHS instruction. */
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COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
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};
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/* Generic64 should produce code tuned for Nocona and K8. */
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static const
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struct processor_costs generic64_cost = {
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@ -721,38 +827,41 @@ const struct processor_costs *ix86_cost = &pentium_cost;
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#define m_486 (1<<PROCESSOR_I486)
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#define m_PENT (1<<PROCESSOR_PENTIUM)
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#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
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#define m_GEODE (1<<PROCESSOR_GEODE)
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#define m_K6_GEODE (m_K6 | m_GEODE)
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#define m_K6 (1<<PROCESSOR_K6)
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#define m_ATHLON (1<<PROCESSOR_ATHLON)
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#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
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#define m_K8 (1<<PROCESSOR_K8)
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#define m_ATHLON_K8 (m_K8 | m_ATHLON)
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#define m_NOCONA (1<<PROCESSOR_NOCONA)
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#define m_CORE2 (1<<PROCESSOR_CORE2)
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#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
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#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
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#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
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/* Generic instruction choice should be common subset of supported CPUs
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(PPro/PENT4/NOCONA/Athlon/K8). */
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(PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
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/* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
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Generic64 seems like good code size tradeoff. We can't enable it for 32bit
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generic because it is not working well with PPro base chips. */
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const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8 | m_GENERIC64;
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const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
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const int x86_use_leave = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_CORE2 | m_GENERIC64;
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const int x86_push_memory = m_386 | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
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const int x86_zero_extend_with_and = m_486 | m_PENT;
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const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC /* m_386 | m_K6 */;
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const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */;
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const int x86_double_with_add = ~m_386;
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const int x86_use_bit_test = m_386;
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const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_GENERIC;
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const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
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const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_CORE2 | m_GENERIC;
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const int x86_cmove = m_PPRO | m_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
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const int x86_3dnow_a = m_ATHLON_K8;
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const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
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const int x86_deep_branch = m_PPRO | m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
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/* Branch hints were put in P4 based on simulation result. But
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after P4 was made, no performance benefit was observed with
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branch hints. It also increases the code size. As the result,
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icc never generates branch hints. */
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const int x86_branch_hints = 0;
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const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */
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const int x86_use_sahf = m_PPRO | m_K6_GEODE | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */
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/* We probably ought to watch for partial register stalls on Generic32
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compilation setting as well. However in current implementation the
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partial register stalls are not eliminated very well - they can
|
||||
@ -762,15 +871,15 @@ const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_G
|
||||
with partial reg. dependencies used by Athlon/P4 based chips, it is better
|
||||
to leave it off for generic32 for now. */
|
||||
const int x86_partial_reg_stall = m_PPRO;
|
||||
const int x86_partial_flag_reg_stall = m_GENERIC;
|
||||
const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
|
||||
const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC);
|
||||
const int x86_partial_flag_reg_stall = m_CORE2 | m_GENERIC;
|
||||
const int x86_use_himode_fiop = m_386 | m_486 | m_K6_GEODE;
|
||||
const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_CORE2 | m_GENERIC);
|
||||
const int x86_use_mov0 = m_K6;
|
||||
const int x86_use_cltd = ~(m_PENT | m_K6 | m_GENERIC);
|
||||
const int x86_use_cltd = ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC);
|
||||
const int x86_read_modify_write = ~m_PENT;
|
||||
const int x86_read_modify = ~(m_PENT | m_PPRO);
|
||||
const int x86_split_long_moves = m_PPRO;
|
||||
const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_GENERIC; /* m_PENT4 ? */
|
||||
const int x86_promote_QImode = m_K6_GEODE | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_CORE2 | m_GENERIC; /* m_PENT4 ? */
|
||||
const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
|
||||
const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
|
||||
const int x86_qimode_math = ~(0);
|
||||
@ -780,18 +889,18 @@ const int x86_promote_qi_regs = 0;
|
||||
if our scheme for avoiding partial stalls was more effective. */
|
||||
const int x86_himode_math = ~(m_PPRO);
|
||||
const int x86_promote_hi_regs = m_PPRO;
|
||||
const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC;
|
||||
const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
|
||||
const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC;
|
||||
const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC;
|
||||
const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC);
|
||||
const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
|
||||
const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
|
||||
const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
|
||||
const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
|
||||
const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC;
|
||||
const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
|
||||
const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
|
||||
const int x86_add_esp_4 = m_ATHLON_K8 | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
|
||||
const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6_GEODE | m_386 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
|
||||
const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_GEODE);
|
||||
const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
|
||||
const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
|
||||
const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
|
||||
const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
|
||||
const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC;
|
||||
const int x86_shift1 = ~m_486;
|
||||
const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
|
||||
const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
|
||||
/* In Generic model we have an conflict here in between PPro/Pentium4 based chips
|
||||
that thread 128bit SSE registers as single units versus K8 based chips that
|
||||
divide SSE registers to two 64bit halves.
|
||||
@ -801,7 +910,7 @@ const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PEN
|
||||
this option on P4 brings over 20% SPECfp regression, while enabling it on
|
||||
K8 brings roughly 2.4% regression that can be partly masked by careful scheduling
|
||||
of moves. */
|
||||
const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC;
|
||||
const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
|
||||
/* Set for machines where the type and dependencies are resolved on SSE
|
||||
register parts instead of whole registers, so we may maintain just
|
||||
lower part of scalar values in proper format leaving the upper part
|
||||
@ -810,18 +919,18 @@ const int x86_sse_split_regs = m_ATHLON_K8;
|
||||
const int x86_sse_typeless_stores = m_ATHLON_K8;
|
||||
const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
|
||||
const int x86_use_ffreep = m_ATHLON_K8;
|
||||
const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
|
||||
const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_GENERIC);
|
||||
const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6_GEODE | m_CORE2;
|
||||
const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC);
|
||||
|
||||
/* ??? Allowing interunit moves makes it all too easy for the compiler to put
|
||||
integer data in xmm registers. Which results in pretty abysmal code. */
|
||||
const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;
|
||||
|
||||
const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC32;
|
||||
const int x86_ext_80387_constants = m_K6_GEODE | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC32;
|
||||
/* Some CPU cores are not able to predict more than 4 branch instructions in
|
||||
the 16 byte window. */
|
||||
const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
|
||||
const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT | m_GENERIC;
|
||||
const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC;
|
||||
const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC;
|
||||
const int x86_use_bt = m_ATHLON_K8;
|
||||
/* Compare and exchange was added for 80486. */
|
||||
const int x86_cmpxchg = ~m_386;
|
||||
@ -831,7 +940,7 @@ const int x86_cmpxchg8b = ~(m_386 | m_486);
|
||||
const int x86_cmpxchg16b = m_NOCONA;
|
||||
/* Exchange and add was added for 80486. */
|
||||
const int x86_xadd = ~m_386;
|
||||
const int x86_pad_returns = m_ATHLON_K8 | m_GENERIC;
|
||||
const int x86_pad_returns = m_ATHLON_K8 | m_CORE2 | m_GENERIC;
|
||||
|
||||
/* In case the average insn count for single function invocation is
|
||||
lower than this constant, emit fast (but longer) prologue and
|
||||
@ -1455,11 +1564,13 @@ override_options (void)
|
||||
{&i486_cost, 0, 0, 16, 15, 16, 15, 16},
|
||||
{&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
|
||||
{&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
|
||||
{&geode_cost, 0, 0, 0, 0, 0, 0, 0},
|
||||
{&k6_cost, 0, 0, 32, 7, 32, 7, 32},
|
||||
{&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
|
||||
{&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
|
||||
{&k8_cost, 0, 0, 16, 7, 16, 7, 16},
|
||||
{&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
|
||||
{&core2_cost, 0, 0, 16, 7, 16, 7, 16},
|
||||
{&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
|
||||
{&generic64_cost, 0, 0, 16, 7, 16, 7, 16}
|
||||
};
|
||||
@ -1506,6 +1617,11 @@ override_options (void)
|
||||
| PTA_MMX | PTA_PREFETCH_SSE},
|
||||
{"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
|
||||
| PTA_MMX | PTA_PREFETCH_SSE},
|
||||
{"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3
|
||||
| PTA_64BIT | PTA_MMX
|
||||
| PTA_PREFETCH_SSE},
|
||||
{"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
|
||||
| PTA_3DNOW_A},
|
||||
{"k6", PROCESSOR_K6, PTA_MMX},
|
||||
{"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
|
||||
{"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
|
||||
@ -13706,6 +13822,9 @@ ix86_issue_rate (void)
|
||||
case PROCESSOR_GENERIC64:
|
||||
return 3;
|
||||
|
||||
case PROCESSOR_CORE2:
|
||||
return 4;
|
||||
|
||||
default:
|
||||
return 1;
|
||||
}
|
||||
|
||||
@ -130,12 +130,14 @@ extern const struct processor_costs *ix86_cost;
|
||||
#define TARGET_486 (ix86_tune == PROCESSOR_I486)
|
||||
#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
|
||||
#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
|
||||
#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
|
||||
#define TARGET_K6 (ix86_tune == PROCESSOR_K6)
|
||||
#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
|
||||
#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
|
||||
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
|
||||
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
|
||||
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
|
||||
#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
|
||||
#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
|
||||
#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
|
||||
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
|
||||
@ -376,6 +378,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if (TARGET_GEODE) \
|
||||
{ \
|
||||
builtin_define ("__tune_geode__"); \
|
||||
} \
|
||||
else if (TARGET_K6) \
|
||||
{ \
|
||||
builtin_define ("__tune_k6__"); \
|
||||
@ -397,6 +403,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|
||||
builtin_define ("__tune_pentium4__"); \
|
||||
else if (TARGET_NOCONA) \
|
||||
builtin_define ("__tune_nocona__"); \
|
||||
else if (TARGET_CORE2) \
|
||||
builtin_define ("__tune_core2__"); \
|
||||
\
|
||||
if (TARGET_MMX) \
|
||||
builtin_define ("__MMX__"); \
|
||||
@ -437,6 +445,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|
||||
builtin_define ("__pentiumpro"); \
|
||||
builtin_define ("__pentiumpro__"); \
|
||||
} \
|
||||
else if (ix86_arch == PROCESSOR_GEODE) \
|
||||
{ \
|
||||
builtin_define ("__geode"); \
|
||||
builtin_define ("__geode__"); \
|
||||
} \
|
||||
else if (ix86_arch == PROCESSOR_K6) \
|
||||
{ \
|
||||
\
|
||||
@ -470,6 +483,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|
||||
builtin_define ("__nocona"); \
|
||||
builtin_define ("__nocona__"); \
|
||||
} \
|
||||
else if (ix86_arch == PROCESSOR_CORE2) \
|
||||
{ \
|
||||
builtin_define ("__core2"); \
|
||||
builtin_define ("__core2__"); \
|
||||
} \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
@ -481,23 +499,25 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
|
||||
#define TARGET_CPU_DEFAULT_pentium2 5
|
||||
#define TARGET_CPU_DEFAULT_pentium3 6
|
||||
#define TARGET_CPU_DEFAULT_pentium4 7
|
||||
#define TARGET_CPU_DEFAULT_k6 8
|
||||
#define TARGET_CPU_DEFAULT_k6_2 9
|
||||
#define TARGET_CPU_DEFAULT_k6_3 10
|
||||
#define TARGET_CPU_DEFAULT_athlon 11
|
||||
#define TARGET_CPU_DEFAULT_athlon_sse 12
|
||||
#define TARGET_CPU_DEFAULT_k8 13
|
||||
#define TARGET_CPU_DEFAULT_pentium_m 14
|
||||
#define TARGET_CPU_DEFAULT_prescott 15
|
||||
#define TARGET_CPU_DEFAULT_nocona 16
|
||||
#define TARGET_CPU_DEFAULT_generic 17
|
||||
#define TARGET_CPU_DEFAULT_geode 8
|
||||
#define TARGET_CPU_DEFAULT_k6 9
|
||||
#define TARGET_CPU_DEFAULT_k6_2 10
|
||||
#define TARGET_CPU_DEFAULT_k6_3 11
|
||||
#define TARGET_CPU_DEFAULT_athlon 12
|
||||
#define TARGET_CPU_DEFAULT_athlon_sse 13
|
||||
#define TARGET_CPU_DEFAULT_k8 14
|
||||
#define TARGET_CPU_DEFAULT_pentium_m 15
|
||||
#define TARGET_CPU_DEFAULT_prescott 16
|
||||
#define TARGET_CPU_DEFAULT_nocona 17
|
||||
#define TARGET_CPU_DEFAULT_core2 18
|
||||
#define TARGET_CPU_DEFAULT_generic 19
|
||||
|
||||
#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
|
||||
"pentiumpro", "pentium2", "pentium3", \
|
||||
"pentium4", "k6", "k6-2", "k6-3",\
|
||||
"pentium4", "geode", "k6", "k6-2", "k6-3", \
|
||||
"athlon", "athlon-4", "k8", \
|
||||
"pentium-m", "prescott", "nocona", \
|
||||
"generic"}
|
||||
"core2", "generic"}
|
||||
|
||||
#ifndef CC1_SPEC
|
||||
#define CC1_SPEC "%(cc1_cpu) "
|
||||
@ -2077,11 +2097,13 @@ enum processor_type
|
||||
PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
|
||||
PROCESSOR_PENTIUM,
|
||||
PROCESSOR_PENTIUMPRO,
|
||||
PROCESSOR_GEODE,
|
||||
PROCESSOR_K6,
|
||||
PROCESSOR_ATHLON,
|
||||
PROCESSOR_PENTIUM4,
|
||||
PROCESSOR_K8,
|
||||
PROCESSOR_NOCONA,
|
||||
PROCESSOR_CORE2,
|
||||
PROCESSOR_GENERIC32,
|
||||
PROCESSOR_GENERIC64,
|
||||
PROCESSOR_max
|
||||
|
||||
@ -187,7 +187,7 @@
|
||||
|
||||
;; Processor type. This attribute must exactly match the processor_type
|
||||
;; enumeration in i386.h.
|
||||
(define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona,generic32,generic64"
|
||||
(define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,nocona,core2,generic32,generic64"
|
||||
(const (symbol_ref "ix86_tune")))
|
||||
|
||||
;; A basic instruction type. Refinements due to arguments to be
|
||||
@ -473,6 +473,7 @@
|
||||
(include "ppro.md")
|
||||
(include "k6.md")
|
||||
(include "athlon.md")
|
||||
(include "geode.md")
|
||||
|
||||
|
||||
;; Operand and operator predicates and constraints
|
||||
|
||||
@ -129,7 +129,7 @@
|
||||
.\" ========================================================================
|
||||
.\"
|
||||
.IX Title "GCC 1"
|
||||
.TH GCC 1 "2011-02-20" "gcc-4.2.1" "GNU"
|
||||
.TH GCC 1 "2011-03-07" "gcc-4.2.1" "GNU"
|
||||
.SH "NAME"
|
||||
gcc \- GNU project C and C++ compiler
|
||||
.SH "SYNOPSIS"
|
||||
@ -8733,6 +8733,10 @@ set support.
|
||||
.IX Item "nocona"
|
||||
Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0,
|
||||
\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support.
|
||||
.IP "\fIcore2\fR" 4
|
||||
.IX Item "core2"
|
||||
Intel Core2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0
|
||||
instruction set support.
|
||||
.IP "\fIk6\fR" 4
|
||||
.IX Item "k6"
|
||||
\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support.
|
||||
@ -8770,6 +8774,9 @@ implemented for this chip.)
|
||||
.IX Item "c3-2"
|
||||
Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is
|
||||
implemented for this chip.)
|
||||
.IP "\fIgeode\fR" 4
|
||||
.IX Item "geode"
|
||||
Embedded AMD \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support.
|
||||
.RE
|
||||
.RS 4
|
||||
.Sp
|
||||
|
||||
@ -9369,6 +9369,9 @@ set support.
|
||||
@item nocona
|
||||
Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE,
|
||||
SSE2 and SSE3 instruction set support.
|
||||
@item core2
|
||||
Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
|
||||
instruction set support.
|
||||
@item k6
|
||||
AMD K6 CPU with MMX instruction set support.
|
||||
@item k6-2, k6-3
|
||||
@ -9396,6 +9399,8 @@ implemented for this chip.)
|
||||
@item c3-2
|
||||
Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is
|
||||
implemented for this chip.)
|
||||
@item geode
|
||||
Embedded AMD CPU with MMX and 3dNOW! instruction set support.
|
||||
@end table
|
||||
|
||||
While picking a specific @var{cpu-type} will schedule things appropriately
|
||||
|
||||
Loading…
Reference in New Issue
Block a user