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Pull in r356809 from upstream llvm trunk (by Eli Friedman):

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[ARM] Don't form "ands" when it isn't scheduled correctly.

  In r322972/r323136, the iteration here was changed to catch cases at
  the beginning of a basic block... but we accidentally deleted an
  important safety check.  Restore that check to the way it was.

  Fixes https://bugs.llvm.org/show_bug.cgi?id=41116

  Differential Revision: https://reviews.llvm.org/D59680

This should fix "Assertion failed: (LiveCPSR && "CPSR liveness tracking
is wrong!"), function UpdateCPSRUse" errors when building the devel/xwpe
port for armv7.

PR:		236062, 236568
MFC after:	1 month
X-MFC-With:	r344779
This commit is contained in:
dim 2019-03-23 14:10:05 +00:00
parent 0e6bf0c478
commit 91e68110e4
1 changed files with 9 additions and 1 deletions
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10
contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -2824,7 +2824,15 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
// change. We can't do this transformation.
return false;
} while (I != B);
if (I == B) {
// In some cases, we scan the use-list of an instruction for an AND;
// that AND is in the same BB, but may not be scheduled before the
// corresponding TST. In that case, bail out.
//
// FIXME: We could try to reschedule the AND.
return false;
}
} while (true);
// Return false if no candidates exist.
if (!MI && !SubAdd)