From 921828e80400ad7fed6b38b3b9ad31940b4477dc Mon Sep 17 00:00:00 2001
From: loos <loos@FreeBSD.org>
Date: Wed, 17 May 2017 22:05:07 +0000
Subject: [PATCH] Fix the offset for the CPU0 MPIC registers.

Please note that only a subset of CPU0 registers are exported.  CPU1
registers are not touched.

Obtained from:	ARMADA38X Functional Specifications
Sponsored by:	Rubicon Communications, LLC (Netgate)
---
 sys/boot/fdt/dts/arm/armada-38x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/boot/fdt/dts/arm/armada-38x.dtsi b/sys/boot/fdt/dts/arm/armada-38x.dtsi
index c4673ecc4d09..e8d1b05c0d27 100644
--- a/sys/boot/fdt/dts/arm/armada-38x.dtsi
+++ b/sys/boot/fdt/dts/arm/armada-38x.dtsi
@@ -419,7 +419,7 @@
 
 			mpic: interrupt-controller@20a00 {
 				compatible = "marvell,mpic";
-				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+				reg = <0x20a00 0x2d0>, <0x21870 0x58>;
 				#interrupt-cells = <1>;
 				#size-cells = <1>;
 				interrupt-controller;