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Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X

Browse Source 
SCSI Controller chip.
This commit is contained in:
gibbs 2002-06-05 19:52:45 +00:00
parent de0f199372
commit 92285ba13e
9 changed files with 19742 additions and 0 deletions
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302
sys/dev/aic7xxx/ahd_pci.c Normal file
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/*
* FreeBSD, PCI product support functions
*
* Copyright (c) 1995-2001 Justin T. Gibbs
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU Public License ("GPL").
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*
* $FreeBSD$
*/
#include <dev/aic7xxx/aic79xx_osm.h>
#define AHD_PCI_IOADDR0 PCIR_MAPS /* Primary I/O BAR */
#define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
#define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Secondary I/O BAR */
static int ahd_pci_probe(device_t dev);
static int ahd_pci_attach(device_t dev);
static device_method_t ahd_pci_device_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, ahd_pci_probe),
DEVMETHOD(device_attach, ahd_pci_attach),
DEVMETHOD(device_detach, ahd_detach),
{ 0, 0 }
};
#if __FreeBSD_version >= 500027
DEVINTERFACE(ahd_pci_device, ahd_pci_device_methods, device);
static device_interface_t *ahd_pci_interfaces[] = {
&ahd_pci_device_interface,
NULL
};
static driver_t ahd_pci_driver = {
"ahd",
ahd_pci_interfaces,
sizeof(struct ahd_softc)
};
#else /* FreeBSD 4.X */
static driver_t ahd_pci_driver = {
"ahd",
ahd_pci_device_methods,
sizeof(struct ahd_softc)
};
#endif /* __FreeBSD_version */
static devclass_t ahd_devclass;
DRIVER_MODULE(ahd, pci, ahd_pci_driver, ahd_devclass, 0, 0);
DRIVER_MODULE(ahd, cardbus, ahd_pci_driver, ahd_devclass, 0, 0);
MODULE_DEPEND(ahd_pci, ahd, 1, 1, 1);
MODULE_VERSION(ahd_pci, 1);
static int
ahd_pci_probe(device_t dev)
{
struct ahd_pci_identity *entry;
entry = ahd_find_pci_device(dev);
if (entry != NULL) {
device_set_desc(dev, entry->name);
return (0);
}
return (ENXIO);
}
static int
ahd_pci_attach(device_t dev)
{
struct ahd_pci_identity *entry;
struct ahd_softc *ahd;
char *name;
int error;
entry = ahd_find_pci_device(dev);
if (entry == NULL)
return (ENXIO);
/*
* Allocate a softc for this card and
* set it up for attachment by our
* common detect routine.
*/
name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT);
if (name == NULL)
return (ENOMEM);
strcpy(name, device_get_nameunit(dev));
ahd = ahd_alloc(dev, name);
if (ahd == NULL)
return (ENOMEM);
ahd_set_unit(ahd, device_get_unit(dev));
/*
* Should we bother disabling 39Bit addressing
* based on installed memory?
*/
if (sizeof(bus_addr_t) > 4)
ahd->flags |= AHD_39BIT_ADDRESSING;
/* Allocate a dmatag for our SCB DMA maps */
/* XXX Should be a child of the PCI bus dma tag */
error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
/*boundary*/0,
(ahd->flags & AHD_39BIT_ADDRESSING)
? 0x7FFFFFFFFF
: BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/MAXBSIZE, /*nsegments*/AHD_NSEG,
/*maxsegsz*/AHD_MAXTRANSFER_SIZE,
/*flags*/BUS_DMA_ALLOCNOW,
&ahd->parent_dmat);
if (error != 0) {
printf("ahd_pci_attach: Could not allocate DMA tag "
"- error %d\n", error);
ahd_free(ahd);
return (ENOMEM);
}
ahd->dev_softc = dev;
error = ahd_pci_config(ahd, entry);
if (error != 0) {
ahd_free(ahd);
return (error);
}
ahd_attach(ahd);
return (0);
}
int
ahd_pci_map_registers(struct ahd_softc *ahd)
{
struct resource *regs;
struct resource *regs2;
u_int command;
int regs_type;
int regs_id;
int regs_id2;
command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
regs = NULL;
regs2 = NULL;
regs_type = 0;
regs_id = 0;
if ((command & PCIM_CMD_MEMEN) != 0) {
regs_type = SYS_RES_MEMORY;
regs_id = AHD_PCI_MEMADDR;
regs = bus_alloc_resource(ahd->dev_softc, regs_type,
&regs_id, 0, ~0, 1, RF_ACTIVE);
if (regs != NULL) {
int error;
ahd->tags[0] = rman_get_bustag(regs);
ahd->bshs[0] = rman_get_bushandle(regs);
ahd->tags[1] = ahd->tags[0];
error = bus_space_subregion(ahd->tags[0], ahd->bshs[0],
/*offset*/0x100,
/*size*/0x100,
&ahd->bshs[1]);
/*
* Do a quick test to see if memory mapped
* I/O is functioning correctly.
*/
if (error != 0 || ahd_inb(ahd, HCNTRL) == 0xFF) {
device_printf(ahd->dev_softc,
"PCI Device %d:%d:%d failed memory "
"mapped test. Using PIO.\n",
ahd_get_pci_bus(ahd->dev_softc),
ahd_get_pci_slot(ahd->dev_softc),
ahd_get_pci_function(ahd->dev_softc));
bus_release_resource(ahd->dev_softc, regs_type,
regs_id, regs);
regs = NULL;
} else {
command &= ~PCIM_CMD_PORTEN;
ahd_pci_write_config(ahd->dev_softc,
PCIR_COMMAND,
command, /*bytes*/1);
}
}
}
if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
regs_type = SYS_RES_IOPORT;
regs_id = AHD_PCI_IOADDR0;
regs = bus_alloc_resource(ahd->dev_softc, regs_type,
&regs_id, 0, ~0, 1, RF_ACTIVE);
if (regs == NULL) {
device_printf(ahd->dev_softc,
"can't allocate register resources\n");
return (ENOMEM);
}
ahd->tags[0] = rman_get_bustag(regs);
ahd->bshs[0] = rman_get_bushandle(regs);
/* And now the second BAR */
regs_id2 = AHD_PCI_IOADDR1;
regs2 = bus_alloc_resource(ahd->dev_softc, regs_type,
&regs_id2, 0, ~0, 1, RF_ACTIVE);
if (regs2 == NULL) {
device_printf(ahd->dev_softc,
"can't allocate register resources\n");
return (ENOMEM);
}
ahd->tags[1] = rman_get_bustag(regs2);
ahd->bshs[1] = rman_get_bushandle(regs2);
command &= ~PCIM_CMD_MEMEN;
ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
command, /*bytes*/1);
ahd->platform_data->regs_res_type[1] = regs_type;
ahd->platform_data->regs_res_id[1] = regs_id2;
ahd->platform_data->regs[1] = regs2;
}
ahd->platform_data->regs_res_type[0] = regs_type;
ahd->platform_data->regs_res_id[0] = regs_id;
ahd->platform_data->regs[0] = regs;
return (0);
}
int
ahd_pci_map_int(struct ahd_softc *ahd)
{
int zero;
zero = 0;
ahd->platform_data->irq =
bus_alloc_resource(ahd->dev_softc, SYS_RES_IRQ, &zero,
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
if (ahd->platform_data->irq == NULL)
return (ENOMEM);
ahd->platform_data->irq_res_type = SYS_RES_IRQ;
return (ahd_map_int(ahd));
}
void
ahd_power_state_change(struct ahd_softc *ahd, ahd_power_state new_state)
{
uint32_t cap;
u_int cap_offset;
/*
* Traverse the capability list looking for
* the power management capability.
*/
cap = 0;
cap_offset = ahd_pci_read_config(ahd->dev_softc,
PCIR_CAP_PTR, /*bytes*/1);
while (cap_offset != 0) {
cap = ahd_pci_read_config(ahd->dev_softc,
cap_offset, /*bytes*/4);
if ((cap & 0xFF) == 1
&& ((cap >> 16) & 0x3) > 0) {
uint32_t pm_control;
pm_control = ahd_pci_read_config(ahd->dev_softc,
cap_offset + 4,
/*bytes*/2);
pm_control &= ~0x3;
pm_control |= new_state;
ahd_pci_write_config(ahd->dev_softc,
cap_offset + 4,
pm_control, /*bytes*/2);
break;
}
cap_offset = (cap >> 8) & 0xFF;
}
}

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sys/dev/aic7xxx/aic79xx.reg Normal file
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/*
* Inline routines shareable across OS platforms.
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic79xx_inline.h#27 $
*
* $FreeBSD$
*/
#ifndef _AIC79XX_INLINE_H_
#define _AIC79XX_INLINE_H_
/******************************** Debugging ***********************************/
static __inline char *ahd_name(struct ahd_softc *ahd);
static __inline char *
ahd_name(struct ahd_softc *ahd)
{
return (ahd->name);
}
/************************ Sequencer Execution Control *************************/
static __inline void ahd_known_modes(struct ahd_softc *ahd,
ahd_mode src, ahd_mode dst);
static __inline ahd_mode_state ahd_build_mode_state(struct ahd_softc *ahd,
ahd_mode src,
ahd_mode dst);
static __inline void ahd_extract_mode_state(struct ahd_softc *ahd,
ahd_mode_state state,
ahd_mode *src, ahd_mode *dst);
static __inline void ahd_set_modes(struct ahd_softc *ahd, ahd_mode src,
ahd_mode dst);
static __inline void ahd_update_modes(struct ahd_softc *ahd);
static __inline void ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode,
ahd_mode dstmode, const char *file,
int line);
static __inline ahd_mode_state ahd_save_modes(struct ahd_softc *ahd);
static __inline void ahd_restore_modes(struct ahd_softc *ahd,
ahd_mode_state state);
static __inline int ahd_is_paused(struct ahd_softc *ahd);
static __inline void ahd_pause(struct ahd_softc *ahd);
static __inline void ahd_unpause(struct ahd_softc *ahd);
static __inline void
ahd_known_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
{
ahd->src_mode = src;
ahd->dst_mode = dst;
ahd->saved_src_mode = src;
ahd->saved_dst_mode = dst;
}
static __inline ahd_mode_state
ahd_build_mode_state(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
{
return ((src << SRC_MODE_SHIFT) | (dst << DST_MODE_SHIFT));
}
static __inline void
ahd_extract_mode_state(struct ahd_softc *ahd, ahd_mode_state state,
ahd_mode *src, ahd_mode *dst)
{
*src = (state & SRC_MODE) >> SRC_MODE_SHIFT;
*dst = (state & DST_MODE) >> DST_MODE_SHIFT;
}
static __inline void
ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
{
if (ahd->src_mode == src && ahd->dst_mode == dst)
return;
#ifdef AHD_DEBUG
if (ahd->src_mode == AHD_MODE_UNKNOWN
|| ahd->dst_mode == AHD_MODE_UNKNOWN)
panic("Setting mode prior to saving it.\n");
if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
printf("Setting mode 0x%x\n",
ahd_build_mode_state(ahd, src, dst));
#endif
ahd_outb(ahd, MODE_PTR, ahd_build_mode_state(ahd, src, dst));
ahd->src_mode = src;
ahd->dst_mode = dst;
}
static __inline void
ahd_update_modes(struct ahd_softc *ahd)
{
ahd_mode_state mode_ptr;
ahd_mode src;
ahd_mode dst;
mode_ptr = ahd_inb(ahd, MODE_PTR);
#ifdef AHD_DEBUG
if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
printf("Reading mode 0x%x\n", mode_ptr);
#endif
ahd_extract_mode_state(ahd, mode_ptr, &src, &dst);
ahd_known_modes(ahd, src, dst);
}
static __inline void
ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode,
ahd_mode dstmode, const char *file, int line)
{
#ifdef AHD_DEBUG
if ((srcmode & AHD_MK_MSK(ahd->src_mode)) == 0
|| (dstmode & AHD_MK_MSK(ahd->dst_mode)) == 0) {
panic("%s:%s:%d: Mode assertion failed.\n",
ahd_name(ahd), file, line);
}
#endif
}
static __inline ahd_mode_state
ahd_save_modes(struct ahd_softc *ahd)
{
if (ahd->src_mode == AHD_MODE_UNKNOWN
|| ahd->dst_mode == AHD_MODE_UNKNOWN)
ahd_update_modes(ahd);
return (ahd_build_mode_state(ahd, ahd->src_mode, ahd->dst_mode));
}
static __inline void
ahd_restore_modes(struct ahd_softc *ahd, ahd_mode_state state)
{
ahd_mode src;
ahd_mode dst;
ahd_extract_mode_state(ahd, state, &src, &dst);
ahd_set_modes(ahd, src, dst);
}
#define AHD_ASSERT_MODES(ahd, source, dest) \
ahd_assert_modes(ahd, source, dest, __FILE__, __LINE__);
/*
* Determine whether the sequencer has halted code execution.
* Returns non-zero status if the sequencer is stopped.
*/
static __inline int
ahd_is_paused(struct ahd_softc *ahd)
{
return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0);
}
/*
* Request that the sequencer stop and wait, indefinitely, for it
* to stop. The sequencer will only acknowledge that it is paused
* once it has reached an instruction boundary and PAUSEDIS is
* cleared in the SEQCTL register. The sequencer may use PAUSEDIS
* for critical sections.
*/
static __inline void
ahd_pause(struct ahd_softc *ahd)
{
ahd_outb(ahd, HCNTRL, ahd->pause);
/*
* Since the sequencer can disable pausing in a critical section, we
* must loop until it actually stops.
*/
while (ahd_is_paused(ahd) == 0)
;
}
/*
* Allow the sequencer to continue program execution.
* We check here to ensure that no additional interrupt
* sources that would cause the sequencer to halt have been
* asserted. If, for example, a SCSI bus reset is detected
* while we are fielding a different, pausing, interrupt type,
* we don't want to release the sequencer before going back
* into our interrupt handler and dealing with this new
* condition.
*/
static __inline void
ahd_unpause(struct ahd_softc *ahd)
{
/*
* Automatically restore our modes to those saved
* prior to the first change of the mode.
*/
if (ahd->saved_src_mode != AHD_MODE_UNKNOWN
&& ahd->saved_dst_mode != AHD_MODE_UNKNOWN)
ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
if ((ahd_inb(ahd, INTSTAT) & ~(SWTMINT | CMDCMPLT)) == 0)
ahd_outb(ahd, HCNTRL, ahd->unpause);
ahd_known_modes(ahd, AHD_MODE_UNKNOWN, AHD_MODE_UNKNOWN);
}
/*********************** Untagged Transaction Routines ************************/
static __inline void ahd_freeze_untagged_queues(struct ahd_softc *ahd);
static __inline void ahd_release_untagged_queues(struct ahd_softc *ahd);
/*
* Block our completion routine from starting the next untagged
* transaction for this target or target lun.
*/
static __inline void
ahd_freeze_untagged_queues(struct ahd_softc *ahd)
{
/*
* Assume we have enough space in the card's SCB
* to obviate the need for a per target untagged
* transaction limit.
*/
#if 0
ahd->untagged_queue_lock++;
#endif
}
/*
* Allow the next untagged transaction for this target or target lun
* to be executed. We use a counting semaphore to allow the lock
* to be acquired recursively. Once the count drops to zero, the
* transaction queues will be run.
*/
static __inline void
ahd_release_untagged_queues(struct ahd_softc *ahd)
{
/*
* Assume we have enough space in the card's SCB
* to obviate the need for a per target untagged
* transaction limit.
*/
#if 0
ahd->untagged_queue_lock--;
if (ahd->untagged_queue_lock == 0)
ahd_run_untagged_queues(ahd);
#endif
}
/*********************** Scatter Gather List Handling *************************/
static __inline void *ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
void *sgptr, bus_addr_t addr,
bus_size_t len, int last);
static __inline void ahd_setup_scb_common(struct ahd_softc *ahd,
struct scb *scb);
static __inline void ahd_setup_data_scb(struct ahd_softc *ahd,
struct scb *scb);
static __inline void ahd_setup_noxfer_scb(struct ahd_softc *ahd,
struct scb *scb);
static __inline void *
ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
void *sgptr, bus_addr_t addr, bus_size_t len, int last)
{
scb->sg_count++;
if (sizeof(bus_addr_t) > 4
&& (ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
struct ahd_dma64_seg *sg;
sg = (struct ahd_dma64_seg *)sgptr;
sg->addr = ahd_htole64(addr);
sg->len = ahd_htole32(len | (last ? AHD_DMA_LAST_SEG : 0));
return (sg + 1);
} else {
struct ahd_dma_seg *sg;
sg = (struct ahd_dma_seg *)sgptr;
sg->addr = ahd_htole64(addr);
sg->len = ahd_htole32(len | ((addr >> 8) & 0x7F000000)
| (last ? AHD_DMA_LAST_SEG : 0));
return (sg + 1);
}
}
static __inline void
ahd_setup_scb_common(struct ahd_softc *ahd, struct scb *scb)
{
/* XXX Handle target mode SCBs. */
if ((scb->flags & SCB_PACKETIZED) != 0) {
/* XXX what about ACA?? It is type 4, but TAG_TYPE == 0x3. */
scb->hscb->task_attribute_nonpkt_tag =
scb->hscb->control & SCB_TAG_TYPE;
scb->hscb->task_management = 0;
} else {
scb->hscb->task_attribute_nonpkt_tag = SCB_GET_TAG(scb);
}
if (scb->hscb->cdb_len <= MAX_CDB_LEN_WITH_SENSE_ADDR
|| (scb->hscb->cdb_len & SCB_CDB_LEN_PTR) != 0)
scb->hscb->shared_data.idata.cdb_plus_saddr.sense_addr =
ahd_htole32(scb->sense_busaddr);
}
static __inline void
ahd_setup_data_scb(struct ahd_softc *ahd, struct scb *scb)
{
/*
* Copy the first SG into the "current" data ponter area.
*/
if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
struct ahd_dma64_seg *sg;
sg = (struct ahd_dma64_seg *)scb->sg_list;
scb->hscb->dataptr = sg->addr;
scb->hscb->datacnt = sg->len;
} else {
struct ahd_dma_seg *sg;
sg = (struct ahd_dma_seg *)scb->sg_list;
scb->hscb->dataptr = sg->addr;
if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
uint64_t high_addr;
high_addr = (ahd_le32toh(sg->len) & 0x7F000000) << 8;
scb->hscb->dataptr |= ahd_htole64(high_addr);
}
scb->hscb->datacnt = sg->len;
}
/*
* Note where to find the SG entries in bus space.
* We also set the full residual flag which the
* sequencer will clear as soon as a data transfer
* occurs.
*/
scb->hscb->sgptr = ahd_htole32(scb->sg_list_busaddr|SG_FULL_RESID);
}
static __inline void
ahd_setup_noxfer_scb(struct ahd_softc *ahd, struct scb *scb)
{
scb->hscb->sgptr = ahd_htole32(SG_LIST_NULL);
scb->hscb->dataptr = 0;
scb->hscb->datacnt = 0;
}
/************************** Memory mapping routines ***************************/
static __inline size_t ahd_sg_size(struct ahd_softc *ahd);
static __inline void *
ahd_sg_bus_to_virt(struct ahd_softc *ahd,
struct scb *scb,
uint32_t sg_busaddr);
static __inline uint32_t
ahd_sg_virt_to_bus(struct ahd_softc *ahd,
struct scb *scb,
void *sg);
static __inline void ahd_sync_scb(struct ahd_softc *ahd,
struct scb *scb, int op);
static __inline void ahd_sync_sglist(struct ahd_softc *ahd,
struct scb *scb, int op);
static __inline void ahd_sync_sense(struct ahd_softc *ahd,
struct scb *scb, int op);
static __inline uint32_t
ahd_targetcmd_offset(struct ahd_softc *ahd,
u_int index);
static __inline size_t
ahd_sg_size(struct ahd_softc *ahd)
{
if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
return (sizeof(struct ahd_dma64_seg));
return (sizeof(struct ahd_dma_seg));
}
static __inline void *
ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr)
{
bus_addr_t sg_offset;
/* sg_list_phys points to entry 1, not 0 */
sg_offset = sg_busaddr - (scb->sg_list_busaddr - ahd_sg_size(ahd));
return ((uint8_t *)scb->sg_list + sg_offset);
}
static __inline uint32_t
ahd_sg_virt_to_bus(struct ahd_softc *ahd, struct scb *scb, void *sg)
{
bus_addr_t sg_offset;
/* sg_list_phys points to entry 1, not 0 */
sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list)
- ahd_sg_size(ahd);
return (scb->sg_list_busaddr + sg_offset);
}
static __inline void
ahd_sync_scb(struct ahd_softc *ahd, struct scb *scb, int op)
{
ahd_dmamap_sync(ahd, ahd->scb_data.hscb_dmat,
scb->hscb_map->dmamap,
/*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr,
/*len*/sizeof(*scb->hscb), op);
}
static __inline void
ahd_sync_sglist(struct ahd_softc *ahd, struct scb *scb, int op)
{
if (scb->sg_count == 0)
return;
ahd_dmamap_sync(ahd, ahd->scb_data.sg_dmat,
scb->sg_map->dmamap,
/*offset*/scb->sg_list_busaddr - ahd_sg_size(ahd),
/*len*/ahd_sg_size(ahd) * scb->sg_count, op);
}
static __inline void
ahd_sync_sense(struct ahd_softc *ahd, struct scb *scb, int op)
{
ahd_dmamap_sync(ahd, ahd->scb_data.sense_dmat,
scb->sense_map->dmamap,
/*offset*/scb->sense_busaddr,
/*len*/AHD_SENSE_BUFSIZE, op);
}
static __inline uint32_t
ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index)
{
return (((uint8_t *)&ahd->targetcmds[index])
- (uint8_t *)ahd->qoutfifo);
}
/*********************** Miscelaneous Support Functions ***********************/
static __inline void ahd_complete_scb(struct ahd_softc *ahd,
struct scb *scb);
static __inline void ahd_update_residual(struct ahd_softc *ahd,
struct scb *scb);
static __inline struct ahd_initiator_tinfo *
ahd_fetch_transinfo(struct ahd_softc *ahd,
char channel, u_int our_id,
u_int remote_id,
struct ahd_tmode_tstate **tstate);
static __inline struct scb*
ahd_get_scb(struct ahd_softc *ahd);
static __inline void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
static __inline uint16_t
ahd_inw(struct ahd_softc *ahd, u_int port);
static __inline void ahd_outw(struct ahd_softc *ahd, u_int port,
u_int value);
static __inline uint32_t
ahd_inl(struct ahd_softc *ahd, u_int port);
static __inline void ahd_outl(struct ahd_softc *ahd, u_int port,
uint32_t value);
static __inline uint64_t
ahd_inq(struct ahd_softc *ahd, u_int port);
static __inline void ahd_outq(struct ahd_softc *ahd, u_int port,
uint64_t value);
static __inline u_int ahd_get_scbptr(struct ahd_softc *ahd);
static __inline void ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr);
static __inline u_int ahd_get_hnscb_qoff(struct ahd_softc *ahd);
static __inline void ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value);
static __inline u_int ahd_get_hescb_qoff(struct ahd_softc *ahd);
static __inline void ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value);
static __inline u_int ahd_get_snscb_qoff(struct ahd_softc *ahd);
static __inline void ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value);
static __inline u_int ahd_get_sescb_qoff(struct ahd_softc *ahd);
static __inline void ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value);
static __inline u_int ahd_get_sdscb_qoff(struct ahd_softc *ahd);
static __inline void ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value);
static __inline u_int ahd_inb_scbram(struct ahd_softc *ahd, u_int offset);
static __inline u_int ahd_inw_scbram(struct ahd_softc *ahd, u_int offset);
static __inline uint32_t
ahd_inl_scbram(struct ahd_softc *ahd, u_int offset);
static __inline void ahd_swap_with_next_hscb(struct ahd_softc *ahd,
struct scb *scb);
static __inline void ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb);
static __inline uint8_t *
ahd_get_sense_buf(struct ahd_softc *ahd,
struct scb *scb);
static __inline uint32_t
ahd_get_sense_bufaddr(struct ahd_softc *ahd,
struct scb *scb);
static __inline void
ahd_complete_scb(struct ahd_softc *ahd, struct scb *scb)
{
uint32_t sgptr;
sgptr = ahd_le32toh(scb->hscb->sgptr);
if ((sgptr & SG_STATUS_VALID) != 0)
ahd_handle_scb_status(ahd, scb);
else
ahd_done(ahd, scb);
}
/*
* Determine whether the sequencer reported a residual
* for this SCB/transaction.
*/
static __inline void
ahd_update_residual(struct ahd_softc *ahd, struct scb *scb)
{
uint32_t sgptr;
sgptr = ahd_le32toh(scb->hscb->sgptr);
if ((sgptr & SG_STATUS_VALID) != 0)
ahd_calc_residual(ahd, scb);
}
/*
* Return pointers to the transfer negotiation information
* for the specified our_id/remote_id pair.
*/
static __inline struct ahd_initiator_tinfo *
ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id,
u_int remote_id, struct ahd_tmode_tstate **tstate)
{
/*
* Transfer data structures are stored from the perspective
* of the target role. Since the parameters for a connection
* in the initiator role to a given target are the same as
* when the roles are reversed, we pretend we are the target.
*/
if (channel == 'B')
our_id += 8;
*tstate = ahd->enabled_targets[our_id];
return (&(*tstate)->transinfo[remote_id]);
}
/*
* Get a free scb. If there are none, see if we can allocate a new SCB.
*/
static __inline struct scb *
ahd_get_scb(struct ahd_softc *ahd)
{
struct scb *scb;
if ((scb = SLIST_FIRST(&ahd->scb_data.free_scbs)) == NULL) {
ahd_alloc_scbs(ahd);
scb = SLIST_FIRST(&ahd->scb_data.free_scbs);
if (scb == NULL)
return (NULL);
}
SLIST_REMOVE_HEAD(&ahd->scb_data.free_scbs, links.sle);
return (scb);
}
/*
* Return an SCB resource to the free list.
*/
static __inline void
ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
{
/* Clean up for the next user */
ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
scb->flags = SCB_FREE;
scb->hscb->control = 0;
SLIST_INSERT_HEAD(&ahd->scb_data.free_scbs, scb, links.sle);
/* Notify the OSM that a resource is now available. */
ahd_platform_scb_free(ahd, scb);
}
static __inline uint16_t
ahd_inw(struct ahd_softc *ahd, u_int port)
{
return ((ahd_inb(ahd, port+1) << 8) | ahd_inb(ahd, port));
}
static __inline void
ahd_outw(struct ahd_softc *ahd, u_int port, u_int value)
{
ahd_outb(ahd, port, value & 0xFF);
ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
}
static __inline uint32_t
ahd_inl(struct ahd_softc *ahd, u_int port)
{
return ((ahd_inb(ahd, port))
| (ahd_inb(ahd, port+1) << 8)
| (ahd_inb(ahd, port+2) << 16)
| (ahd_inb(ahd, port+3) << 24));
}
static __inline void
ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value)
{
ahd_outb(ahd, port, (value) & 0xFF);
ahd_outb(ahd, port+1, ((value) >> 8) & 0xFF);
ahd_outb(ahd, port+2, ((value) >> 16) & 0xFF);
ahd_outb(ahd, port+3, ((value) >> 24) & 0xFF);
}
static __inline uint64_t
ahd_inq(struct ahd_softc *ahd, u_int port)
{
return ((ahd_inb(ahd, port))
| (ahd_inb(ahd, port+1) << 8)
| (ahd_inb(ahd, port+2) << 16)
| (ahd_inb(ahd, port+3) << 24)
| (((uint64_t)ahd_inb(ahd, port+4)) << 32)
| (((uint64_t)ahd_inb(ahd, port+5)) << 40)
| (((uint64_t)ahd_inb(ahd, port+6)) << 48)
| (((uint64_t)ahd_inb(ahd, port+7)) << 56));
}
static __inline void
ahd_outq(struct ahd_softc *ahd, u_int port, uint64_t value)
{
ahd_outb(ahd, port, value & 0xFF);
ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
ahd_outb(ahd, port+2, (value >> 16) & 0xFF);
ahd_outb(ahd, port+3, (value >> 24) & 0xFF);
ahd_outb(ahd, port+4, (value >> 32) & 0xFF);
ahd_outb(ahd, port+5, (value >> 40) & 0xFF);
ahd_outb(ahd, port+6, (value >> 48) & 0xFF);
ahd_outb(ahd, port+7, (value >> 56) & 0xFF);
}
static __inline u_int
ahd_get_scbptr(struct ahd_softc *ahd)
{
AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
return (ahd_inb(ahd, SCBPTR) | (ahd_inb(ahd, SCBPTR + 1) << 8));
}
static __inline void
ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr)
{
AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
ahd_outb(ahd, SCBPTR, scbptr & 0xFF);
ahd_outb(ahd, SCBPTR+1, (scbptr >> 8) & 0xFF);
}
static __inline u_int
ahd_get_hnscb_qoff(struct ahd_softc *ahd)
{
return (ahd_inw_atomic(ahd, HNSCB_QOFF));
}
static __inline void
ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value)
{
ahd_outw_atomic(ahd, HNSCB_QOFF, value);
}
static __inline u_int
ahd_get_hescb_qoff(struct ahd_softc *ahd)
{
return (ahd_inb(ahd, HESCB_QOFF));
}
static __inline void
ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value)
{
ahd_outb(ahd, HESCB_QOFF, value);
}
static __inline u_int
ahd_get_snscb_qoff(struct ahd_softc *ahd)
{
u_int oldvalue;
AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
oldvalue = ahd_inw(ahd, SNSCB_QOFF);
ahd_outw(ahd, SNSCB_QOFF, oldvalue);
return (oldvalue);
}
static __inline void
ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value)
{
AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
ahd_outw(ahd, SNSCB_QOFF, value);
}
static __inline u_int
ahd_get_sescb_qoff(struct ahd_softc *ahd)
{
AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
return (ahd_inb(ahd, SESCB_QOFF));
}
static __inline void
ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value)
{
AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
ahd_outb(ahd, SESCB_QOFF, value);
}
static __inline u_int
ahd_get_sdscb_qoff(struct ahd_softc *ahd)
{
AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
return (ahd_inb(ahd, SDSCB_QOFF) | (ahd_inb(ahd, SDSCB_QOFF + 1) << 8));
}
static __inline void
ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value)
{
AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
ahd_outb(ahd, SDSCB_QOFF, value & 0xFF);
ahd_outb(ahd, SDSCB_QOFF+1, (value >> 8) & 0xFF);
}
static __inline u_int
ahd_inb_scbram(struct ahd_softc *ahd, u_int offset)
{
u_int value;
/*
* Workaround PCI-X Rev A. hardware bug.
* After a host read of SCB memory, the chip
* may become confused into thinking prefetch
* was required. This starts the discard timer
* running and can cause an unexpected discard
* timer interrupt. The work around is to read
* a normal register prior to the exhaustion of
* the discard timer. The mode pointer register
* has no side effects and so serves well for
* this purpose.
*
* Razor #528
*/
value = ahd_inb(ahd, offset);
ahd_inb(ahd, MODE_PTR);
return (value);
}
static __inline u_int
ahd_inw_scbram(struct ahd_softc *ahd, u_int offset)
{
return (ahd_inb_scbram(ahd, offset)
| (ahd_inb_scbram(ahd, offset+1) << 8));
}
static __inline uint32_t
ahd_inl_scbram(struct ahd_softc *ahd, u_int offset)
{
return (ahd_inb_scbram(ahd, offset)
| (ahd_inb_scbram(ahd, offset+1) << 8)
| (ahd_inb_scbram(ahd, offset+2) << 16)
| (ahd_inb_scbram(ahd, offset+3) << 24));
}
static __inline struct scb *
ahd_lookup_scb(struct ahd_softc *ahd, u_int tag)
{
struct scb* scb;
if (tag >= AHD_SCB_MAX)
return (NULL);
scb = ahd->scb_data.scbindex[tag];
if (scb != NULL)
ahd_sync_scb(ahd, scb,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
return (scb);
}
static __inline void
ahd_swap_with_next_hscb(struct ahd_softc *ahd, struct scb *scb)
{
struct hardware_scb *q_hscb;
uint32_t saved_hscb_busaddr;
/*
* Our queuing method is a bit tricky. The card
* knows in advance which HSCB (by address) to download,
* and we can't disappoint it. To achieve this, the next
* SCB to download is saved off in ahd->next_queued_scb.
* When we are called to queue "an arbitrary scb",
* we copy the contents of the incoming HSCB to the one
* the sequencer knows about, swap HSCB pointers and
* finally assign the SCB to the tag indexed location
* in the scb_array. This makes sure that we can still
* locate the correct SCB by SCB_TAG.
*/
q_hscb = ahd->next_queued_scb->hscb;
saved_hscb_busaddr = q_hscb->hscb_busaddr;
memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
q_hscb->hscb_busaddr = saved_hscb_busaddr;
q_hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
/* Now swap HSCB pointers. */
ahd->next_queued_scb->hscb = scb->hscb;
scb->hscb = q_hscb;
/* Now define the mapping from tag to SCB in the scbindex */
/* XXX This should be constant now. Can we avoid the mapping? */
ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = scb;
}
/*
* Tell the sequencer about a new transaction to execute.
*/
static __inline void
ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb)
{
ahd_swap_with_next_hscb(ahd, scb);
if (SCBID_IS_NULL(SCB_GET_TAG(scb)))
panic("Attempt to queue invalid SCB tag %x\n",
SCB_GET_TAG(scb));
/*
* Keep a history of SCBs we've downloaded in the qinfifo.
*/
ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
ahd->qinfifonext++;
if (scb->sg_count != 0)
ahd_setup_data_scb(ahd, scb);
else
ahd_setup_noxfer_scb(ahd, scb);
ahd_setup_scb_common(ahd, scb);
/*
* Make sure our data is consistant from the
* perspective of the adapter.
*/
ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
#ifdef AHD_DEBUG
if ((ahd_debug & AHD_SHOW_QUEUE) != 0) {
printf("%s: Queueing SCB 0x%x bus addr 0x%x - 0x%x%x/0x%x\n",
ahd_name(ahd),
SCB_GET_TAG(scb), scb->hscb->hscb_busaddr,
(u_int)((scb->hscb->dataptr >> 32) & 0xFFFFFFFF),
(u_int)(scb->hscb->dataptr & 0xFFFFFFFF),
scb->hscb->datacnt);
}
#endif
/* Tell the adapter about the newly queued SCB */
ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
}
static __inline uint8_t *
ahd_get_sense_buf(struct ahd_softc *ahd, struct scb *scb)
{
return (scb->sense_data);
}
static __inline uint32_t
ahd_get_sense_bufaddr(struct ahd_softc *ahd, struct scb *scb)
{
return (scb->sense_busaddr);
}
/************************** Interrupt Processing ******************************/
static __inline void ahd_sync_qoutfifo(struct ahd_softc *ahd, int op);
static __inline void ahd_sync_tqinfifo(struct ahd_softc *ahd, int op);
static __inline u_int ahd_check_cmdcmpltqueues(struct ahd_softc *ahd);
static __inline void ahd_intr(struct ahd_softc *ahd);
static __inline void
ahd_sync_qoutfifo(struct ahd_softc *ahd, int op)
{
ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_dmamap,
/*offset*/0, /*len*/AHC_SCB_MAX * sizeof(uint16_t), op);
}
static __inline void
ahd_sync_tqinfifo(struct ahd_softc *ahd, int op)
{
#ifdef AHD_TARGET_MODE
if ((ahd->flags & AHD_TARGETROLE) != 0) {
ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
ahd->shared_data_dmamap,
ahd_targetcmd_offset(ahd, 0),
sizeof(struct target_cmd) * AHD_TMODE_CMDS,
op);
}
#endif
}
/*
* See if the firmware has posted any completed commands
* into our in-core command complete fifos.
*/
#define AHD_RUN_QOUTFIFO 0x1
#define AHD_RUN_TQINFIFO 0x2
static __inline u_int
ahd_check_cmdcmpltqueues(struct ahd_softc *ahd)
{
u_int retval;
retval = 0;
ahd_dmamap_sync(ahd, ahd->shared_data_dmat, ahd->shared_data_dmamap,
/*offset*/ahd->qoutfifonext, /*len*/2,
BUS_DMASYNC_POSTREAD);
if (ahd->qoutfifo[ahd->qoutfifonext] != SCB_LIST_NULL_LE)
retval |= AHD_RUN_QOUTFIFO;
#ifdef AHD_TARGET_MODE
if ((ahd->flags & AHD_TARGETROLE) != 0
&& (ahd->flags & AHD_TQINFIFO_BLOCKED) == 0) {
ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
ahd->shared_data_dmamap,
ahd_targetcmd_offset(ahd, ahd->tqinfifofnext),
/*len*/sizeof(struct target_cmd),
BUS_DMASYNC_POSTREAD);
if (ahd->targetcmds[ahd->tqinfifonext].cmd_valid != 0)
retval |= AHD_RUN_TQINFIFO;
}
#endif
return (retval);
}
/*
* Catch an interrupt from the adapter
*/
static __inline void
ahd_intr(struct ahd_softc *ahd)
{
u_int intstat;
/*
* Instead of directly reading the interrupt status register,
* infer the cause of the interrupt by checking our in-core
* completion queues. This avoids a costly PCI bus read in
* most cases.
*/
if ((ahd->flags & AHD_ALL_INTERRUPTS) == 0
&& (ahd_check_cmdcmpltqueues(ahd) != 0))
intstat = CMDCMPLT;
else
intstat = ahd_inb(ahd, INTSTAT);
if (intstat & CMDCMPLT) {
ahd_outb(ahd, CLRINT, CLRCMDINT);
/*
* Ensure that the chip sees that we've cleared
* this interrupt before we walk the output fifo.
* Otherwise, we may, due to posted bus writes,
* clear the interrupt after we finish the scan,
* and after the sequencer has added new entries
* and asserted the interrupt again.
*/
ahd_flush_device_writes(ahd);
ahd_run_qoutfifo(ahd);
#ifdef AHD_TARGET_MODE
if ((ahd->flags & AHD_TARGETROLE) != 0)
ahd_run_tqinfifo(ahd, /*paused*/FALSE);
#endif
}
if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0)
/* Hot eject */
return;
if ((intstat & INT_PEND) == 0)
return;
if (intstat & HWERRINT) {
ahd_handle_hwerrint(ahd);
return;
}
if ((intstat & (PCIINT|SPLTINT)) != 0) {
ahd->bus_intr(ahd);
return;
}
if ((intstat & SEQINT) != 0)
ahd_handle_seqint(ahd, intstat);
if ((intstat & SCSIINT) != 0)
ahd_handle_scsiint(ahd, intstat);
}
#endif /* _AIC79XX_INLINE_H_ */

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/*
* FreeBSD platform specific driver option settings, data structures,
* function declarations and includes.
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU Public License ("GPL").
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*
* $FreeBSD$
*/
#ifndef _AIC79XX_FREEBSD_H_
#define _AIC79XX_FREEBSD_H_
#include <opt_aic79xx.h> /* for config options */
#ifndef NPCI
#include <pci.h>
#endif
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h> /* For device_t */
#include <sys/eventhandler.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/queue.h>
#define AHD_PCI_CONFIG 1
#include <machine/bus_memio.h>
#include <machine/bus_pio.h>
#include <machine/bus.h>
#include <machine/endian.h>
#include <machine/clock.h>
#include <machine/resource.h>
#include <sys/rman.h>
#if NPCI > 0
#include <pci/pcireg.h>
#include <pci/pcivar.h>
#endif
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/cam_debug.h>
#include <cam/cam_sim.h>
#include <cam/cam_xpt_sim.h>
#include <cam/scsi/scsi_all.h>
#include <cam/scsi/scsi_message.h>
#include <cam/scsi/scsi_iu.h>
#ifdef CAM_NEW_TRAN_CODE
#define AHD_NEW_TRAN_SETTINGS
#endif /* CAM_NEW_TRAN_CODE */
/****************************** Platform Macros *******************************/
#define SIM_IS_SCSIBUS_B(ahd, sim) \
(0)
#define SIM_CHANNEL(ahd, sim) \
('A')
#define SIM_SCSI_ID(ahd, sim) \
(ahd->our_id)
#define SIM_PATH(ahd, sim) \
(ahd->platform_data->path)
#define BUILD_SCSIID(ahd, sim, target_id, our_id) \
((((target_id) << TID_SHIFT) & TID) | (our_id))
#define SCB_GET_SIM(ahd, scb) \
((ahd)->platform_data->sim)
#ifndef offsetof
#define offsetof(type, member) ((size_t)(&((type *)0)->member))
#endif
/************************* Forward Declarations *******************************/
typedef device_t ahd_dev_softc_t;
typedef union ccb *ahd_io_ctx_t;
/***************************** Bus Space/DMA **********************************/
#define ahd_dma_tag_create(ahd, parent_tag, alignment, boundary, \
lowaddr, highaddr, filter, filterarg, \
maxsize, nsegments, maxsegsz, flags, \
dma_tagp) \
bus_dma_tag_create(parent_tag, alignment, boundary, \
lowaddr, highaddr, filter, filterarg, \
maxsize, nsegments, maxsegsz, flags, \
dma_tagp)
#define ahd_dma_tag_destroy(ahd, tag) \
bus_dma_tag_destroy(tag)
#define ahd_dmamem_alloc(ahd, dmat, vaddr, flags, mapp) \
bus_dmamem_alloc(dmat, vaddr, flags, mapp)
#define ahd_dmamem_free(ahd, dmat, vaddr, map) \
bus_dmamem_free(dmat, vaddr, map)
#define ahd_dmamap_create(ahd, tag, flags, mapp) \
bus_dmamap_create(tag, flags, mapp)
#define ahd_dmamap_destroy(ahd, tag, map) \
bus_dmamap_destroy(tag, map)
#define ahd_dmamap_load(ahd, dmat, map, addr, buflen, callback, \
callback_arg, flags) \
bus_dmamap_load(dmat, map, addr, buflen, callback, callback_arg, flags)
#define ahd_dmamap_unload(ahd, tag, map) \
bus_dmamap_unload(tag, map)
/* XXX Need to update Bus DMA for partial map syncs */
#define ahd_dmamap_sync(ahd, dma_tag, dmamap, offset, len, op) \
bus_dmamap_sync(dma_tag, dmamap, op)
/************************ Tunable Driver Parameters **************************/
/*
* The number of dma segments supported. The sequencer can handle any number
* of physically contiguous S/G entrys. To reduce the driver's memory
* consumption, we limit the number supported to be sufficient to handle
* the largest mapping supported by the kernel, MAXPHYS. Assuming the
* transfer is as fragmented as possible and unaligned, this turns out to
* be the number of paged sized transfers in MAXPHYS plus an extra element
* to handle any unaligned residual. The sequencer fetches SG elements
* in cacheline sized chucks, so make the number per-transaction an even
* multiple of 16 which should align us on even the largest of cacheline
* boundaries.
*/
#define AHD_NSEG (roundup(btoc(MAXPHYS) + 1, 16))
/* This driver supports target mode */
#if NOT_YET
#define AHD_TARGET_MODE 1
#endif
/************************** Softc/SCB Platform Data ***************************/
struct ahd_platform_data {
/*
* Hooks into the XPT.
*/
struct cam_sim *sim;
struct cam_sim *sim_b;
struct cam_path *path;
struct cam_path *path_b;
int regs_res_type[2];
int regs_res_id[2];
int irq_res_type;
struct resource *regs[2];
struct resource *irq;
void *ih;
eventhandler_tag eh;
};
struct scb_platform_data {
};
/********************************* Byte Order *********************************/
/*
* XXX Waiting for FreeBSD byte swapping functions.
* For now assume host is Little Endian.
*/
#define ahd_htobe16(x) x
#define ahd_htobe32(x) x
#define ahd_htobe64(x) x
#define ahd_htole16(x) x
#define ahd_htole32(x) x
#define ahd_htole64(x) x
#define ahd_be16toh(x) x
#define ahd_be32toh(x) x
#define ahd_be64toh(x) x
#define ahd_le16toh(x) x
#define ahd_le32toh(x) x
#define ahd_le64toh(x) x
/************************** Timer DataStructures ******************************/
typedef struct callout ahd_timer_t;
/***************************** Core Includes **********************************/
#include <dev/aic7xxx/aic79xx.h>
/***************************** Timer Facilities *******************************/
#define ahd_timer_init callout_init
#define ahd_timer_stop callout_stop
static __inline void
ahd_timer_reset(ahd_timer_t *timer, int usec, ahd_callback_t *func, void *arg)
{
callout_reset(timer, (usec * hz)/1000000, func, arg);
}
/*************************** Device Access ************************************/
#define ahd_inb(ahd, port) \
bus_space_read_1((ahd)->tags[(port) >> 8], \
(ahd)->bshs[(port) >> 8], (port) & 0xFF)
#define ahd_outb(ahd, port, value) \
bus_space_write_1((ahd)->tags[(port) >> 8], \
(ahd)->bshs[(port) >> 8], (port) & 0xFF, value)
#define ahd_inw_atomic(ahd, port) \
ahd_le16toh(bus_space_read_2((ahd)->tags[(port) >> 8], \
(ahd)->bshs[(port) >> 8], (port) & 0xFF))
#define ahd_outw_atomic(ahd, port, value) \
bus_space_write_2((ahd)->tags[(port) >> 8], \
(ahd)->bshs[(port) >> 8], \
(port & 0xFF), ahd_htole16(value))
#define ahd_outsb(ahd, port, valp, count) \
bus_space_write_multi_1((ahd)->tags[(port) >> 8], \
(ahd)->bshs[(port) >> 8], \
(port & 0xFF), valp, count)
#define ahd_insb(ahd, port, valp, count) \
bus_space_read_multi_1((ahd)->tags[(port) >> 8], \
(ahd)->bshs[(port) >> 8], \
(port & 0xFF), valp, count)
static __inline void ahd_flush_device_writes(struct ahd_softc *);
static __inline void
ahd_flush_device_writes(struct ahd_softc *ahd)
{
/* XXX Is this sufficient for all architectures??? */
ahd_inb(ahd, INTSTAT);
}
/**************************** Locking Primitives ******************************/
/* Lock protecting internal data structures */
static __inline void ahd_lockinit(struct ahd_softc *);
static __inline void ahd_lock(struct ahd_softc *, unsigned long *flags);
static __inline void ahd_unlock(struct ahd_softc *, unsigned long *flags);
/* Lock held during command compeletion to the upper layer */
static __inline void ahd_done_lockinit(struct ahd_softc *);
static __inline void ahd_done_lock(struct ahd_softc *, unsigned long *flags);
static __inline void ahd_done_unlock(struct ahd_softc *, unsigned long *flags);
/* Lock held during ahc_list manipulation and ahc softc frees */
static __inline void ahd_list_lockinit(void);
static __inline void ahd_list_lock(unsigned long *flags);
static __inline void ahd_list_unlock(unsigned long *flags);
static __inline void
ahd_lockinit(struct ahd_softc *ahd)
{
}
static __inline void
ahd_lock(struct ahd_softc *ahd, unsigned long *flags)
{
*flags = splcam();
}
static __inline void
ahd_unlock(struct ahd_softc *ahd, unsigned long *flags)
{
splx(*flags);
}
/* Lock held during command compeletion to the upper layer */
static __inline void
ahd_done_lockinit(struct ahd_softc *ahd)
{
}
static __inline void
ahd_done_lock(struct ahd_softc *ahd, unsigned long *flags)
{
}
static __inline void
ahd_done_unlock(struct ahd_softc *ahd, unsigned long *flags)
{
}
/* Lock held during ahc_list manipulation and ahc softc frees */
static __inline void
ahd_list_lockinit()
{
}
static __inline void
ahd_list_lock(unsigned long *flags)
{
}
static __inline void
ahd_list_unlock(unsigned long *flags)
{
}
/****************************** OS Primitives *********************************/
#define ahd_delay DELAY
/************************** Transaction Operations ****************************/
static __inline void ahd_set_transaction_status(struct scb *, uint32_t);
static __inline void ahd_set_scsi_status(struct scb *, uint32_t);
static __inline uint32_t ahd_get_transaction_status(struct scb *);
static __inline uint32_t ahd_get_scsi_status(struct scb *);
static __inline void ahd_set_transaction_tag(struct scb *, int, u_int);
static __inline u_long ahd_get_transfer_length(struct scb *);
static __inline int ahd_get_transfer_dir(struct scb *);
static __inline void ahd_set_residual(struct scb *, u_long);
static __inline void ahd_set_sense_residual(struct scb *, u_long);
static __inline u_long ahd_get_residual(struct scb *);
static __inline int ahd_perform_autosense(struct scb *);
static __inline uint32_t ahd_get_sense_bufsize(struct ahd_softc*, struct scb*);
static __inline void ahd_freeze_simq(struct ahd_softc *);
static __inline void ahd_release_simq(struct ahd_softc *);
static __inline void ahd_freeze_ccb(union ccb *ccb);
static __inline void ahd_freeze_scb(struct scb *scb);
static __inline void ahd_platform_freeze_devq(struct ahd_softc *, struct scb *);
static __inline int ahd_platform_abort_scbs(struct ahd_softc *ahd, int target,
char channel, int lun, u_int tag,
role_t role, uint32_t status);
static __inline
void ahd_set_transaction_status(struct scb *scb, uint32_t status)
{
scb->io_ctx->ccb_h.status &= ~CAM_STATUS_MASK;
scb->io_ctx->ccb_h.status |= status;
}
static __inline
void ahd_set_scsi_status(struct scb *scb, uint32_t status)
{
scb->io_ctx->csio.scsi_status = status;
}
static __inline
uint32_t ahd_get_transaction_status(struct scb *scb)
{
return (scb->io_ctx->ccb_h.status & CAM_STATUS_MASK);
}
static __inline
uint32_t ahd_get_scsi_status(struct scb *scb)
{
return (scb->io_ctx->csio.scsi_status);
}
static __inline
void ahd_set_transaction_tag(struct scb *scb, int enabled, u_int type)
{
scb->io_ctx->csio.tag_action = type;
if (enabled)
scb->io_ctx->ccb_h.flags |= CAM_TAG_ACTION_VALID;
else
scb->io_ctx->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
}
static __inline
u_long ahd_get_transfer_length(struct scb *scb)
{
return (scb->io_ctx->csio.dxfer_len);
}
static __inline
int ahd_get_transfer_dir(struct scb *scb)
{
return (scb->io_ctx->ccb_h.flags & CAM_DIR_MASK);
}
static __inline
void ahd_set_residual(struct scb *scb, u_long resid)
{
scb->io_ctx->csio.resid = resid;
}
static __inline
void ahd_set_sense_residual(struct scb *scb, u_long resid)
{
scb->io_ctx->csio.sense_resid = resid;
}
static __inline
u_long ahd_get_residual(struct scb *scb)
{
return (scb->io_ctx->csio.resid);
}
static __inline
int ahd_perform_autosense(struct scb *scb)
{
return (!(scb->io_ctx->ccb_h.flags & CAM_DIS_AUTOSENSE));
}
static __inline uint32_t
ahd_get_sense_bufsize(struct ahd_softc *ahd, struct scb *scb)
{
return (sizeof(struct scsi_sense_data));
}
static __inline void
ahd_freeze_simq(struct ahd_softc *ahd)
{
xpt_freeze_simq(ahd->platform_data->sim, /*count*/1);
}
static __inline void
ahd_release_simq(struct ahd_softc *ahd)
{
xpt_release_simq(ahd->platform_data->sim, /*run queue*/TRUE);
}
static __inline void
ahd_freeze_ccb(union ccb *ccb)
{
if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) {
ccb->ccb_h.status |= CAM_DEV_QFRZN;
xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
}
}
static __inline void
ahd_freeze_scb(struct scb *scb)
{
ahd_freeze_ccb(scb->io_ctx);
}
static __inline void
ahd_platform_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
{
/* Nothing to do here for FreeBSD */
}
static __inline int
ahd_platform_abort_scbs(struct ahd_softc *ahd, int target,
char channel, int lun, u_int tag,
role_t role, uint32_t status)
{
/* Nothing to do here for FreeBSD */
return (0);
}
static __inline void
ahd_platform_scb_free(struct ahd_softc *ahd, struct scb *scb)
{
/* What do we do to generically handle driver resource shortages??? */
if ((ahd->flags & AHD_RESOURCE_SHORTAGE) != 0
&& scb->io_ctx != NULL
&& (scb->io_ctx->ccb_h.status & CAM_RELEASE_SIMQ) == 0) {
scb->io_ctx->ccb_h.status |= CAM_RELEASE_SIMQ;
ahd->flags &= ~AHD_RESOURCE_SHORTAGE;
}
scb->io_ctx = NULL;
}
/********************************** PCI ***************************************/
#ifdef AHD_PCI_CONFIG
static __inline uint32_t ahd_pci_read_config(ahd_dev_softc_t pci,
int reg, int width);
static __inline void ahd_pci_write_config(ahd_dev_softc_t pci,
int reg, uint32_t value,
int width);
static __inline int ahd_get_pci_function(ahd_dev_softc_t);
static __inline int ahd_get_pci_slot(ahd_dev_softc_t);
static __inline int ahd_get_pci_bus(ahd_dev_softc_t);
int ahd_pci_map_registers(struct ahd_softc *ahd);
int ahd_pci_map_int(struct ahd_softc *ahd);
static __inline uint32_t
ahd_pci_read_config(ahd_dev_softc_t pci, int reg, int width)
{
return (pci_read_config(pci, reg, width));
}
static __inline void
ahd_pci_write_config(ahd_dev_softc_t pci, int reg, uint32_t value, int width)
{
pci_write_config(pci, reg, value, width);
}
static __inline int
ahd_get_pci_function(ahd_dev_softc_t pci)
{
return (pci_get_function(pci));
}
static __inline int
ahd_get_pci_slot(ahd_dev_softc_t pci)
{
return (pci_get_slot(pci));
}
static __inline int
ahd_get_pci_bus(ahd_dev_softc_t pci)
{
return (pci_get_bus(pci));
}
typedef enum
{
AHD_POWER_STATE_D0,
AHD_POWER_STATE_D1,
AHD_POWER_STATE_D2,
AHD_POWER_STATE_D3
} ahd_power_state;
void ahd_power_state_change(struct ahd_softc *ahd,
ahd_power_state new_state);
#endif
/******************************** VL/EISA *************************************/
int aic7770_map_registers(struct ahd_softc *ahd);
int aic7770_map_int(struct ahd_softc *ahd, int irq);
/********************************* Debug **************************************/
static __inline void ahd_print_path(struct ahd_softc *, struct scb *);
static __inline void ahd_platform_dump_card_state(struct ahd_softc *ahd);
static __inline void
ahd_print_path(struct ahd_softc *ahd, struct scb *scb)
{
xpt_print_path(scb->io_ctx->ccb_h.path);
}
static __inline void
ahd_platform_dump_card_state(struct ahd_softc *ahd)
{
/* Nothing to do here for FreeBSD */
}
/**************************** Transfer Settings *******************************/
void ahd_notify_xfer_settings_change(struct ahd_softc *,
struct ahd_devinfo *);
void ahd_platform_set_tags(struct ahd_softc *, struct ahd_devinfo *,
int /*enable*/);
/************************* Initialization/Teardown ****************************/
int ahd_platform_alloc(struct ahd_softc *ahd, void *platform_arg);
void ahd_platform_free(struct ahd_softc *ahd);
int ahd_map_int(struct ahd_softc *ahd);
int ahd_attach(struct ahd_softc *);
int ahd_softc_comp(struct ahd_softc *lahd, struct ahd_softc *rahd);
int ahd_detach(device_t);
/****************************** Interrupts ************************************/
void ahd_platform_intr(void *);
static __inline void ahd_platform_flushwork(struct ahd_softc *ahd);
static __inline void
ahd_platform_flushwork(struct ahd_softc *ahd)
{
}
/************************ Misc Function Declarations **************************/
timeout_t ahd_timeout;
void ahd_done(struct ahd_softc *ahd, struct scb *scb);
void ahd_send_async(struct ahd_softc *, char /*channel*/,
u_int /*target*/, u_int /*lun*/, ac_code, void *arg);
#endif /* _AIC79XX_FREEBSD_H_ */

792
sys/dev/aic7xxx/aic79xx_pci.c Normal file
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@ -0,0 +1,792 @@
/*
* Product specific probe and attach routines for:
* aic7901 and aic7902 SCSI controllers
*
* Copyright (c) 1994-2001 Justin T. Gibbs.
* Copyright (c) 2000-2001 Adaptec Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGES.
*
* $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#32 $
*
* $FreeBSD$
*/
#ifdef __linux__
#include "aic79xx_osm.h"
#include "aic79xx_inline.h"
#else
#include <dev/aic7xxx/aic79xx_osm.h>
#include <dev/aic7xxx/aic79xx_inline.h>
#endif
static __inline uint64_t
ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
{
uint64_t id;
id = subvendor
| (subdevice << 16)
| ((uint64_t)vendor << 32)
| ((uint64_t)device << 48);
return (id);
}
#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
#define ID_AIC7901 0x800F9005FFFF9005ull
#define ID_AIC7901_IROC 0x80089005FFFF9005ull
#define ID_AHA_29320 0x8000900500609005ull
#define ID_AHA_29320LP 0x8000900500409005ull
#define ID_AIC7902 0x801F9005FFFF9005ull
#define ID_AIC7902_IROC 0x80189005FFFF9005ull
#define ID_AHA_39320 0x8010900500409005ull
#define ID_AHA_39320D 0x8011900500419005ull
#define ID_AHA_39320D_CPQ 0x8011900500AC0E11ull
#define ID_AIC7902_PCI_REV_A3 0x2
#define ID_AIC7902_PCI_REV_A4 0x3
#define ID_AIC7902_PCI_REV_B0 0xFF /* Rev Id not yet known. */
#define SUBID_CPQ 0x0E11
#define DEVID_9005_TYPE(id) ((id) & 0xF)
#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
#define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */
#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
#define DEVID_9005_MFUNC(id) ((id) & 0x10)
#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
#define SUBID_9005_TYPE(id) ((id) & 0xF)
#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
#define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
#define SUBID_9005_SEEPTYPE_NONE 0x0
#define SUBID_9005_SEEPTYPE_4K 0x1
static ahd_device_setup_t ahd_aic7901_setup;
static ahd_device_setup_t ahd_aic7902_setup;
struct ahd_pci_identity ahd_pci_ident_table [] =
{
/* aic7901 based controllers */
{
ID_AHA_29320,
ID_ALL_MASK,
"Adaptec 29320 Ultra320 SCSI adapter",
ahd_aic7901_setup
},
{
ID_AHA_29320LP,
ID_ALL_MASK,
"Adaptec 29320LP Ultra320 SCSI adapter",
ahd_aic7901_setup
},
/* aic7902 based controllers */
{
ID_AHA_39320,
ID_ALL_MASK,
"Adaptec 39320 Ultra320 SCSI adapter",
ahd_aic7902_setup
},
{
ID_AHA_39320D,
ID_ALL_MASK,
"Adaptec 39320D Ultra320 SCSI adapter",
ahd_aic7902_setup
},
{
ID_AHA_39320D_CPQ,
ID_ALL_MASK,
"Adaptec (Compaq OEM) 39320D Ultra320 SCSI adapter",
ahd_aic7902_setup
},
/* Generic chip probes for devices we don't know 'exactly' */
{
ID_AIC7901 & ID_9005_GENERIC_MASK,
ID_9005_GENERIC_MASK,
"Adaptec aic7901 Ultra320 SCSI adapter",
ahd_aic7901_setup
},
{
ID_AIC7902 & ID_9005_GENERIC_MASK,
ID_9005_GENERIC_MASK,
"Adaptec aic7902 Ultra320 SCSI adapter",
ahd_aic7902_setup
}
};
const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
#define DEVCONFIG 0x40
#define PCIXINITPAT 0x0000E000ul
#define PCIXINIT_PCI33_66 0x0000E000ul
#define PCIXINIT_PCIX50_66 0x0000C000ul
#define PCIXINIT_PCIX66_100 0x0000A000ul
#define PCIXINIT_PCIX100_133 0x00008000ul
#define PCI_BUS_MODES_INDEX(devconfig) \
(((devconfig) & PCIXINITPAT) >> 13)
static const char *pci_bus_modes[] =
{
"PCI bus mode unknown",
"PCI bus mode unknown",
"PCI bus mode unknown",
"PCI bus mode unknown",
"PCI-X 101-133Mhz",
"PCI-X 67-100Mhz",
"PCI-X 50-66Mhz",
"PCI 33 or 66Mhz"
};
#define TESTMODE 0x00000800ul
#define IRDY_RST 0x00000200ul
#define FRAME_RST 0x00000100ul
#define PCI64BIT 0x00000080ul
#define MRDCEN 0x00000040ul
#define ENDIANSEL 0x00000020ul
#define MIXQWENDIANEN 0x00000008ul
#define DACEN 0x00000004ul
#define STPWLEVEL 0x00000002ul
#define QWENDIANSEL 0x00000001ul
#define DEVCONFIG1 0x44
#define PREQDIS 0x01
#define CSIZE_LATTIME 0x0c
#define CACHESIZE 0x000000fful
#define LATTIME 0x0000ff00ul
static int ahd_check_extport(struct ahd_softc *ahd);
static void ahd_configure_termination(struct ahd_softc *ahd,
u_int adapter_control);
static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
struct ahd_pci_identity *
ahd_find_pci_device(ahd_dev_softc_t pci)
{
uint64_t full_id;
uint16_t device;
uint16_t vendor;
uint16_t subdevice;
uint16_t subvendor;
struct ahd_pci_identity *entry;
u_int i;
vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
full_id = ahd_compose_id(device,
vendor,
subdevice,
subvendor);
for (i = 0; i < ahd_num_pci_devs; i++) {
entry = &ahd_pci_ident_table[i];
if (entry->full_id == (full_id & entry->id_mask)) {
/* Honor exclusion entries. */
if (entry->name == NULL)
return (NULL);
return (entry);
}
}
return (NULL);
}
int
ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
{
struct scb_data *shared_scb_data;
u_long l;
u_long s;
u_int command;
uint32_t devconfig;
uint16_t subvendor;
int error;
shared_scb_data = NULL;
error = entry->setup(ahd);
if (error != 0)
return (error);
ahd->description = entry->name;
devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
ahd->chip |= AHD_PCI;
/* Disable PCIX workarounds when running in PCI mode. */
ahd->bugs &= ~AHD_PCIX_BUG_MASK;
} else {
ahd->chip |= AHD_PCIX;
}
ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
/*
* Record if this is a Compaq board.
*/
subvendor = ahd_pci_read_config(ahd->dev_softc,
PCIR_SUBVEND_0, /*bytes*/2);
if (subvendor == SUBID_CPQ)
ahd->flags |= AHD_CPQ_BOARD;
ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
error = ahd_pci_map_registers(ahd);
if (error != 0)
return (error);
/*
* If we need to support high memory, enable dual
* address cycles. This bit must be set to enable
* high address bit generation even if we are on a
* 64bit bus (PCI64BIT set in devconfig).
*/
if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
uint32_t devconfig;
if (bootverbose)
printf("%s: Enabling 39Bit Addressing\n",
ahd_name(ahd));
devconfig = ahd_pci_read_config(ahd->dev_softc,
DEVCONFIG, /*bytes*/4);
devconfig |= DACEN;
ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
devconfig, /*bytes*/4);
}
/* Ensure busmastering is enabled */
command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
command |= PCIM_CMD_BUSMASTEREN;
ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/1);
error = ahd_softc_init(ahd);
if (error != 0)
return (error);
ahd->bus_intr = ahd_pci_intr;
error = ahd_reset(ahd);
if (error != 0)
return (ENXIO);
ahd->pci_cachesize =
ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
/*bytes*/1) & CACHESIZE;
ahd->pci_cachesize *= 4;
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
/* See if we have a SEEPROM and perform auto-term */
error = ahd_check_extport(ahd);
if (error != 0)
return (error);
/* Core initialization */
error = ahd_init(ahd);
if (error != 0)
return (error);
/*
* Allow interrupts now that we are completely setup.
*/
error = ahd_pci_map_int(ahd);
if (error != 0)
return (error);
ahd_list_lock(&l);
/*
* Link this softc in with all other ahd instances.
*/
ahd_softc_insert(ahd);
ahd_lock(ahd, &s);
ahd_intr_enable(ahd, TRUE);
ahd_unlock(ahd, &s);
ahd_list_unlock(&l);
return (0);
}
/*
* Check the external port logic for a serial eeprom
* and termination/cable detection contrls.
*/
static int
ahd_check_extport(struct ahd_softc *ahd)
{
struct seeprom_config *sc;
u_int adapter_control;
int have_seeprom;
int error;
sc = ahd->seep_config;
have_seeprom = ahd_acquire_seeprom(ahd);
if (have_seeprom) {
u_int start_addr;
if (bootverbose)
printf("%s: Reading SEEPROM...", ahd_name(ahd));
/* Address is always in units of 16bit words */
start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
error = ahd_read_seeprom(ahd, (uint16_t *)sc,
start_addr, sizeof(*sc)/2);
if (error != 0) {
printf("Unable to read SEEPROM\n");
have_seeprom = 0;
} else {
have_seeprom = ahd_verify_cksum(sc);
if (bootverbose) {
if (have_seeprom == 0)
printf ("checksum error\n");
else
printf ("done.\n");
}
}
ahd_release_seeprom(ahd);
}
if (!have_seeprom) {
u_int nvram_scb;
/*
* Pull scratch ram settings and treat them as
* if they are the contents of an seeprom if
* the 'ADPT', 'BIOS', or 'ASPI' signature is found
* in SCB 0xFF. We manually compose the data as 16bit
* values to avoid endian issues.
*/
ahd_set_scbptr(ahd, 0xFF);
nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
printf("nvram_scb == 0x%x\n", nvram_scb);
printf("SCBPTR == 0x%x\n", ahd_get_scbptr(ahd));
printf("Signature = %c%c%c%c\n",
ahd_inb_scbram(ahd, SCB_BASE + 0),
ahd_inb_scbram(ahd, SCB_BASE + 1),
ahd_inb_scbram(ahd, SCB_BASE + 2),
ahd_inb_scbram(ahd, SCB_BASE + 3));
if (nvram_scb != 0xFF
&& ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
&& ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
&& ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
&& ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
|| (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
&& ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
&& ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
&& ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
|| (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
&& ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
&& ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
&& ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
uint16_t *sc_data;
int i;
ahd_set_scbptr(ahd, nvram_scb);
sc_data = (uint16_t *)sc;
for (i = 0; i < 64; i += 2)
*sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
have_seeprom = ahd_verify_cksum(sc);
if (have_seeprom)
ahd->flags |= AHD_SCB_CONFIG_USED;
}
}
#if AHD_DEBUG
if (have_seeprom != 0
&& (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
uint8_t *sc_data;
int i;
printf("%s: Seeprom Contents:", ahd_name(ahd));
sc_data = (uint8_t *)sc;
for (i = 0; i < (sizeof(*sc)); i += 2)
printf("\n\t0x%.4x",
sc_data[i] | (sc_data[i+1] << 8));
printf("\n");
}
#endif
if (!have_seeprom) {
if (bootverbose)
printf("%s: No SEEPROM available.\n", ahd_name(ahd));
ahd->flags |= AHD_USEDEFAULTS;
error = ahd_default_config(ahd);
adapter_control = CFAUTOTERM|CFSEAUTOTERM;
free(ahd->seep_config, M_DEVBUF);
ahd->seep_config = NULL;
} else {
error = ahd_parse_cfgdata(ahd, sc);
adapter_control = sc->adapter_control;
}
if (error != 0)
return (error);
ahd_configure_termination(ahd, adapter_control);
return (0);
}
static void
ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
{
int error;
u_int sxfrctl1;
uint8_t termctl;
uint32_t devconfig;
devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
devconfig &= ~STPWLEVEL;
if ((ahd->flags & AHD_STPWLEVEL_A) != 0) {
devconfig |= STPWLEVEL;
}
ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
/* Make sure current sensing is off. */
if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
(void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
}
/*
* Read to sense. Write to set.
*/
error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
if ((adapter_control & CFAUTOTERM) == 0) {
if (bootverbose)
printf("%s: Manual Primary Termination\n",
ahd_name(ahd));
termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
if ((adapter_control & CFSTERM) != 0)
termctl |= FLX_TERMCTL_ENPRILOW;
if ((adapter_control & CFWSTERM) != 0)
termctl |= FLX_TERMCTL_ENPRIHIGH;
} else if (error != 0) {
printf("%s: Primary Auto-Term Sensing failed! "
"Using Defaults.\n", ahd_name(ahd));
termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
}
if ((adapter_control & CFSEAUTOTERM) == 0) {
if (bootverbose)
printf("%s: Manual Secondary Termination\n",
ahd_name(ahd));
termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
if ((adapter_control & CFSELOWTERM) != 0)
termctl |= FLX_TERMCTL_ENSECLOW;
if ((adapter_control & CFSEHIGHTERM) != 0)
termctl |= FLX_TERMCTL_ENSECHIGH;
} else if (error != 0) {
printf("%s: Secondary Auto-Term Sensing failed! "
"Using Defaults.\n", ahd_name(ahd));
termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
}
/*
* Now set the termination based on what we found.
*/
sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
ahd->flags |= AHD_TERM_ENB_A;
sxfrctl1 |= STPWEN;
}
/* Must set the latch once in order to be effective. */
ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
ahd_outb(ahd, SXFRCTL1, sxfrctl1);
error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
if (error != 0) {
printf("%s: Unable to set termination settings!\n",
ahd_name(ahd));
} else if (bootverbose) {
printf("%s: Primary High byte termination %sabled\n",
ahd_name(ahd),
(termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
printf("%s: Primary Low byte termination %sabled\n",
ahd_name(ahd),
(termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
printf("%s: Secondary High byte termination %sabled\n",
ahd_name(ahd),
(termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
printf("%s: Secondary Low byte termination %sabled\n",
ahd_name(ahd),
(termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
}
return;
}
#define DPE 0x80
#define SSE 0x40
#define RMA 0x20
#define RTA 0x10
#define STA 0x08
#define DPR 0x01
static const char *split_status_source[] =
{
"DFF0",
"DFF1",
"OVLY",
"CMC",
};
static const char *pci_status_source[] =
{
"DFF0",
"DFF1",
"SG",
"CMC",
"OVLY",
"NONE",
"MSI",
"TARG"
};
static const char *split_status_strings[] =
{
"%s: Received split response in %s.\n"
"%s: Received split completion error message in %s\n",
"%s: Receive overrun in %s\n",
"%s: Count not complete in %s\n",
"%s: Split completion data bucket in %s\n",
"%s: Split completion address error in %s\n",
"%s: Split completion byte count error in %s\n",
"%s: Signaled Target-abort to early terminate a split in %s\n",
};
static const char *pci_status_strings[] =
{
"%s: Data Parity Error has been reported via PERR# in %s\n",
"%s: Target initial wait state error in %s\n",
"%s: Split completion read data parity error in %s\n",
"%s: Split completion address attribute parity error in %s\n",
"%s: Received a Target Abort in %s\n",
"%s: Received a Master Abort in %s\n",
"%s: Signal System Error Detected in %s\n",
"%s: Address or Write Phase Parity Error Detected in %s.\n"
};
void
ahd_pci_intr(struct ahd_softc *ahd)
{
uint8_t pci_status[8];
ahd_mode_state saved_modes;
u_int pci_status1;
u_int intstat;
u_int i;
u_int reg;
intstat = ahd_inb(ahd, INTSTAT);
if ((intstat & SPLTINT) != 0)
ahd_pci_split_intr(ahd, intstat);
if ((intstat & PCIINT) == 0)
return;
printf("%s: PCI error Interrupt\n", ahd_name(ahd));
saved_modes = ahd_save_modes(ahd);
ahd_dump_card_state(ahd);
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
if (i == 5)
continue;
pci_status[i] = ahd_inb(ahd, reg);
/* Clear latched errors. So our interupt deasserts. */
ahd_outb(ahd, reg, pci_status[i]);
}
for (i = 0; i < 8; i++) {
u_int bit;
if (i == 5)
continue;
for (bit = 0; bit < 8; bit++) {
if ((pci_status[i] & (0x1 << bit)) != 0) {
static const char *s;
s = pci_status_strings[bit];
if (i == 7/*TARG*/ && bit == 3)
s = "%s: Signal Target Abort\n";
printf(s, ahd_name(ahd), pci_status_source[i]);
}
}
}
pci_status1 = ahd_pci_read_config(ahd->dev_softc,
PCIR_STATUS + 1, /*bytes*/1);
ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
pci_status1, /*bytes*/1);
ahd_restore_modes(ahd, saved_modes);
ahd_unpause(ahd);
}
static void
ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
{
uint8_t split_status[4];
uint8_t split_status1[4];
uint8_t sg_split_status[2];
uint8_t sg_split_status1[2];
ahd_mode_state saved_modes;
u_int i;
uint16_t pcix_status;
/*
* Check for splits in all modes. Modes 0 and 1
* additionally have SG engine splits to look at.
*/
pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
/*bytes*/2);
printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
ahd_name(ahd), pcix_status);
saved_modes = ahd_save_modes(ahd);
for (i = 0; i < 4; i++) {
ahd_set_modes(ahd, i, i);
split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
/* Clear latched errors. So our interupt deasserts. */
ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
if (i != 0)
continue;
sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
/* Clear latched errors. So our interupt deasserts. */
ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
}
for (i = 0; i < 4; i++) {
u_int bit;
for (bit = 0; bit < 8; bit++) {
if ((split_status[i] & (0x1 << bit)) != 0) {
static const char *s;
s = split_status_strings[bit];
printf(s, ahd_name(ahd),
split_status_source[i]);
}
if (i != 0)
continue;
if ((sg_split_status[i] & (0x1 << bit)) != 0) {
static const char *s;
s = split_status_strings[bit];
printf(s, ahd_name(ahd), "SG");
}
}
}
/*
* Clear PCI-X status bits.
*/
ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
pcix_status, /*bytes*/2);
ahd_restore_modes(ahd, saved_modes);
}
static int
ahd_aic7901_setup(struct ahd_softc *ahd)
{
ahd_dev_softc_t pci;
pci = ahd->dev_softc;
ahd->channel = 'A';
ahd->chip = AHD_AIC7901;
ahd->features = AHD_AIC7901_FE;
return (0);
}
static int
ahd_aic7902_setup(struct ahd_softc *ahd)
{
ahd_dev_softc_t pci;
u_int rev;
u_int devconfig1;
pci = ahd->dev_softc;
rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
if (rev < ID_AIC7902_PCI_REV_A3) {
printf("%s: Unable to attach to unsupported chip revision %d\n",
ahd_name(ahd), rev);
ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/1);
return (ENXIO);
}
if (rev < ID_AIC7902_PCI_REV_B0) {
/*
* Pending request assertion does not work on the A if we have
* DMA requests outstanding on both channels. See H2A3 Razors
* #327 and #365.
*/
devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
ahd_pci_write_config(pci, DEVCONFIG1,
devconfig1|PREQDIS, /*bytes*/1);
devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
/*
* Enable A series workarounds.
*/
ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
| AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
| AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
| AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
| AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
| AHD_PCIX_CHIPRST_BUG|AHD_PKTIZED_STATUS_BUG;
if (rev < ID_AIC7902_PCI_REV_A4)
ahd->bugs |= AHD_PCIX_ARBITER_BUG|AHD_PCIX_SPLIT_BUG;
}
ahd->channel = ahd_get_pci_function(pci) + 'A';
ahd->chip = AHD_AIC7902;
ahd->features = AHD_AIC7902_FE;
return (0);
}